1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_APB_SARADC_REG_H_ 15 #define _SOC_APB_SARADC_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) 23 /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ 24 /*description: wait arbit signal stable after sar_done*/ 25 #define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 26 #define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) 27 #define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 28 #define APB_SARADC_WAIT_ARB_CYCLE_S 30 29 /* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ 30 /*description: force option to xpd sar blocks*/ 31 #define APB_SARADC_XPD_SAR_FORCE 0x00000003 32 #define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) 33 #define APB_SARADC_XPD_SAR_FORCE_V 0x3 34 #define APB_SARADC_XPD_SAR_FORCE_S 27 35 /* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ 36 /*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data 37 is from GPIO matrix*/ 38 #define APB_SARADC_DATA_TO_I2S (BIT(26)) 39 #define APB_SARADC_DATA_TO_I2S_M (BIT(26)) 40 #define APB_SARADC_DATA_TO_I2S_V 0x1 41 #define APB_SARADC_DATA_TO_I2S_S 26 42 /* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ 43 /*description: 1: sar_sel will be coded by the MSB of the 16-bit output data 44 in this case the resolution should not be larger than 11 bits.*/ 45 #define APB_SARADC_DATA_SAR_SEL (BIT(25)) 46 #define APB_SARADC_DATA_SAR_SEL_M (BIT(25)) 47 #define APB_SARADC_DATA_SAR_SEL_V 0x1 48 #define APB_SARADC_DATA_SAR_SEL_S 25 49 /* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ 50 /*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ 51 #define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) 52 #define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) 53 #define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1 54 #define APB_SARADC_SAR2_PATT_P_CLEAR_S 24 55 /* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ 56 /*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ 57 #define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) 58 #define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) 59 #define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1 60 #define APB_SARADC_SAR1_PATT_P_CLEAR_S 23 61 /* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ 62 /*description: 0 ~ 15 means length 1 ~ 16*/ 63 #define APB_SARADC_SAR2_PATT_LEN 0x0000000F 64 #define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S)) 65 #define APB_SARADC_SAR2_PATT_LEN_V 0xF 66 #define APB_SARADC_SAR2_PATT_LEN_S 19 67 /* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ 68 /*description: 0 ~ 15 means length 1 ~ 16*/ 69 #define APB_SARADC_SAR1_PATT_LEN 0x0000000F 70 #define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S)) 71 #define APB_SARADC_SAR1_PATT_LEN_V 0xF 72 #define APB_SARADC_SAR1_PATT_LEN_S 15 73 /* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ 74 /*description: SAR clock divider*/ 75 #define APB_SARADC_SAR_CLK_DIV 0x000000FF 76 #define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) 77 #define APB_SARADC_SAR_CLK_DIV_V 0xFF 78 #define APB_SARADC_SAR_CLK_DIV_S 7 79 /* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ 80 /*description: */ 81 #define APB_SARADC_SAR_CLK_GATED (BIT(6)) 82 #define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) 83 #define APB_SARADC_SAR_CLK_GATED_V 0x1 84 #define APB_SARADC_SAR_CLK_GATED_S 6 85 /* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ 86 /*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ 87 #define APB_SARADC_SAR_SEL (BIT(5)) 88 #define APB_SARADC_SAR_SEL_M (BIT(5)) 89 #define APB_SARADC_SAR_SEL_V 0x1 90 #define APB_SARADC_SAR_SEL_S 5 91 /* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ 92 /*description: 0: single mode 1: double mode 2: alternate mode*/ 93 #define APB_SARADC_WORK_MODE 0x00000003 94 #define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S)) 95 #define APB_SARADC_WORK_MODE_V 0x3 96 #define APB_SARADC_WORK_MODE_S 3 97 /* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ 98 /*description: */ 99 #define APB_SARADC_START (BIT(1)) 100 #define APB_SARADC_START_M (BIT(1)) 101 #define APB_SARADC_START_V 0x1 102 #define APB_SARADC_START_S 1 103 /* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ 104 /*description: */ 105 #define APB_SARADC_START_FORCE (BIT(0)) 106 #define APB_SARADC_START_FORCE_M (BIT(0)) 107 #define APB_SARADC_START_FORCE_V 0x1 108 #define APB_SARADC_START_FORCE_S 0 109 110 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) 111 /* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ 112 /*description: to enable saradc timer trigger*/ 113 #define APB_SARADC_TIMER_EN (BIT(24)) 114 #define APB_SARADC_TIMER_EN_M (BIT(24)) 115 #define APB_SARADC_TIMER_EN_V 0x1 116 #define APB_SARADC_TIMER_EN_S 24 117 /* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ 118 /*description: to set saradc timer target*/ 119 #define APB_SARADC_TIMER_TARGET 0x00000FFF 120 #define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) 121 #define APB_SARADC_TIMER_TARGET_V 0xFFF 122 #define APB_SARADC_TIMER_TARGET_S 12 123 /* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ 124 /*description: 1: select saradc timer 0: i2s_ws trigger*/ 125 #define APB_SARADC_TIMER_SEL (BIT(11)) 126 #define APB_SARADC_TIMER_SEL_M (BIT(11)) 127 #define APB_SARADC_TIMER_SEL_V 0x1 128 #define APB_SARADC_TIMER_SEL_S 11 129 /* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ 130 /*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ 131 #define APB_SARADC_SAR2_INV (BIT(10)) 132 #define APB_SARADC_SAR2_INV_M (BIT(10)) 133 #define APB_SARADC_SAR2_INV_V 0x1 134 #define APB_SARADC_SAR2_INV_S 10 135 /* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ 136 /*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ 137 #define APB_SARADC_SAR1_INV (BIT(9)) 138 #define APB_SARADC_SAR1_INV_M (BIT(9)) 139 #define APB_SARADC_SAR1_INV_V 0x1 140 #define APB_SARADC_SAR1_INV_S 9 141 /* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ 142 /*description: max conversion number*/ 143 #define APB_SARADC_MAX_MEAS_NUM 0x000000FF 144 #define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) 145 #define APB_SARADC_MAX_MEAS_NUM_V 0xFF 146 #define APB_SARADC_MAX_MEAS_NUM_S 1 147 /* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 148 /*description: */ 149 #define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) 150 #define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) 151 #define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 152 #define APB_SARADC_MEAS_NUM_LIMIT_S 0 153 154 #define APB_SARADC_FSM_REG (DR_REG_APB_SARADC_BASE + 0x008) 155 /* APB_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ 156 /*description: sample cycles*/ 157 #define APB_SARADC_SAMPLE_CYCLE 0x000000FF 158 #define APB_SARADC_SAMPLE_CYCLE_M ((APB_SARADC_SAMPLE_CYCLE_V)<<(APB_SARADC_SAMPLE_CYCLE_S)) 159 #define APB_SARADC_SAMPLE_CYCLE_V 0xFF 160 #define APB_SARADC_SAMPLE_CYCLE_S 24 161 /* APB_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */ 162 /*description: sample number*/ 163 #define APB_SARADC_SAMPLE_NUM 0x000000FF 164 #define APB_SARADC_SAMPLE_NUM_M ((APB_SARADC_SAMPLE_NUM_V)<<(APB_SARADC_SAMPLE_NUM_S)) 165 #define APB_SARADC_SAMPLE_NUM_V 0xFF 166 #define APB_SARADC_SAMPLE_NUM_S 16 167 168 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) 169 /* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ 170 /*description: */ 171 #define APB_SARADC_STANDBY_WAIT 0x000000FF 172 #define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) 173 #define APB_SARADC_STANDBY_WAIT_V 0xFF 174 #define APB_SARADC_STANDBY_WAIT_S 16 175 /* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ 176 /*description: */ 177 #define APB_SARADC_RSTB_WAIT 0x000000FF 178 #define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) 179 #define APB_SARADC_RSTB_WAIT_V 0xFF 180 #define APB_SARADC_RSTB_WAIT_S 8 181 /* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ 182 /*description: */ 183 #define APB_SARADC_XPD_WAIT 0x000000FF 184 #define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) 185 #define APB_SARADC_XPD_WAIT_V 0xFF 186 #define APB_SARADC_XPD_WAIT_S 0 187 188 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) 189 /* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ 190 /*description: */ 191 #define APB_SARADC_SAR1_STATUS 0xFFFFFFFF 192 #define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) 193 #define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF 194 #define APB_SARADC_SAR1_STATUS_S 0 195 196 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) 197 /* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ 198 /*description: */ 199 #define APB_SARADC_SAR2_STATUS 0xFFFFFFFF 200 #define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) 201 #define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF 202 #define APB_SARADC_SAR2_STATUS_S 0 203 204 #define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) 205 /* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 206 /*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ 207 #define APB_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF 208 #define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S)) 209 #define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF 210 #define APB_SARADC_SAR1_PATT_TAB1_S 0 211 212 #define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) 213 /* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 214 /*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ 215 #define APB_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF 216 #define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S)) 217 #define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF 218 #define APB_SARADC_SAR1_PATT_TAB2_S 0 219 220 #define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020) 221 /* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 222 /*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ 223 #define APB_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF 224 #define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S)) 225 #define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF 226 #define APB_SARADC_SAR1_PATT_TAB3_S 0 227 228 #define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024) 229 /* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 230 /*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ 231 #define APB_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF 232 #define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S)) 233 #define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF 234 #define APB_SARADC_SAR1_PATT_TAB4_S 0 235 236 #define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028) 237 /* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 238 /*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ 239 #define APB_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF 240 #define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S)) 241 #define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF 242 #define APB_SARADC_SAR2_PATT_TAB1_S 0 243 244 #define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C) 245 /* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 246 /*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ 247 #define APB_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF 248 #define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S)) 249 #define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF 250 #define APB_SARADC_SAR2_PATT_TAB2_S 0 251 252 #define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030) 253 /* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 254 /*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ 255 #define APB_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF 256 #define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S)) 257 #define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF 258 #define APB_SARADC_SAR2_PATT_TAB3_S 0 259 260 #define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034) 261 /* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ 262 /*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ 263 #define APB_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF 264 #define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S)) 265 #define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF 266 #define APB_SARADC_SAR2_PATT_TAB4_S 0 267 268 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) 269 /* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ 270 /*description: adc2 arbiter uses fixed priority*/ 271 #define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) 272 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) 273 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 274 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 275 /* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ 276 /*description: Set adc2 arbiter wifi priority*/ 277 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 278 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) 279 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 280 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 281 /* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ 282 /*description: Set adc2 arbiter rtc priority*/ 283 #define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 284 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) 285 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 286 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 287 /* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ 288 /*description: Set adc2 arbiterapb priority*/ 289 #define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 290 #define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) 291 #define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 292 #define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 293 /* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 294 /*description: adc2 arbiter force grant*/ 295 #define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) 296 #define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) 297 #define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 298 #define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 299 /* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 300 /*description: adc2 arbiter force to enable wifi controller*/ 301 #define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) 302 #define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) 303 #define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 304 #define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 305 /* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 306 /*description: adc2 arbiter force to enable rtc controller*/ 307 #define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) 308 #define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) 309 #define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 310 #define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 311 /* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 312 /*description: adc2 arbiter force to enableapb controller*/ 313 #define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) 314 #define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) 315 #define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 316 #define APB_SARADC_ADC_ARB_APB_FORCE_S 2 317 318 #define APB_SARADC_FILTER_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) 319 /* APB_SARADC_ADC1_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 320 /*description: enable apb_adc1_filter*/ 321 #define APB_SARADC_ADC1_FILTER_EN (BIT(31)) 322 #define APB_SARADC_ADC1_FILTER_EN_M (BIT(31)) 323 #define APB_SARADC_ADC1_FILTER_EN_V 0x1 324 #define APB_SARADC_ADC1_FILTER_EN_S 31 325 /* APB_SARADC_ADC2_FILTER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 326 /*description: enable apb_adc2_filter*/ 327 #define APB_SARADC_ADC2_FILTER_EN (BIT(30)) 328 #define APB_SARADC_ADC2_FILTER_EN_M (BIT(30)) 329 #define APB_SARADC_ADC2_FILTER_EN_V 0x1 330 #define APB_SARADC_ADC2_FILTER_EN_S 30 331 /* APB_SARADC_ADC1_FILTER_FACTOR : R/W ;bitpos:[29:23] ;default: 7'd64 ; */ 332 /*description: apb_adc1_filter_factor*/ 333 #define APB_SARADC_ADC1_FILTER_FACTOR 0x0000007F 334 #define APB_SARADC_ADC1_FILTER_FACTOR_M ((APB_SARADC_ADC1_FILTER_FACTOR_V)<<(APB_SARADC_ADC1_FILTER_FACTOR_S)) 335 #define APB_SARADC_ADC1_FILTER_FACTOR_V 0x7F 336 #define APB_SARADC_ADC1_FILTER_FACTOR_S 23 337 /* APB_SARADC_ADC2_FILTER_FACTOR : R/W ;bitpos:[22:16] ;default: 7'd64 ; */ 338 /*description: apb_adc2_filter_factor*/ 339 #define APB_SARADC_ADC2_FILTER_FACTOR 0x0000007F 340 #define APB_SARADC_ADC2_FILTER_FACTOR_M ((APB_SARADC_ADC2_FILTER_FACTOR_V)<<(APB_SARADC_ADC2_FILTER_FACTOR_S)) 341 #define APB_SARADC_ADC2_FILTER_FACTOR_V 0x7F 342 #define APB_SARADC_ADC2_FILTER_FACTOR_S 16 343 /* APB_SARADC_ADC1_FILTER_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ 344 /*description: reset_adc1_filter*/ 345 #define APB_SARADC_ADC1_FILTER_RESET (BIT(1)) 346 #define APB_SARADC_ADC1_FILTER_RESET_M (BIT(1)) 347 #define APB_SARADC_ADC1_FILTER_RESET_V 0x1 348 #define APB_SARADC_ADC1_FILTER_RESET_S 1 349 /* APB_SARADC_ADC2_FILTER_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */ 350 /*description: reset_adc2_filter*/ 351 #define APB_SARADC_ADC2_FILTER_RESET (BIT(0)) 352 #define APB_SARADC_ADC2_FILTER_RESET_M (BIT(0)) 353 #define APB_SARADC_ADC2_FILTER_RESET_V 0x1 354 #define APB_SARADC_ADC2_FILTER_RESET_S 0 355 356 #define APB_SARADC_FILTER_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040) 357 /* APB_SARADC_ADC1_FILTER_DATA : RO ;bitpos:[31:16] ;default: 16'd0 ; */ 358 /*description: */ 359 #define APB_SARADC_ADC1_FILTER_DATA 0x0000FFFF 360 #define APB_SARADC_ADC1_FILTER_DATA_M ((APB_SARADC_ADC1_FILTER_DATA_V)<<(APB_SARADC_ADC1_FILTER_DATA_S)) 361 #define APB_SARADC_ADC1_FILTER_DATA_V 0xFFFF 362 #define APB_SARADC_ADC1_FILTER_DATA_S 16 363 /* APB_SARADC_ADC2_FILTER_DATA : RO ;bitpos:[15:0] ;default: 16'd0 ; */ 364 /*description: */ 365 #define APB_SARADC_ADC2_FILTER_DATA 0x0000FFFF 366 #define APB_SARADC_ADC2_FILTER_DATA_M ((APB_SARADC_ADC2_FILTER_DATA_V)<<(APB_SARADC_ADC2_FILTER_DATA_S)) 367 #define APB_SARADC_ADC2_FILTER_DATA_V 0xFFFF 368 #define APB_SARADC_ADC2_FILTER_DATA_S 0 369 370 #define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044) 371 /* APB_SARADC_ADC1_THRES_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 372 /*description: */ 373 #define APB_SARADC_ADC1_THRES_EN (BIT(31)) 374 #define APB_SARADC_ADC1_THRES_EN_M (BIT(31)) 375 #define APB_SARADC_ADC1_THRES_EN_V 0x1 376 #define APB_SARADC_ADC1_THRES_EN_S 31 377 /* APB_SARADC_ADC2_THRES_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 378 /*description: */ 379 #define APB_SARADC_ADC2_THRES_EN (BIT(30)) 380 #define APB_SARADC_ADC2_THRES_EN_M (BIT(30)) 381 #define APB_SARADC_ADC2_THRES_EN_V 0x1 382 #define APB_SARADC_ADC2_THRES_EN_S 30 383 /* APB_SARADC_ADC1_THRES : R/W ;bitpos:[29:17] ;default: 13'd0 ; */ 384 /*description: */ 385 #define APB_SARADC_ADC1_THRES 0x00001FFF 386 #define APB_SARADC_ADC1_THRES_M ((APB_SARADC_ADC1_THRES_V)<<(APB_SARADC_ADC1_THRES_S)) 387 #define APB_SARADC_ADC1_THRES_V 0x1FFF 388 #define APB_SARADC_ADC1_THRES_S 17 389 /* APB_SARADC_ADC2_THRES : R/W ;bitpos:[16:4] ;default: 13'd0 ; */ 390 /*description: */ 391 #define APB_SARADC_ADC2_THRES 0x00001FFF 392 #define APB_SARADC_ADC2_THRES_M ((APB_SARADC_ADC2_THRES_V)<<(APB_SARADC_ADC2_THRES_S)) 393 #define APB_SARADC_ADC2_THRES_V 0x1FFF 394 #define APB_SARADC_ADC2_THRES_S 4 395 /* APB_SARADC_ADC1_THRES_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ 396 /*description: */ 397 #define APB_SARADC_ADC1_THRES_MODE (BIT(3)) 398 #define APB_SARADC_ADC1_THRES_MODE_M (BIT(3)) 399 #define APB_SARADC_ADC1_THRES_MODE_V 0x1 400 #define APB_SARADC_ADC1_THRES_MODE_S 3 401 /* APB_SARADC_ADC2_THRES_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ 402 /*description: */ 403 #define APB_SARADC_ADC2_THRES_MODE (BIT(2)) 404 #define APB_SARADC_ADC2_THRES_MODE_M (BIT(2)) 405 #define APB_SARADC_ADC2_THRES_MODE_V 0x1 406 #define APB_SARADC_ADC2_THRES_MODE_S 2 407 /* APB_SARADC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 408 /*description: */ 409 #define APB_SARADC_CLK_EN (BIT(0)) 410 #define APB_SARADC_CLK_EN_M (BIT(0)) 411 #define APB_SARADC_CLK_EN_V 0x1 412 #define APB_SARADC_CLK_EN_S 0 413 414 #define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x048) 415 /* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 416 /*description: */ 417 #define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) 418 #define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) 419 #define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 420 #define APB_SARADC_ADC1_DONE_INT_ENA_S 31 421 /* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ 422 /*description: */ 423 #define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) 424 #define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) 425 #define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 426 #define APB_SARADC_ADC2_DONE_INT_ENA_S 30 427 /* APB_SARADC_ADC1_THRES_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ 428 /*description: */ 429 #define APB_SARADC_ADC1_THRES_INT_ENA (BIT(29)) 430 #define APB_SARADC_ADC1_THRES_INT_ENA_M (BIT(29)) 431 #define APB_SARADC_ADC1_THRES_INT_ENA_V 0x1 432 #define APB_SARADC_ADC1_THRES_INT_ENA_S 29 433 /* APB_SARADC_ADC2_THRES_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ 434 /*description: */ 435 #define APB_SARADC_ADC2_THRES_INT_ENA (BIT(28)) 436 #define APB_SARADC_ADC2_THRES_INT_ENA_M (BIT(28)) 437 #define APB_SARADC_ADC2_THRES_INT_ENA_V 0x1 438 #define APB_SARADC_ADC2_THRES_INT_ENA_S 28 439 440 #define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x04C) 441 /* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ 442 /*description: */ 443 #define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) 444 #define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) 445 #define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 446 #define APB_SARADC_ADC1_DONE_INT_RAW_S 31 447 /* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ 448 /*description: */ 449 #define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) 450 #define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) 451 #define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 452 #define APB_SARADC_ADC2_DONE_INT_RAW_S 30 453 /* APB_SARADC_ADC1_THRES_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ 454 /*description: */ 455 #define APB_SARADC_ADC1_THRES_INT_RAW (BIT(29)) 456 #define APB_SARADC_ADC1_THRES_INT_RAW_M (BIT(29)) 457 #define APB_SARADC_ADC1_THRES_INT_RAW_V 0x1 458 #define APB_SARADC_ADC1_THRES_INT_RAW_S 29 459 /* APB_SARADC_ADC2_THRES_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ 460 /*description: */ 461 #define APB_SARADC_ADC2_THRES_INT_RAW (BIT(28)) 462 #define APB_SARADC_ADC2_THRES_INT_RAW_M (BIT(28)) 463 #define APB_SARADC_ADC2_THRES_INT_RAW_V 0x1 464 #define APB_SARADC_ADC2_THRES_INT_RAW_S 28 465 466 #define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x050) 467 /* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ 468 /*description: */ 469 #define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) 470 #define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) 471 #define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 472 #define APB_SARADC_ADC1_DONE_INT_ST_S 31 473 /* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ 474 /*description: */ 475 #define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) 476 #define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) 477 #define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 478 #define APB_SARADC_ADC2_DONE_INT_ST_S 30 479 /* APB_SARADC_ADC1_THRES_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ 480 /*description: */ 481 #define APB_SARADC_ADC1_THRES_INT_ST (BIT(29)) 482 #define APB_SARADC_ADC1_THRES_INT_ST_M (BIT(29)) 483 #define APB_SARADC_ADC1_THRES_INT_ST_V 0x1 484 #define APB_SARADC_ADC1_THRES_INT_ST_S 29 485 /* APB_SARADC_ADC2_THRES_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ 486 /*description: */ 487 #define APB_SARADC_ADC2_THRES_INT_ST (BIT(28)) 488 #define APB_SARADC_ADC2_THRES_INT_ST_M (BIT(28)) 489 #define APB_SARADC_ADC2_THRES_INT_ST_V 0x1 490 #define APB_SARADC_ADC2_THRES_INT_ST_S 28 491 492 #define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x054) 493 /* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ 494 /*description: */ 495 #define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) 496 #define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) 497 #define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 498 #define APB_SARADC_ADC1_DONE_INT_CLR_S 31 499 /* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ 500 /*description: */ 501 #define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) 502 #define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) 503 #define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 504 #define APB_SARADC_ADC2_DONE_INT_CLR_S 30 505 /* APB_SARADC_ADC1_THRES_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 506 /*description: */ 507 #define APB_SARADC_ADC1_THRES_INT_CLR (BIT(29)) 508 #define APB_SARADC_ADC1_THRES_INT_CLR_M (BIT(29)) 509 #define APB_SARADC_ADC1_THRES_INT_CLR_V 0x1 510 #define APB_SARADC_ADC1_THRES_INT_CLR_S 29 511 /* APB_SARADC_ADC2_THRES_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 512 /*description: */ 513 #define APB_SARADC_ADC2_THRES_INT_CLR (BIT(28)) 514 #define APB_SARADC_ADC2_THRES_INT_CLR_M (BIT(28)) 515 #define APB_SARADC_ADC2_THRES_INT_CLR_V 0x1 516 #define APB_SARADC_ADC2_THRES_INT_CLR_S 28 517 518 #define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x058) 519 /* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ 520 /*description: enable apb_adc use spi_dma*/ 521 #define APB_SARADC_APB_ADC_TRANS (BIT(31)) 522 #define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) 523 #define APB_SARADC_APB_ADC_TRANS_V 0x1 524 #define APB_SARADC_APB_ADC_TRANS_S 31 525 /* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ 526 /*description: reset_apb_adc_state*/ 527 #define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) 528 #define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) 529 #define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 530 #define APB_SARADC_APB_ADC_RESET_FSM_S 30 531 /* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ 532 /*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ 533 #define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF 534 #define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) 535 #define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF 536 #define APB_SARADC_APB_ADC_EOF_NUM_S 0 537 538 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x05c) 539 /* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ 540 /*description: Set this bit to enable clk_apll*/ 541 #define APB_SARADC_CLK_SEL 0x00000003 542 #define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) 543 #define APB_SARADC_CLK_SEL_V 0x3 544 #define APB_SARADC_CLK_SEL_S 21 545 /* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ 546 /*description: Fractional clock divider denominator value*/ 547 #define APB_SARADC_CLKM_DIV_A 0x0000003F 548 #define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) 549 #define APB_SARADC_CLKM_DIV_A_V 0x3F 550 #define APB_SARADC_CLKM_DIV_A_S 14 551 /* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ 552 /*description: Fractional clock divider numerator value*/ 553 #define APB_SARADC_CLKM_DIV_B 0x0000003F 554 #define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) 555 #define APB_SARADC_CLKM_DIV_B_V 0x3F 556 #define APB_SARADC_CLKM_DIV_B_S 8 557 /* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ 558 /*description: Integral I2S clock divider value*/ 559 #define APB_SARADC_CLKM_DIV_NUM 0x000000FF 560 #define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) 561 #define APB_SARADC_CLKM_DIV_NUM_V 0xFF 562 #define APB_SARADC_CLKM_DIV_NUM_S 0 563 564 #define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x060) 565 /* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 566 /*description: */ 567 #define APB_SARADC_APB_DAC_RST (BIT(16)) 568 #define APB_SARADC_APB_DAC_RST_M (BIT(16)) 569 #define APB_SARADC_APB_DAC_RST_V 0x1 570 #define APB_SARADC_APB_DAC_RST_S 16 571 /* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */ 572 /*description: */ 573 #define APB_SARADC_DAC_RESET_FIFO (BIT(15)) 574 #define APB_SARADC_DAC_RESET_FIFO_M (BIT(15)) 575 #define APB_SARADC_DAC_RESET_FIFO_V 0x1 576 #define APB_SARADC_DAC_RESET_FIFO_S 15 577 /* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */ 578 /*description: enable dma_dac*/ 579 #define APB_SARADC_APB_DAC_TRANS (BIT(14)) 580 #define APB_SARADC_APB_DAC_TRANS_M (BIT(14)) 581 #define APB_SARADC_APB_DAC_TRANS_V 0x1 582 #define APB_SARADC_APB_DAC_TRANS_S 14 583 /* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ 584 /*description: enable dac alter mode*/ 585 #define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13)) 586 #define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13)) 587 #define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1 588 #define APB_SARADC_APB_DAC_ALTER_MODE_S 13 589 /* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 590 /*description: enable read dac data*/ 591 #define APB_SARADC_DAC_TIMER_EN (BIT(12)) 592 #define APB_SARADC_DAC_TIMER_EN_M (BIT(12)) 593 #define APB_SARADC_DAC_TIMER_EN_V 0x1 594 #define APB_SARADC_DAC_TIMER_EN_S 12 595 /* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */ 596 /*description: dac_timer target*/ 597 #define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF 598 #define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V)<<(APB_SARADC_DAC_TIMER_TARGET_S)) 599 #define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF 600 #define APB_SARADC_DAC_TIMER_TARGET_S 0 601 602 #define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) 603 /* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h01907162 ; */ 604 /*description: */ 605 #define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF 606 #define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S)) 607 #define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF 608 #define APB_SARADC_APB_CTRL_DATE_S 0 609 610 #ifdef __cplusplus 611 } 612 #endif 613 614 615 616 #endif /*_SOC_APB_SARADC_REG_H_ */ 617
