1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_APB_SARADC_STRUCT_H_ 15 #define _SOC_APB_SARADC_STRUCT_H_ 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 typedef volatile struct { 21 union { 22 struct { 23 uint32_t start_force: 1; 24 uint32_t start: 1; 25 uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate mode*/ 26 uint32_t sar_clk_gated: 1; 27 uint32_t sar_clk_div: 8; /*SAR clock divider*/ 28 uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/ 29 uint32_t reserved18: 5; 30 uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ 31 uint32_t reserved24: 3; 32 uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ 33 uint32_t reserved29: 1; 34 uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ 35 }; 36 uint32_t val; 37 } ctrl; 38 union { 39 struct { 40 uint32_t meas_num_limit: 1; 41 uint32_t max_meas_num: 8; /*max conversion number*/ 42 uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ 43 uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ 44 uint32_t reserved11: 1; /*1: select saradc timer 0: i2s_ws trigger*/ 45 uint32_t timer_target: 12; /*to set saradc timer target*/ 46 uint32_t timer_en: 1; /*to enable saradc timer trigger*/ 47 uint32_t reserved25: 7; 48 }; 49 uint32_t val; 50 } ctrl2; 51 union { 52 struct { 53 uint32_t reserved0: 26; 54 uint32_t filter_factor1: 3; 55 uint32_t filter_factor0: 3; 56 }; 57 uint32_t val; 58 } filter_ctrl1; 59 union { 60 struct { 61 uint32_t xpd_wait: 8; 62 uint32_t rstb_wait: 8; 63 uint32_t standby_wait: 8; 64 uint32_t reserved24: 8; 65 }; 66 uint32_t val; 67 } fsm_wait; 68 uint32_t sar1_status; /**/ 69 uint32_t sar2_status; /**/ 70 union { 71 struct { 72 uint32_t sar_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ 73 uint32_t reserved24: 8; 74 }; 75 uint32_t val; 76 } sar_patt_tab[2]; 77 union { 78 struct { 79 uint32_t reserved0: 23; 80 uint32_t onetime_atten: 2; 81 uint32_t onetime_channel: 4; 82 uint32_t onetime_start: 1; 83 uint32_t adc2_onetime_sample: 1; 84 uint32_t adc1_onetime_sample: 1; 85 }; 86 uint32_t val; 87 } onetime_sample; 88 union { 89 struct { 90 uint32_t reserved0: 2; 91 uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ 92 uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ 93 uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ 94 uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ 95 uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ 96 uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ 97 uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ 98 uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ 99 uint32_t reserved13: 19; 100 }; 101 uint32_t val; 102 } apb_adc_arb_ctrl; 103 union { 104 struct { 105 uint32_t reserved0: 18; 106 uint32_t filter_channel1: 4; 107 uint32_t filter_channel0: 4; /*apb_adc1_filter_factor*/ 108 uint32_t reserved26: 5; 109 uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ 110 }; 111 uint32_t val; 112 } filter_ctrl0; 113 union { 114 struct { 115 uint32_t adc1_data: 17; 116 uint32_t reserved17:15; 117 }; 118 uint32_t val; 119 } apb_saradc1_data_status; 120 union { 121 struct { 122 uint32_t adc2_data: 17; 123 uint32_t reserved17:15; 124 }; 125 uint32_t val; 126 } apb_saradc2_data_status; 127 union { 128 struct { 129 uint32_t thres0_channel: 4; 130 uint32_t reserved4: 1; 131 uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ 132 uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ 133 uint32_t reserved31: 1; 134 }; 135 uint32_t val; 136 } thres0_ctrl; 137 union { 138 struct { 139 uint32_t thres1_channel: 4; 140 uint32_t reserved4: 1; 141 uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ 142 uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ 143 uint32_t reserved31: 1; 144 }; 145 uint32_t val; 146 } thres1_ctrl; 147 union { 148 struct { 149 uint32_t reserved0: 27; 150 uint32_t thres_all_en: 1; 151 uint32_t reserved28: 2; 152 uint32_t thres1_en: 1; 153 uint32_t thres0_en: 1; 154 }; 155 uint32_t val; 156 } thres_ctrl; 157 union { 158 struct { 159 uint32_t reserved0: 26; 160 uint32_t thres1_low: 1; 161 uint32_t thres0_low: 1; 162 uint32_t thres1_high: 1; 163 uint32_t thres0_high: 1; 164 uint32_t adc2_done: 1; 165 uint32_t adc1_done: 1; 166 }; 167 uint32_t val; 168 } int_ena; 169 union { 170 struct { 171 uint32_t reserved0: 26; 172 uint32_t thres1_low: 1; 173 uint32_t thres0_low: 1; 174 uint32_t thres1_high: 1; 175 uint32_t thres0_high: 1; 176 uint32_t adc2_done: 1; 177 uint32_t adc1_done: 1; 178 }; 179 uint32_t val; 180 } int_raw; 181 union { 182 struct { 183 uint32_t reserved0: 26; 184 uint32_t thres1_low: 1; 185 uint32_t thres0_low: 1; 186 uint32_t thres1_high: 1; 187 uint32_t thres0_high: 1; 188 uint32_t adc2_done: 1; 189 uint32_t adc1_done: 1; 190 }; 191 uint32_t val; 192 } int_st; 193 union { 194 struct { 195 uint32_t reserved0: 26; 196 uint32_t thres1_low: 1; 197 uint32_t thres0_low: 1; 198 uint32_t thres1_high: 1; 199 uint32_t thres0_high: 1; 200 uint32_t adc2_done: 1; 201 uint32_t adc1_done: 1; 202 }; 203 uint32_t val; 204 } int_clr; 205 union { 206 struct { 207 uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ 208 uint32_t reserved16: 14; 209 uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ 210 uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ 211 }; 212 uint32_t val; 213 } dma_conf; 214 union { 215 struct { 216 uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ 217 uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ 218 uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ 219 uint32_t clk_en: 1; 220 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ 221 uint32_t reserved23: 9; 222 }; 223 uint32_t val; 224 } apb_adc_clkm_conf; 225 union { 226 struct { 227 uint32_t tsens_out: 8; 228 uint32_t reserved8: 5; 229 uint32_t tsens_in_inv: 1; 230 uint32_t tsens_clk_div: 8; 231 uint32_t tsens_pu: 1; 232 uint32_t reserved23: 9; 233 }; 234 uint32_t val; 235 } apb_tsens_ctrl; 236 union { 237 struct { 238 uint32_t tsens_xpd_wait: 12; 239 uint32_t tsens_xpd_force: 2; 240 uint32_t tsens_clk_inv: 1; 241 uint32_t tsens_clk_sel: 1; 242 uint32_t reserved16: 16; 243 }; 244 uint32_t val; 245 } apb_tsens_ctrl2; 246 union { 247 struct { 248 uint32_t cali_cfg: 17; 249 uint32_t reserved17:15; 250 }; 251 uint32_t val; 252 } cali; 253 uint32_t reserved_64; 254 uint32_t reserved_68; 255 uint32_t reserved_6c; 256 uint32_t reserved_70; 257 uint32_t reserved_74; 258 uint32_t reserved_78; 259 uint32_t reserved_7c; 260 uint32_t reserved_80; 261 uint32_t reserved_84; 262 uint32_t reserved_88; 263 uint32_t reserved_8c; 264 uint32_t reserved_90; 265 uint32_t reserved_94; 266 uint32_t reserved_98; 267 uint32_t reserved_9c; 268 uint32_t reserved_a0; 269 uint32_t reserved_a4; 270 uint32_t reserved_a8; 271 uint32_t reserved_ac; 272 uint32_t reserved_b0; 273 uint32_t reserved_b4; 274 uint32_t reserved_b8; 275 uint32_t reserved_bc; 276 uint32_t reserved_c0; 277 uint32_t reserved_c4; 278 uint32_t reserved_c8; 279 uint32_t reserved_cc; 280 uint32_t reserved_d0; 281 uint32_t reserved_d4; 282 uint32_t reserved_d8; 283 uint32_t reserved_dc; 284 uint32_t reserved_e0; 285 uint32_t reserved_e4; 286 uint32_t reserved_e8; 287 uint32_t reserved_ec; 288 uint32_t reserved_f0; 289 uint32_t reserved_f4; 290 uint32_t reserved_f8; 291 uint32_t reserved_fc; 292 uint32_t reserved_100; 293 uint32_t reserved_104; 294 uint32_t reserved_108; 295 uint32_t reserved_10c; 296 uint32_t reserved_110; 297 uint32_t reserved_114; 298 uint32_t reserved_118; 299 uint32_t reserved_11c; 300 uint32_t reserved_120; 301 uint32_t reserved_124; 302 uint32_t reserved_128; 303 uint32_t reserved_12c; 304 uint32_t reserved_130; 305 uint32_t reserved_134; 306 uint32_t reserved_138; 307 uint32_t reserved_13c; 308 uint32_t reserved_140; 309 uint32_t reserved_144; 310 uint32_t reserved_148; 311 uint32_t reserved_14c; 312 uint32_t reserved_150; 313 uint32_t reserved_154; 314 uint32_t reserved_158; 315 uint32_t reserved_15c; 316 uint32_t reserved_160; 317 uint32_t reserved_164; 318 uint32_t reserved_168; 319 uint32_t reserved_16c; 320 uint32_t reserved_170; 321 uint32_t reserved_174; 322 uint32_t reserved_178; 323 uint32_t reserved_17c; 324 uint32_t reserved_180; 325 uint32_t reserved_184; 326 uint32_t reserved_188; 327 uint32_t reserved_18c; 328 uint32_t reserved_190; 329 uint32_t reserved_194; 330 uint32_t reserved_198; 331 uint32_t reserved_19c; 332 uint32_t reserved_1a0; 333 uint32_t reserved_1a4; 334 uint32_t reserved_1a8; 335 uint32_t reserved_1ac; 336 uint32_t reserved_1b0; 337 uint32_t reserved_1b4; 338 uint32_t reserved_1b8; 339 uint32_t reserved_1bc; 340 uint32_t reserved_1c0; 341 uint32_t reserved_1c4; 342 uint32_t reserved_1c8; 343 uint32_t reserved_1cc; 344 uint32_t reserved_1d0; 345 uint32_t reserved_1d4; 346 uint32_t reserved_1d8; 347 uint32_t reserved_1dc; 348 uint32_t reserved_1e0; 349 uint32_t reserved_1e4; 350 uint32_t reserved_1e8; 351 uint32_t reserved_1ec; 352 uint32_t reserved_1f0; 353 uint32_t reserved_1f4; 354 uint32_t reserved_1f8; 355 uint32_t reserved_1fc; 356 uint32_t reserved_200; 357 uint32_t reserved_204; 358 uint32_t reserved_208; 359 uint32_t reserved_20c; 360 uint32_t reserved_210; 361 uint32_t reserved_214; 362 uint32_t reserved_218; 363 uint32_t reserved_21c; 364 uint32_t reserved_220; 365 uint32_t reserved_224; 366 uint32_t reserved_228; 367 uint32_t reserved_22c; 368 uint32_t reserved_230; 369 uint32_t reserved_234; 370 uint32_t reserved_238; 371 uint32_t reserved_23c; 372 uint32_t reserved_240; 373 uint32_t reserved_244; 374 uint32_t reserved_248; 375 uint32_t reserved_24c; 376 uint32_t reserved_250; 377 uint32_t reserved_254; 378 uint32_t reserved_258; 379 uint32_t reserved_25c; 380 uint32_t reserved_260; 381 uint32_t reserved_264; 382 uint32_t reserved_268; 383 uint32_t reserved_26c; 384 uint32_t reserved_270; 385 uint32_t reserved_274; 386 uint32_t reserved_278; 387 uint32_t reserved_27c; 388 uint32_t reserved_280; 389 uint32_t reserved_284; 390 uint32_t reserved_288; 391 uint32_t reserved_28c; 392 uint32_t reserved_290; 393 uint32_t reserved_294; 394 uint32_t reserved_298; 395 uint32_t reserved_29c; 396 uint32_t reserved_2a0; 397 uint32_t reserved_2a4; 398 uint32_t reserved_2a8; 399 uint32_t reserved_2ac; 400 uint32_t reserved_2b0; 401 uint32_t reserved_2b4; 402 uint32_t reserved_2b8; 403 uint32_t reserved_2bc; 404 uint32_t reserved_2c0; 405 uint32_t reserved_2c4; 406 uint32_t reserved_2c8; 407 uint32_t reserved_2cc; 408 uint32_t reserved_2d0; 409 uint32_t reserved_2d4; 410 uint32_t reserved_2d8; 411 uint32_t reserved_2dc; 412 uint32_t reserved_2e0; 413 uint32_t reserved_2e4; 414 uint32_t reserved_2e8; 415 uint32_t reserved_2ec; 416 uint32_t reserved_2f0; 417 uint32_t reserved_2f4; 418 uint32_t reserved_2f8; 419 uint32_t reserved_2fc; 420 uint32_t reserved_300; 421 uint32_t reserved_304; 422 uint32_t reserved_308; 423 uint32_t reserved_30c; 424 uint32_t reserved_310; 425 uint32_t reserved_314; 426 uint32_t reserved_318; 427 uint32_t reserved_31c; 428 uint32_t reserved_320; 429 uint32_t reserved_324; 430 uint32_t reserved_328; 431 uint32_t reserved_32c; 432 uint32_t reserved_330; 433 uint32_t reserved_334; 434 uint32_t reserved_338; 435 uint32_t reserved_33c; 436 uint32_t reserved_340; 437 uint32_t reserved_344; 438 uint32_t reserved_348; 439 uint32_t reserved_34c; 440 uint32_t reserved_350; 441 uint32_t reserved_354; 442 uint32_t reserved_358; 443 uint32_t reserved_35c; 444 uint32_t reserved_360; 445 uint32_t reserved_364; 446 uint32_t reserved_368; 447 uint32_t reserved_36c; 448 uint32_t reserved_370; 449 uint32_t reserved_374; 450 uint32_t reserved_378; 451 uint32_t reserved_37c; 452 uint32_t reserved_380; 453 uint32_t reserved_384; 454 uint32_t reserved_388; 455 uint32_t reserved_38c; 456 uint32_t reserved_390; 457 uint32_t reserved_394; 458 uint32_t reserved_398; 459 uint32_t reserved_39c; 460 uint32_t reserved_3a0; 461 uint32_t reserved_3a4; 462 uint32_t reserved_3a8; 463 uint32_t reserved_3ac; 464 uint32_t reserved_3b0; 465 uint32_t reserved_3b4; 466 uint32_t reserved_3b8; 467 uint32_t reserved_3bc; 468 uint32_t reserved_3c0; 469 uint32_t reserved_3c4; 470 uint32_t reserved_3c8; 471 uint32_t reserved_3cc; 472 uint32_t reserved_3d0; 473 uint32_t reserved_3d4; 474 uint32_t reserved_3d8; 475 uint32_t reserved_3dc; 476 uint32_t reserved_3e0; 477 uint32_t reserved_3e4; 478 uint32_t reserved_3e8; 479 uint32_t reserved_3ec; 480 uint32_t reserved_3f0; 481 uint32_t reserved_3f4; 482 uint32_t reserved_3f8; 483 uint32_t apb_ctrl_date; /**/ 484 } apb_saradc_dev_t; 485 extern apb_saradc_dev_t APB_SARADC; 486 #ifdef __cplusplus 487 } 488 #endif 489 490 #endif /* _SOC_APB_SARADC_STRUCT_H_ */ 491
