1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RTC_CNTL_REG_H_ 15 #define _SOC_RTC_CNTL_REG_H_ 16 17 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ 18 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 19 /* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ 20 #define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A 21 22 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ 23 #define RTC_WDT_RESET_LENGTH_100_NS 0 24 #define RTC_WDT_RESET_LENGTH_200_NS 1 25 #define RTC_WDT_RESET_LENGTH_300_NS 2 26 #define RTC_WDT_RESET_LENGTH_400_NS 3 27 #define RTC_WDT_RESET_LENGTH_500_NS 4 28 #define RTC_WDT_RESET_LENGTH_800_NS 5 29 #define RTC_WDT_RESET_LENGTH_1600_NS 6 30 #define RTC_WDT_RESET_LENGTH_3200_NS 7 31 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 #include "soc.h" 37 #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG 38 #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG 39 40 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 41 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ 42 /*description: SW system reset*/ 43 #define RTC_CNTL_SW_SYS_RST (BIT(31)) 44 #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) 45 #define RTC_CNTL_SW_SYS_RST_V 0x1 46 #define RTC_CNTL_SW_SYS_RST_S 31 47 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ 48 /*description: digital core force no reset in deep sleep*/ 49 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) 50 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) 51 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 52 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 53 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ 54 /*description: digital wrap force reset in deep sleep*/ 55 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) 56 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) 57 #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 58 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 59 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ 60 /*description: */ 61 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) 62 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) 63 #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 64 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 65 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 66 /*description: */ 67 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) 68 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) 69 #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 70 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 71 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ 72 /*description: */ 73 #define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) 74 #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) 75 #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 76 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 77 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ 78 /*description: */ 79 #define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) 80 #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) 81 #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 82 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 83 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 84 /*description: */ 85 #define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) 86 #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) 87 #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 88 #define RTC_CNTL_PLL_FORCE_ISO_S 24 89 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ 90 /*description: */ 91 #define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) 92 #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) 93 #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 94 #define RTC_CNTL_XTL_FORCE_ISO_S 23 95 /* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 96 /*description: */ 97 #define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 98 #define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) 99 #define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 100 #define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 101 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ 102 /*description: wait bias_sleep and current source wakeup*/ 103 #define RTC_CNTL_XTL_EN_WAIT 0x0000000F 104 #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) 105 #define RTC_CNTL_XTL_EN_WAIT_V 0xF 106 #define RTC_CNTL_XTL_EN_WAIT_S 14 107 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ 108 /*description: crystall force power up*/ 109 #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) 110 #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) 111 #define RTC_CNTL_XTL_FORCE_PU_V 0x1 112 #define RTC_CNTL_XTL_FORCE_PU_S 13 113 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 114 /*description: crystall force power down*/ 115 #define RTC_CNTL_XTL_FORCE_PD (BIT(12)) 116 #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) 117 #define RTC_CNTL_XTL_FORCE_PD_V 0x1 118 #define RTC_CNTL_XTL_FORCE_PD_S 12 119 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ 120 /*description: BB_PLL force power up*/ 121 #define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) 122 #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) 123 #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 124 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 125 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 126 /*description: BB_PLL force power down*/ 127 #define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) 128 #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) 129 #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 130 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 131 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ 132 /*description: BB_PLL_I2C force power up*/ 133 #define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) 134 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) 135 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 136 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 137 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 138 /*description: BB_PLL _I2C force power down*/ 139 #define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) 140 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) 141 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 142 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 143 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ 144 /*description: BB_I2C force power up*/ 145 #define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) 146 #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) 147 #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 148 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 149 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 150 /*description: BB_I2C force power down*/ 151 #define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) 152 #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) 153 #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 154 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 155 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ 156 /*description: PRO CPU SW reset*/ 157 #define RTC_CNTL_SW_PROCPU_RST (BIT(5)) 158 #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) 159 #define RTC_CNTL_SW_PROCPU_RST_V 0x1 160 #define RTC_CNTL_SW_PROCPU_RST_S 5 161 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ 162 /*description: APP CPU SW reset*/ 163 #define RTC_CNTL_SW_APPCPU_RST (BIT(4)) 164 #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) 165 #define RTC_CNTL_SW_APPCPU_RST_V 0x1 166 #define RTC_CNTL_SW_APPCPU_RST_S 4 167 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 168 /*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 169 0x86 will stall PRO CPU*/ 170 #define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 171 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) 172 #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 173 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 174 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 175 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 176 0x86 will stall APP CPU*/ 177 #define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 178 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) 179 #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 180 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 181 182 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 183 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 184 /*description: */ 185 #define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF 186 #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) 187 #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF 188 #define RTC_CNTL_SLP_VAL_LO_S 0 189 190 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 191 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ 192 /*description: timer alarm enable bit*/ 193 #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) 194 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) 195 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 196 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 197 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 198 /*description: RTC sleep timer high 16 bits*/ 199 #define RTC_CNTL_SLP_VAL_HI 0x0000FFFF 200 #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) 201 #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF 202 #define RTC_CNTL_SLP_VAL_HI_S 0 203 204 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 205 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ 206 /*description: Set 1: to update register with RTC timer*/ 207 #define RTC_CNTL_TIME_UPDATE (BIT(31)) 208 #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) 209 #define RTC_CNTL_TIME_UPDATE_V 0x1 210 #define RTC_CNTL_TIME_UPDATE_S 31 211 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 212 /*description: enable to record system reset time*/ 213 #define RTC_CNTL_TIMER_SYS_RST (BIT(29)) 214 #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) 215 #define RTC_CNTL_TIMER_SYS_RST_V 0x1 216 #define RTC_CNTL_TIMER_SYS_RST_S 29 217 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ 218 /*description: Enable to record 40M XTAL OFF time*/ 219 #define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) 220 #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) 221 #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 222 #define RTC_CNTL_TIMER_XTL_OFF_S 28 223 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 224 /*description: Enable to record system stall time*/ 225 #define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) 226 #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) 227 #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 228 #define RTC_CNTL_TIMER_SYS_STALL_S 27 229 230 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 231 /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 232 /*description: RTC timer low 32 bits*/ 233 #define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF 234 #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) 235 #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF 236 #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 237 238 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 239 /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 240 /*description: RTC timer high 16 bits*/ 241 #define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF 242 #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) 243 #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF 244 #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 245 246 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 247 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 248 /*description: sleep enable bit*/ 249 #define RTC_CNTL_SLEEP_EN (BIT(31)) 250 #define RTC_CNTL_SLEEP_EN_M (BIT(31)) 251 #define RTC_CNTL_SLEEP_EN_V 0x1 252 #define RTC_CNTL_SLEEP_EN_S 31 253 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ 254 /*description: leep reject bit*/ 255 #define RTC_CNTL_SLP_REJECT (BIT(30)) 256 #define RTC_CNTL_SLP_REJECT_M (BIT(30)) 257 #define RTC_CNTL_SLP_REJECT_V 0x1 258 #define RTC_CNTL_SLP_REJECT_S 30 259 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ 260 /*description: leep wakeup bit*/ 261 #define RTC_CNTL_SLP_WAKEUP (BIT(29)) 262 #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) 263 #define RTC_CNTL_SLP_WAKEUP_V 0x1 264 #define RTC_CNTL_SLP_WAKEUP_S 29 265 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ 266 /*description: SDIO active indication*/ 267 #define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) 268 #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) 269 #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 270 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 271 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ 272 /*description: 1: APB to RTC using bridge*/ 273 #define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) 274 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) 275 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 276 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 277 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 278 /*description: clear rtc sleep reject cause*/ 279 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) 280 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) 281 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 282 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 283 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ 284 /*description: rtc software interrupt to main cpu*/ 285 #define RTC_CNTL_SW_CPU_INT (BIT(0)) 286 #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) 287 #define RTC_CNTL_SW_CPU_INT_V 0x1 288 #define RTC_CNTL_SW_CPU_INT_S 0 289 290 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 291 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ 292 /*description: PLL wait cycles in slow_clk_rtc*/ 293 #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF 294 #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) 295 #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF 296 #define RTC_CNTL_PLL_BUF_WAIT_S 24 297 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 298 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ 299 /*description: XTAL wait cycles in slow_clk_rtc*/ 300 #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF 301 #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) 302 #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF 303 #define RTC_CNTL_XTL_BUF_WAIT_S 14 304 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 305 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ 306 /*description: CK8M wait cycles in slow_clk_rtc*/ 307 #define RTC_CNTL_CK8M_WAIT 0x000000FF 308 #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) 309 #define RTC_CNTL_CK8M_WAIT_V 0xFF 310 #define RTC_CNTL_CK8M_WAIT_S 6 311 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 312 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ 313 /*description: CPU stall wait cycles in fast_clk_rtc*/ 314 #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F 315 #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) 316 #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F 317 #define RTC_CNTL_CPU_STALL_WAIT_S 1 318 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ 319 /*description: CPU stall enable bit*/ 320 #define RTC_CNTL_CPU_STALL_EN (BIT(0)) 321 #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) 322 #define RTC_CNTL_CPU_STALL_EN_V 0x1 323 #define RTC_CNTL_CPU_STALL_EN_S 0 324 325 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 326 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 327 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ 328 #define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF 329 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) 330 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF 331 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 332 333 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) 334 /* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ 335 /*description: */ 336 #define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F 337 #define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) 338 #define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F 339 #define RTC_CNTL_BT_POWERUP_TIMER_S 25 340 /* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ 341 /*description: */ 342 #define RTC_CNTL_BT_WAIT_TIMER 0x000001FF 343 #define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) 344 #define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF 345 #define RTC_CNTL_BT_WAIT_TIMER_S 16 346 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 347 /*description: */ 348 #define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F 349 #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) 350 #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F 351 #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 352 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 353 /*description: */ 354 #define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF 355 #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) 356 #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF 357 #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 358 359 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) 360 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 361 /*description: */ 362 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F 363 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) 364 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F 365 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 366 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 367 /*description: */ 368 #define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF 369 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) 370 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF 371 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 372 /* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 373 /*description: */ 374 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F 375 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) 376 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F 377 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 378 /* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 379 /*description: */ 380 #define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF 381 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) 382 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF 383 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 384 385 #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) 386 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ 387 /*description: minimal sleep cycles in slow_clk_rtc*/ 388 #define RTC_CNTL_MIN_SLP_VAL 0x000000FF 389 #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) 390 #define RTC_CNTL_MIN_SLP_VAL_V 0xFF 391 #define RTC_CNTL_MIN_SLP_VAL_S 8 392 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 393 394 #define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) 395 /* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ 396 /*description: */ 397 #define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F 398 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) 399 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F 400 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 401 /* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ 402 /*description: */ 403 #define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF 404 #define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) 405 #define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF 406 #define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 407 408 #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) 409 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ 410 /*description: */ 411 #define RTC_CNTL_PLL_I2C_PU (BIT(31)) 412 #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) 413 #define RTC_CNTL_PLL_I2C_PU_V 0x1 414 #define RTC_CNTL_PLL_I2C_PU_S 31 415 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ 416 /*description: 1: CKGEN_I2C power up*/ 417 #define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) 418 #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) 419 #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 420 #define RTC_CNTL_CKGEN_I2C_PU_S 30 421 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ 422 /*description: 1: RFRX_PBUS power up*/ 423 #define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) 424 #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) 425 #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 426 #define RTC_CNTL_RFRX_PBUS_PU_S 28 427 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ 428 /*description: 1: TXRF_I2C power up*/ 429 #define RTC_CNTL_TXRF_I2C_PU (BIT(27)) 430 #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) 431 #define RTC_CNTL_TXRF_I2C_PU_V 0x1 432 #define RTC_CNTL_TXRF_I2C_PU_S 27 433 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ 434 /*description: 1: PVTMON power up*/ 435 #define RTC_CNTL_PVTMON_PU (BIT(26)) 436 #define RTC_CNTL_PVTMON_PU_M (BIT(26)) 437 #define RTC_CNTL_PVTMON_PU_V 0x1 438 #define RTC_CNTL_PVTMON_PU_S 26 439 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ 440 /*description: start BBPLL calibration during sleep*/ 441 #define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) 442 #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) 443 #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 444 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 445 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 446 /*description: PLLA force power up*/ 447 #define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) 448 #define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) 449 #define RTC_CNTL_PLLA_FORCE_PU_V 0x1 450 #define RTC_CNTL_PLLA_FORCE_PU_S 24 451 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ 452 /*description: PLLA force power down*/ 453 #define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) 454 #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) 455 #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 456 #define RTC_CNTL_PLLA_FORCE_PD_S 23 457 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ 458 /*description: PLLA force power up*/ 459 #define RTC_CNTL_SAR_I2C_PU (BIT(22)) 460 #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) 461 #define RTC_CNTL_SAR_I2C_PU_V 0x1 462 #define RTC_CNTL_SAR_I2C_PU_S 22 463 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 464 /*description: */ 465 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) 466 #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) 467 #define RTC_CNTL_GLITCH_RST_EN_V 0x1 468 #define RTC_CNTL_GLITCH_RST_EN_S 20 469 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 470 /*description: */ 471 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) 472 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) 473 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 474 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 475 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ 476 /*description: */ 477 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) 478 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) 479 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 480 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 481 482 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) 483 /* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ 484 /*description: */ 485 #define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) 486 #define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) 487 #define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 488 #define RTC_CNTL_DRESET_MASK_PROCPU_S 25 489 /* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 490 /*description: */ 491 #define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) 492 #define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) 493 #define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 494 #define RTC_CNTL_DRESET_MASK_APPCPU_S 24 495 /* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ 496 /*description: */ 497 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) 498 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) 499 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 500 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 501 /* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ 502 /*description: */ 503 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) 504 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) 505 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 506 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 507 /* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ 508 /*description: */ 509 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) 510 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) 511 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 512 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 513 /* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ 514 /*description: */ 515 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) 516 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) 517 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 518 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 519 /* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 520 /*description: PROCPU OcdHaltOnReset*/ 521 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) 522 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) 523 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 524 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 525 /* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ 526 /*description: APPCPU OcdHaltOnReset*/ 527 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) 528 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) 529 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 530 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 531 /* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ 532 /*description: clear APP CPU reset flag*/ 533 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) 534 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) 535 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 536 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 537 /* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ 538 /*description: clear PRO CPU reset_flag*/ 539 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) 540 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) 541 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 542 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 543 /* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ 544 /*description: APP CPU reset flag*/ 545 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) 546 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) 547 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 548 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 549 /* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ 550 /*description: PRO CPU reset_flag*/ 551 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) 552 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) 553 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 554 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 555 /* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ 556 /*description: PRO CPU state vector sel*/ 557 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) 558 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) 559 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 560 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 561 /* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ 562 /*description: APP CPU state vector sel*/ 563 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) 564 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) 565 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 566 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 567 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ 568 /*description: reset cause of APP CPU*/ 569 #define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F 570 #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) 571 #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F 572 #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 573 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ 574 /*description: reset cause of PRO CPU*/ 575 #define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F 576 #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) 577 #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F 578 #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 579 580 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) 581 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ 582 /*description: wakeup enable bitmap*/ 583 #define RTC_CNTL_WAKEUP_ENA 0x0001FFFF 584 #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) 585 #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF 586 #define RTC_CNTL_WAKEUP_ENA_S 15 587 588 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) 589 /* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ 590 /*description: */ 591 #define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) 592 #define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) 593 #define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 594 #define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 595 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 596 /*description: enbale gitch det interrupt*/ 597 #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) 598 #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) 599 #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 600 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 601 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 602 /*description: enable xtal32k_dead interrupt*/ 603 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) 604 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) 605 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 606 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 607 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 608 /*description: enable super watch dog interrupt*/ 609 #define RTC_CNTL_SWD_INT_ENA (BIT(15)) 610 #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) 611 #define RTC_CNTL_SWD_INT_ENA_V 0x1 612 #define RTC_CNTL_SWD_INT_ENA_S 15 613 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 614 /*description: enable RTC main timer interrupt*/ 615 #define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) 616 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) 617 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 618 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 619 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 620 /*description: enable brown out interrupt*/ 621 #define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) 622 #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) 623 #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 624 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 625 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 626 /*description: enable RTC WDT interrupt*/ 627 #define RTC_CNTL_WDT_INT_ENA (BIT(3)) 628 #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) 629 #define RTC_CNTL_WDT_INT_ENA_V 0x1 630 #define RTC_CNTL_WDT_INT_ENA_S 3 631 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 632 /*description: enable sleep reject interrupt*/ 633 #define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) 634 #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) 635 #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 636 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 637 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 638 /*description: enable sleep wakeup interrupt*/ 639 #define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) 640 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) 641 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 642 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 643 644 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) 645 /* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ 646 /*description: */ 647 #define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) 648 #define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) 649 #define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 650 #define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 651 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 652 /*description: glitch_det_interrupt_raw*/ 653 #define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) 654 #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) 655 #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 656 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 657 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 658 /*description: xtal32k dead detection interrupt raw*/ 659 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) 660 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) 661 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 662 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 663 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 664 /*description: super watch dog interrupt raw*/ 665 #define RTC_CNTL_SWD_INT_RAW (BIT(15)) 666 #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) 667 #define RTC_CNTL_SWD_INT_RAW_V 0x1 668 #define RTC_CNTL_SWD_INT_RAW_S 15 669 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 670 /*description: RTC main timer interrupt raw*/ 671 #define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) 672 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) 673 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 674 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 675 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 676 /*description: brown out interrupt raw*/ 677 #define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) 678 #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) 679 #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 680 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 681 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 682 /*description: RTC WDT interrupt raw*/ 683 #define RTC_CNTL_WDT_INT_RAW (BIT(3)) 684 #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) 685 #define RTC_CNTL_WDT_INT_RAW_V 0x1 686 #define RTC_CNTL_WDT_INT_RAW_S 3 687 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 688 /*description: sleep reject interrupt raw*/ 689 #define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) 690 #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) 691 #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 692 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 693 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 694 /*description: sleep wakeup interrupt raw*/ 695 #define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) 696 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) 697 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 698 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 699 700 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) 701 /* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ 702 /*description: */ 703 #define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) 704 #define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) 705 #define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 706 #define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 707 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 708 /*description: glitch_det_interrupt state*/ 709 #define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) 710 #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) 711 #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 712 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 713 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 714 /*description: xtal32k dead detection interrupt state*/ 715 #define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) 716 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) 717 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 718 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 719 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 720 /*description: super watch dog interrupt state*/ 721 #define RTC_CNTL_SWD_INT_ST (BIT(15)) 722 #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) 723 #define RTC_CNTL_SWD_INT_ST_V 0x1 724 #define RTC_CNTL_SWD_INT_ST_S 15 725 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 726 /*description: RTC main timer interrupt state*/ 727 #define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) 728 #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) 729 #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 730 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 731 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 732 /*description: brown out interrupt state*/ 733 #define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) 734 #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) 735 #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 736 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 737 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 738 /*description: RTC WDT interrupt state*/ 739 #define RTC_CNTL_WDT_INT_ST (BIT(3)) 740 #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) 741 #define RTC_CNTL_WDT_INT_ST_V 0x1 742 #define RTC_CNTL_WDT_INT_ST_S 3 743 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 744 /*description: sleep reject interrupt state*/ 745 #define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) 746 #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) 747 #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 748 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 749 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 750 /*description: sleep wakeup interrupt state*/ 751 #define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) 752 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) 753 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 754 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 755 756 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) 757 /* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ 758 /*description: */ 759 #define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) 760 #define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) 761 #define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 762 #define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 763 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 764 /*description: Clear glitch det interrupt state*/ 765 #define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) 766 #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) 767 #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 768 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 769 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 770 /*description: Clear RTC WDT interrupt state*/ 771 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) 772 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) 773 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 774 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 775 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 776 /*description: Clear super watch dog interrupt state*/ 777 #define RTC_CNTL_SWD_INT_CLR (BIT(15)) 778 #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) 779 #define RTC_CNTL_SWD_INT_CLR_V 0x1 780 #define RTC_CNTL_SWD_INT_CLR_S 15 781 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 782 /*description: Clear RTC main timer interrupt state*/ 783 #define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) 784 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) 785 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 786 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 787 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 788 /*description: Clear brown out interrupt state*/ 789 #define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) 790 #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) 791 #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 792 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 793 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 794 /*description: Clear RTC WDT interrupt state*/ 795 #define RTC_CNTL_WDT_INT_CLR (BIT(3)) 796 #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) 797 #define RTC_CNTL_WDT_INT_CLR_V 0x1 798 #define RTC_CNTL_WDT_INT_CLR_S 3 799 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 800 /*description: Clear sleep reject interrupt state*/ 801 #define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) 802 #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) 803 #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 804 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 805 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 806 /*description: Clear sleep wakeup interrupt state*/ 807 #define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) 808 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) 809 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 810 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 811 812 #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) 813 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ 814 /*description: */ 815 #define RTC_CNTL_SCRATCH0 0xFFFFFFFF 816 #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) 817 #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF 818 #define RTC_CNTL_SCRATCH0_S 0 819 820 #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) 821 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ 822 /*description: */ 823 #define RTC_CNTL_SCRATCH1 0xFFFFFFFF 824 #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) 825 #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF 826 #define RTC_CNTL_SCRATCH1_S 0 827 828 #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) 829 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ 830 /*description: */ 831 #define RTC_CNTL_SCRATCH2 0xFFFFFFFF 832 #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) 833 #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF 834 #define RTC_CNTL_SCRATCH2_S 0 835 836 #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) 837 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ 838 /*description: */ 839 #define RTC_CNTL_SCRATCH3 0xFFFFFFFF 840 #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) 841 #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF 842 #define RTC_CNTL_SCRATCH3_S 0 843 844 #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) 845 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 846 /*description: */ 847 #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) 848 #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) 849 #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 850 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 851 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 852 /*description: 0: power down XTAL at high level*/ 853 #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) 854 #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) 855 #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 856 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 857 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ 858 /*description: XTAL_32K sel. 0: external XTAL_32K*/ 859 #define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) 860 #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) 861 #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 862 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 863 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ 864 /*description: state of 32k_wdt*/ 865 #define RTC_CNTL_WDT_STATE 0x00000007 866 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) 867 #define RTC_CNTL_WDT_STATE_V 0x7 868 #define RTC_CNTL_WDT_STATE_S 20 869 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ 870 /*description: DAC_XTAL_32K*/ 871 #define RTC_CNTL_DAC_XTAL_32K 0x00000007 872 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) 873 #define RTC_CNTL_DAC_XTAL_32K_V 0x7 874 #define RTC_CNTL_DAC_XTAL_32K_S 17 875 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ 876 /*description: XPD_XTAL_32K*/ 877 #define RTC_CNTL_XPD_XTAL_32K (BIT(16)) 878 #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) 879 #define RTC_CNTL_XPD_XTAL_32K_V 0x1 880 #define RTC_CNTL_XPD_XTAL_32K_S 16 881 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ 882 /*description: DRES_XTAL_32K*/ 883 #define RTC_CNTL_DRES_XTAL_32K 0x00000007 884 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) 885 #define RTC_CNTL_DRES_XTAL_32K_V 0x7 886 #define RTC_CNTL_DRES_XTAL_32K_S 13 887 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ 888 /*description: xtal_32k gm control*/ 889 #define RTC_CNTL_DGM_XTAL_32K 0x00000007 890 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) 891 #define RTC_CNTL_DGM_XTAL_32K_V 0x7 892 #define RTC_CNTL_DGM_XTAL_32K_S 10 893 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ 894 /*description: 0: single-end buffer 1: differential buffer*/ 895 #define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) 896 #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) 897 #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 898 #define RTC_CNTL_DBUF_XTAL_32K_S 9 899 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ 900 /*description: apply an internal clock to help xtal 32k to start*/ 901 #define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) 902 #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) 903 #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 904 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 905 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ 906 /*description: Xtal 32k xpd control by sw or fsm*/ 907 #define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) 908 #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) 909 #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 910 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 911 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 912 /*description: xtal 32k switch back xtal when xtal is restarted*/ 913 #define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) 914 #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) 915 #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 916 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 917 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ 918 /*description: xtal 32k restart xtal when xtal is dead*/ 919 #define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) 920 #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) 921 #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 922 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 923 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 924 /*description: xtal 32k switch to back up clock when xtal is dead*/ 925 #define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) 926 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) 927 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 928 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 929 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 930 /*description: xtal 32k external xtal clock force on*/ 931 #define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) 932 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) 933 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 934 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 935 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 936 /*description: xtal 32k watch dog sw reset*/ 937 #define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) 938 #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) 939 #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 940 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 941 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 942 /*description: xtal 32k watch dog clock force on*/ 943 #define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) 944 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) 945 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 946 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 947 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 948 /*description: xtal 32k watch dog enable*/ 949 #define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) 950 #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) 951 #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 952 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 953 954 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) 955 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ 956 /*description: enable filter for gpio wakeup event*/ 957 #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) 958 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) 959 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 960 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 961 962 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) 963 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 964 /*description: enable reject for deep sleep*/ 965 #define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) 966 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) 967 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 968 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 969 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 970 /*description: enable reject for light sleep*/ 971 #define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) 972 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) 973 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 974 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 975 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ 976 /*description: sleep reject enable*/ 977 #define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF 978 #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) 979 #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF 980 #define RTC_CNTL_SLEEP_REJECT_ENA_S 12 981 982 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) 983 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ 984 /*description: */ 985 #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 986 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) 987 #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 988 #define RTC_CNTL_CPUPERIOD_SEL_S 30 989 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ 990 /*description: CPU sel option*/ 991 #define RTC_CNTL_CPUSEL_CONF (BIT(29)) 992 #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) 993 #define RTC_CNTL_CPUSEL_CONF_V 0x1 994 #define RTC_CNTL_CPUSEL_CONF_S 29 995 996 #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) 997 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 998 /*description: */ 999 #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 1000 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) 1001 #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 1002 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 1003 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1004 /*description: fast_clk_rtc sel. 0: XTAL div 4*/ 1005 #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) 1006 #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) 1007 #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 1008 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 1009 /* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ 1010 /*description: */ 1011 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) 1012 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) 1013 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 1014 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 1015 /* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1016 /*description: */ 1017 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) 1018 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) 1019 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 1020 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 1021 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1022 /*description: CK8M force power up*/ 1023 #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) 1024 #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) 1025 #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 1026 #define RTC_CNTL_CK8M_FORCE_PU_S 26 1027 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ 1028 /*description: CK8M force power down*/ 1029 #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) 1030 #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) 1031 #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 1032 #define RTC_CNTL_CK8M_FORCE_PD_S 25 1033 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ 1034 /*description: CK8M_DFREQ*/ 1035 #define RTC_CNTL_CK8M_DFREQ 0x000000FF 1036 #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) 1037 #define RTC_CNTL_CK8M_DFREQ_V 0xFF 1038 #define RTC_CNTL_CK8M_DFREQ_S 17 1039 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1040 /*description: CK8M force no gating during sleep*/ 1041 #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) 1042 #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) 1043 #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 1044 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 1045 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1046 /*description: XTAL force no gating during sleep*/ 1047 #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) 1048 #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) 1049 #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 1050 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 1051 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ 1052 /*description: divider = reg_ck8m_div_sel + 1*/ 1053 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 1054 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) 1055 #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 1056 #define RTC_CNTL_CK8M_DIV_SEL_S 12 1057 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1058 /*description: enable CK8M for digital core (no relationship with RTC core)*/ 1059 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) 1060 #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) 1061 #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 1062 #define RTC_CNTL_DIG_CLK8M_EN_S 10 1063 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1064 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ 1065 #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) 1066 #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) 1067 #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 1068 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 1069 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1070 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ 1071 #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) 1072 #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) 1073 #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 1074 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 1075 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1076 /*description: 1: CK8M_D256_OUT is actually CK8M*/ 1077 #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) 1078 #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) 1079 #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 1080 #define RTC_CNTL_ENB_CK8M_DIV_S 7 1081 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ 1082 /*description: disable CK8M and CK8M_D256_OUT*/ 1083 #define RTC_CNTL_ENB_CK8M (BIT(6)) 1084 #define RTC_CNTL_ENB_CK8M_M (BIT(6)) 1085 #define RTC_CNTL_ENB_CK8M_V 0x1 1086 #define RTC_CNTL_ENB_CK8M_S 6 1087 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ 1088 /*description: CK8M_D256_OUT divider. 00: div128*/ 1089 #define RTC_CNTL_CK8M_DIV 0x00000003 1090 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) 1091 #define RTC_CNTL_CK8M_DIV_V 0x3 1092 #define RTC_CNTL_CK8M_DIV_S 4 1093 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ 1094 /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ 1095 #define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) 1096 #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) 1097 #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 1098 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 1099 /* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1100 /*description: */ 1101 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) 1102 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) 1103 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 1104 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 1105 /* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1106 /*description: */ 1107 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) 1108 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) 1109 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 1110 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 1111 1112 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) 1113 /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1114 /*description: */ 1115 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) 1116 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) 1117 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 1118 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 1119 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ 1120 /*description: */ 1121 #define RTC_CNTL_ANA_CLK_DIV 0x000000FF 1122 #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) 1123 #define RTC_CNTL_ANA_CLK_DIV_V 0xFF 1124 #define RTC_CNTL_ANA_CLK_DIV_S 23 1125 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1126 /*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ 1127 #define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) 1128 #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) 1129 #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 1130 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 1131 1132 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) 1133 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1134 /*description: */ 1135 #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) 1136 #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) 1137 #define RTC_CNTL_XPD_SDIO_REG_V 0x1 1138 #define RTC_CNTL_XPD_SDIO_REG_S 31 1139 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ 1140 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ 1141 #define RTC_CNTL_DREFH_SDIO 0x00000003 1142 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) 1143 #define RTC_CNTL_DREFH_SDIO_V 0x3 1144 #define RTC_CNTL_DREFH_SDIO_S 29 1145 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ 1146 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ 1147 #define RTC_CNTL_DREFM_SDIO 0x00000003 1148 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) 1149 #define RTC_CNTL_DREFM_SDIO_V 0x3 1150 #define RTC_CNTL_DREFM_SDIO_S 27 1151 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ 1152 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ 1153 #define RTC_CNTL_DREFL_SDIO 0x00000003 1154 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) 1155 #define RTC_CNTL_DREFL_SDIO_V 0x3 1156 #define RTC_CNTL_DREFL_SDIO_S 25 1157 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ 1158 /*description: read only register for REG1P8_READY*/ 1159 #define RTC_CNTL_REG1P8_READY (BIT(24)) 1160 #define RTC_CNTL_REG1P8_READY_M (BIT(24)) 1161 #define RTC_CNTL_REG1P8_READY_V 0x1 1162 #define RTC_CNTL_REG1P8_READY_S 24 1163 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1164 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 1165 #define RTC_CNTL_SDIO_TIEH (BIT(23)) 1166 #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) 1167 #define RTC_CNTL_SDIO_TIEH_V 0x1 1168 #define RTC_CNTL_SDIO_TIEH_S 23 1169 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1170 /*description: 1: use SW option to control SDIO_REG*/ 1171 #define RTC_CNTL_SDIO_FORCE (BIT(22)) 1172 #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) 1173 #define RTC_CNTL_SDIO_FORCE_V 0x1 1174 #define RTC_CNTL_SDIO_FORCE_S 22 1175 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1176 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ 1177 #define RTC_CNTL_SDIO_PD_EN (BIT(21)) 1178 #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) 1179 #define RTC_CNTL_SDIO_PD_EN_V 0x1 1180 #define RTC_CNTL_SDIO_PD_EN_S 21 1181 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1182 /*description: enable current limit*/ 1183 #define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) 1184 #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) 1185 #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 1186 #define RTC_CNTL_SDIO_ENCURLIM_S 20 1187 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1188 /*description: select current limit mode*/ 1189 #define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) 1190 #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) 1191 #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 1192 #define RTC_CNTL_SDIO_MODECURLIM_S 19 1193 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ 1194 /*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ 1195 #define RTC_CNTL_SDIO_DCURLIM 0x00000007 1196 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) 1197 #define RTC_CNTL_SDIO_DCURLIM_V 0x7 1198 #define RTC_CNTL_SDIO_DCURLIM_S 16 1199 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ 1200 /*description: 0 to set init[1:0]=0*/ 1201 #define RTC_CNTL_SDIO_EN_INITI (BIT(15)) 1202 #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) 1203 #define RTC_CNTL_SDIO_EN_INITI_V 0x1 1204 #define RTC_CNTL_SDIO_EN_INITI_S 15 1205 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ 1206 /*description: add resistor from ldo output to ground. 0: no res*/ 1207 #define RTC_CNTL_SDIO_INITI 0x00000003 1208 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) 1209 #define RTC_CNTL_SDIO_INITI_V 0x3 1210 #define RTC_CNTL_SDIO_INITI_S 13 1211 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ 1212 /*description: ability to prevent LDO from overshoot*/ 1213 #define RTC_CNTL_SDIO_DCAP 0x00000003 1214 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) 1215 #define RTC_CNTL_SDIO_DCAP_V 0x3 1216 #define RTC_CNTL_SDIO_DCAP_S 11 1217 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ 1218 /*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ 1219 #define RTC_CNTL_SDIO_DTHDRV 0x00000003 1220 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) 1221 #define RTC_CNTL_SDIO_DTHDRV_V 0x3 1222 #define RTC_CNTL_SDIO_DTHDRV_S 9 1223 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ 1224 /*description: timer count to apply reg_sdio_dcap after sdio power on*/ 1225 #define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF 1226 #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) 1227 #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF 1228 #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 1229 1230 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) 1231 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ 1232 /*description: DBG_ATTEN when rtc in monitor state*/ 1233 #define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F 1234 #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) 1235 #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF 1236 #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 1237 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ 1238 /*description: DBG_ATTEN when rtc in sleep state*/ 1239 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F 1240 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) 1241 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF 1242 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 1243 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1244 /*description: bias_sleep when rtc in monitor state*/ 1245 #define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) 1246 #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) 1247 #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 1248 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 1249 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1250 /*description: bias_sleep when rtc in sleep_state*/ 1251 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) 1252 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) 1253 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 1254 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 1255 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1256 /*description: xpd cur when rtc in monitor state*/ 1257 #define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) 1258 #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) 1259 #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 1260 #define RTC_CNTL_PD_CUR_MONITOR_S 15 1261 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1262 /*description: xpd cur when rtc in sleep_state*/ 1263 #define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) 1264 #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) 1265 #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 1266 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 1267 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1268 /*description: */ 1269 #define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) 1270 #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) 1271 #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 1272 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 1273 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1274 /*description: */ 1275 #define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) 1276 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) 1277 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 1278 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 1279 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1280 /*description: */ 1281 #define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) 1282 #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) 1283 #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 1284 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 1285 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1286 /*description: */ 1287 #define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) 1288 #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) 1289 #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 1290 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 1291 /* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1292 /*description: */ 1293 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) 1294 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) 1295 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 1296 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 1297 /* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 1298 /*description: */ 1299 #define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF 1300 #define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) 1301 #define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF 1302 #define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 1303 1304 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) 1305 /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1306 /*description: */ 1307 #define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) 1308 #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) 1309 #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 1310 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 1311 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1312 /*description: RTC_REG force power down (for RTC_REG power down means decrease 1313 the voltage to 0.8v or lower )*/ 1314 #define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) 1315 #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) 1316 #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 1317 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 1318 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1319 /*description: RTC_DBOOST force power up*/ 1320 #define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) 1321 #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) 1322 #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 1323 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 1324 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1325 /*description: RTC_DBOOST force power down*/ 1326 #define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) 1327 #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) 1328 #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 1329 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 1330 1331 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ 1332 /*description: SCK_DCAP*/ 1333 #define RTC_CNTL_SCK_DCAP 0x000000FF 1334 #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) 1335 #define RTC_CNTL_SCK_DCAP_V 0xFF 1336 #define RTC_CNTL_SCK_DCAP_S 14 1337 #define RTC_CNTL_SCK_DCAP_DEFAULT 255 1338 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1339 /*description: */ 1340 #define RTC_CNTL_DIG_CAL_EN (BIT(7)) 1341 #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) 1342 #define RTC_CNTL_DIG_CAL_EN_V 0x1 1343 #define RTC_CNTL_DIG_CAL_EN_S 7 1344 1345 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) 1346 /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ 1347 /*description: rtc pad force hold*/ 1348 #define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) 1349 #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) 1350 #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 1351 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 1352 1353 #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) 1354 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1355 /*description: */ 1356 #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) 1357 #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) 1358 #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 1359 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 1360 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1361 /*description: enable power down wifi in sleep*/ 1362 #define RTC_CNTL_WIFI_PD_EN (BIT(30)) 1363 #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) 1364 #define RTC_CNTL_WIFI_PD_EN_V 0x1 1365 #define RTC_CNTL_WIFI_PD_EN_S 30 1366 /* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1367 /*description: */ 1368 #define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) 1369 #define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) 1370 #define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 1371 #define RTC_CNTL_CPU_TOP_PD_EN_S 29 1372 /* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 1373 /*description: */ 1374 #define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) 1375 #define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) 1376 #define RTC_CNTL_DG_PERI_PD_EN_V 0x1 1377 #define RTC_CNTL_DG_PERI_PD_EN_S 28 1378 /* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1379 /*description: */ 1380 #define RTC_CNTL_BT_PD_EN (BIT(27)) 1381 #define RTC_CNTL_BT_PD_EN_M (BIT(27)) 1382 #define RTC_CNTL_BT_PD_EN_V 0x1 1383 #define RTC_CNTL_BT_PD_EN_S 27 1384 /* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1385 /*description: */ 1386 #define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) 1387 #define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) 1388 #define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 1389 #define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 1390 /* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 1391 /*description: */ 1392 #define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) 1393 #define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) 1394 #define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 1395 #define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 1396 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1397 /*description: digital core force power up*/ 1398 #define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) 1399 #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) 1400 #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 1401 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 1402 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 1403 /*description: digital core force power down*/ 1404 #define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) 1405 #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) 1406 #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 1407 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 1408 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ 1409 /*description: wifi force power up*/ 1410 #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) 1411 #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) 1412 #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 1413 #define RTC_CNTL_WIFI_FORCE_PU_S 18 1414 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1415 /*description: wifi force power down*/ 1416 #define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) 1417 #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) 1418 #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 1419 #define RTC_CNTL_WIFI_FORCE_PD_S 17 1420 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1421 /*description: */ 1422 #define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) 1423 #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) 1424 #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 1425 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 1426 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1427 /*description: */ 1428 #define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) 1429 #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) 1430 #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 1431 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 1432 /* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ 1433 /*description: */ 1434 #define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) 1435 #define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) 1436 #define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 1437 #define RTC_CNTL_DG_PERI_FORCE_PU_S 14 1438 /* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1439 /*description: */ 1440 #define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) 1441 #define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) 1442 #define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 1443 #define RTC_CNTL_DG_PERI_FORCE_PD_S 13 1444 /* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1445 /*description: */ 1446 #define RTC_CNTL_BT_FORCE_PU (BIT(12)) 1447 #define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) 1448 #define RTC_CNTL_BT_FORCE_PU_V 0x1 1449 #define RTC_CNTL_BT_FORCE_PU_S 12 1450 /* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1451 /*description: */ 1452 #define RTC_CNTL_BT_FORCE_PD (BIT(11)) 1453 #define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) 1454 #define RTC_CNTL_BT_FORCE_PD_V 0x1 1455 #define RTC_CNTL_BT_FORCE_PD_S 11 1456 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 1457 /*description: memories in digital core force no PD in sleep*/ 1458 #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) 1459 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) 1460 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 1461 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 1462 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1463 /*description: memories in digital core force PD in sleep*/ 1464 #define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) 1465 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) 1466 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 1467 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 1468 /* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1469 /*description: */ 1470 #define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) 1471 #define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) 1472 #define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 1473 #define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 1474 /* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 1475 /*description: */ 1476 #define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 1477 #define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) 1478 #define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 1479 #define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 1480 1481 #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) 1482 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1483 /*description: */ 1484 #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) 1485 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) 1486 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 1487 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 1488 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1489 /*description: digital core force ISO*/ 1490 #define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) 1491 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) 1492 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 1493 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 1494 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1495 /*description: wifi force no ISO*/ 1496 #define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) 1497 #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) 1498 #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 1499 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 1500 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1501 /*description: wifi force ISO*/ 1502 #define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) 1503 #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) 1504 #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 1505 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 1506 /* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 1507 /*description: cpu force no ISO*/ 1508 #define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) 1509 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) 1510 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 1511 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 1512 /* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1513 /*description: cpu force ISO*/ 1514 #define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) 1515 #define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) 1516 #define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 1517 #define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 1518 /* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ 1519 /*description: */ 1520 #define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) 1521 #define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) 1522 #define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 1523 #define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 1524 /* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 1525 /*description: */ 1526 #define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) 1527 #define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) 1528 #define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 1529 #define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 1530 /* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1531 /*description: */ 1532 #define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) 1533 #define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) 1534 #define RTC_CNTL_BT_FORCE_NOISO_V 0x1 1535 #define RTC_CNTL_BT_FORCE_NOISO_S 23 1536 /* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1537 /*description: */ 1538 #define RTC_CNTL_BT_FORCE_ISO (BIT(22)) 1539 #define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) 1540 #define RTC_CNTL_BT_FORCE_ISO_V 0x1 1541 #define RTC_CNTL_BT_FORCE_ISO_S 22 1542 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1543 /*description: digital pad force hold*/ 1544 #define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) 1545 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) 1546 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 1547 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 1548 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1549 /*description: digital pad force un-hold*/ 1550 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) 1551 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) 1552 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 1553 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 1554 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ 1555 /*description: digital pad force ISO*/ 1556 #define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) 1557 #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) 1558 #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 1559 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 1560 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1561 /*description: digital pad force no ISO*/ 1562 #define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) 1563 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) 1564 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 1565 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 1566 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1567 /*description: digital pad enable auto-hold*/ 1568 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) 1569 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) 1570 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 1571 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 1572 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ 1573 /*description: wtite only register to clear digital pad auto-hold*/ 1574 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) 1575 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) 1576 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 1577 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 1578 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ 1579 /*description: read only register to indicate digital pad auto-hold status*/ 1580 #define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) 1581 #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) 1582 #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 1583 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 1584 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1585 /*description: */ 1586 #define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) 1587 #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) 1588 #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 1589 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 1590 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ 1591 /*description: */ 1592 #define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) 1593 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) 1594 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 1595 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 1596 1597 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) 1598 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 1599 /*description: */ 1600 #define RTC_CNTL_WDT_EN (BIT(31)) 1601 #define RTC_CNTL_WDT_EN_M (BIT(31)) 1602 #define RTC_CNTL_WDT_EN_V 0x1 1603 #define RTC_CNTL_WDT_EN_S 31 1604 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 1605 /*description: 1: interrupt stage en*/ 1606 #define RTC_CNTL_WDT_STG0 0x00000007 1607 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) 1608 #define RTC_CNTL_WDT_STG0_V 0x7 1609 #define RTC_CNTL_WDT_STG0_S 28 1610 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 1611 /*description: 1: interrupt stage en*/ 1612 #define RTC_CNTL_WDT_STG1 0x00000007 1613 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) 1614 #define RTC_CNTL_WDT_STG1_V 0x7 1615 #define RTC_CNTL_WDT_STG1_S 25 1616 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ 1617 /*description: 1: interrupt stage en*/ 1618 #define RTC_CNTL_WDT_STG2 0x00000007 1619 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) 1620 #define RTC_CNTL_WDT_STG2_V 0x7 1621 #define RTC_CNTL_WDT_STG2_S 22 1622 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ 1623 /*description: 1: interrupt stage en*/ 1624 #define RTC_CNTL_WDT_STG3 0x00000007 1625 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) 1626 #define RTC_CNTL_WDT_STG3_V 0x7 1627 #define RTC_CNTL_WDT_STG3_S 19 1628 /* RTC_CNTL_WDT_STGX : */ 1629 /*description: stage action selection values */ 1630 #define RTC_WDT_STG_SEL_OFF 0 1631 #define RTC_WDT_STG_SEL_INT 1 1632 #define RTC_WDT_STG_SEL_RESET_CPU 2 1633 #define RTC_WDT_STG_SEL_RESET_SYSTEM 3 1634 #define RTC_WDT_STG_SEL_RESET_RTC 4 1635 1636 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ 1637 /*description: CPU reset counter length*/ 1638 #define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 1639 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) 1640 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 1641 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 1642 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ 1643 /*description: system reset counter length*/ 1644 #define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 1645 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) 1646 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 1647 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 1648 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 1649 /*description: enable WDT in flash boot*/ 1650 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) 1651 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) 1652 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 1653 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 1654 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1655 /*description: enable WDT reset PRO CPU*/ 1656 #define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) 1657 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) 1658 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 1659 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 1660 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1661 /*description: enable WDT reset APP CPU*/ 1662 #define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) 1663 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) 1664 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 1665 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 1666 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1667 /*description: pause WDT in sleep*/ 1668 #define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) 1669 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) 1670 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 1671 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 1672 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1673 /*description: wdt reset whole chip enable*/ 1674 #define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) 1675 #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) 1676 #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 1677 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 1678 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ 1679 /*description: chip reset siginal pulse width*/ 1680 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF 1681 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) 1682 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF 1683 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 1684 1685 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) 1686 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ 1687 /*description: */ 1688 #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF 1689 #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) 1690 #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF 1691 #define RTC_CNTL_WDT_STG0_HOLD_S 0 1692 1693 #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) 1694 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ 1695 /*description: */ 1696 #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF 1697 #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) 1698 #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF 1699 #define RTC_CNTL_WDT_STG1_HOLD_S 0 1700 1701 #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) 1702 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1703 /*description: */ 1704 #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF 1705 #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) 1706 #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF 1707 #define RTC_CNTL_WDT_STG2_HOLD_S 0 1708 1709 #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) 1710 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1711 /*description: */ 1712 #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF 1713 #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) 1714 #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF 1715 #define RTC_CNTL_WDT_STG3_HOLD_S 0 1716 1717 #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) 1718 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ 1719 /*description: */ 1720 #define RTC_CNTL_WDT_FEED (BIT(31)) 1721 #define RTC_CNTL_WDT_FEED_M (BIT(31)) 1722 #define RTC_CNTL_WDT_FEED_V 0x1 1723 #define RTC_CNTL_WDT_FEED_S 31 1724 1725 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) 1726 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 1727 /*description: */ 1728 #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF 1729 #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) 1730 #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF 1731 #define RTC_CNTL_WDT_WKEY_S 0 1732 1733 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) 1734 /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1735 /*description: automatically feed swd when int comes*/ 1736 #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) 1737 #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) 1738 #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 1739 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 1740 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1741 /*description: disabel SWD*/ 1742 #define RTC_CNTL_SWD_DISABLE (BIT(30)) 1743 #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) 1744 #define RTC_CNTL_SWD_DISABLE_V 0x1 1745 #define RTC_CNTL_SWD_DISABLE_S 30 1746 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ 1747 /*description: Sw feed swd*/ 1748 #define RTC_CNTL_SWD_FEED (BIT(29)) 1749 #define RTC_CNTL_SWD_FEED_M (BIT(29)) 1750 #define RTC_CNTL_SWD_FEED_V 0x1 1751 #define RTC_CNTL_SWD_FEED_S 29 1752 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 1753 /*description: reset swd reset flag*/ 1754 #define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) 1755 #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) 1756 #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 1757 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 1758 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ 1759 /*description: adjust signal width send to swd*/ 1760 #define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF 1761 #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) 1762 #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF 1763 #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 1764 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1765 /*description: */ 1766 #define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) 1767 #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) 1768 #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 1769 #define RTC_CNTL_SWD_BYPASS_RST_S 17 1770 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ 1771 /*description: swd interrupt for feeding*/ 1772 #define RTC_CNTL_SWD_FEED_INT (BIT(1)) 1773 #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) 1774 #define RTC_CNTL_SWD_FEED_INT_V 0x1 1775 #define RTC_CNTL_SWD_FEED_INT_S 1 1776 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ 1777 /*description: swd reset flag*/ 1778 #define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) 1779 #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) 1780 #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 1781 #define RTC_CNTL_SWD_RESET_FLAG_S 0 1782 1783 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) 1784 /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ 1785 /*description: */ 1786 #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF 1787 #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) 1788 #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF 1789 #define RTC_CNTL_SWD_WKEY_S 0 1790 1791 #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) 1792 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ 1793 /*description: */ 1794 #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F 1795 #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) 1796 #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F 1797 #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 1798 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ 1799 /*description: {reg_sw_stall_appcpu_c1[5:0]*/ 1800 #define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F 1801 #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) 1802 #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F 1803 #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 1804 1805 #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) 1806 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1807 /*description: */ 1808 #define RTC_CNTL_SCRATCH4 0xFFFFFFFF 1809 #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) 1810 #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF 1811 #define RTC_CNTL_SCRATCH4_S 0 1812 1813 #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) 1814 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1815 /*description: */ 1816 #define RTC_CNTL_SCRATCH5 0xFFFFFFFF 1817 #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) 1818 #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF 1819 #define RTC_CNTL_SCRATCH5_S 0 1820 1821 #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) 1822 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1823 /*description: */ 1824 #define RTC_CNTL_SCRATCH6 0xFFFFFFFF 1825 #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) 1826 #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF 1827 #define RTC_CNTL_SCRATCH6_S 0 1828 1829 #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) 1830 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1831 /*description: */ 1832 #define RTC_CNTL_SCRATCH7 0xFFFFFFFF 1833 #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) 1834 #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF 1835 #define RTC_CNTL_SCRATCH7_S 0 1836 1837 #define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) 1838 /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ 1839 /*description: rtc main state machine status*/ 1840 #define RTC_CNTL_MAIN_STATE 0x0000000F 1841 #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) 1842 #define RTC_CNTL_MAIN_STATE_V 0xF 1843 #define RTC_CNTL_MAIN_STATE_S 28 1844 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ 1845 /*description: rtc main state machine is in idle state*/ 1846 #define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) 1847 #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) 1848 #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 1849 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 1850 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ 1851 /*description: rtc main state machine is in sleep state*/ 1852 #define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) 1853 #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) 1854 #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 1855 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 1856 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ 1857 /*description: rtc main state machine is in wait xtal state*/ 1858 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) 1859 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) 1860 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 1861 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 1862 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ 1863 /*description: rtc main state machine is in wait pll state*/ 1864 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) 1865 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) 1866 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 1867 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 1868 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ 1869 /*description: rtc main state machine is in wait 8m state*/ 1870 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) 1871 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) 1872 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 1873 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 1874 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ 1875 /*description: rtc main state machine is in the states of low power*/ 1876 #define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) 1877 #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) 1878 #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 1879 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 1880 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ 1881 /*description: rtc main state machine is in the states of wakeup process*/ 1882 #define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) 1883 #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) 1884 #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 1885 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 1886 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 1887 /*description: rtc main state machine has been waited for some cycles*/ 1888 #define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) 1889 #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) 1890 #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 1891 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 1892 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ 1893 /*description: rtc is ready to receive wake up trigger from wake up source*/ 1894 #define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) 1895 #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) 1896 #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 1897 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 1898 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ 1899 /*description: rtc main state machine is in states that pll should be running*/ 1900 #define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) 1901 #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) 1902 #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 1903 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 1904 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ 1905 /*description: no use any more*/ 1906 #define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) 1907 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) 1908 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 1909 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 1910 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ 1911 /*description: ulp/cocpu is done*/ 1912 #define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) 1913 #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) 1914 #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 1915 #define RTC_CNTL_COCPU_STATE_DONE_S 16 1916 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ 1917 /*description: ulp/cocpu is in sleep state*/ 1918 #define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) 1919 #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) 1920 #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 1921 #define RTC_CNTL_COCPU_STATE_SLP_S 15 1922 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ 1923 /*description: ulp/cocpu is about to working. Switch rtc main state*/ 1924 #define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) 1925 #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) 1926 #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 1927 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 1928 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ 1929 /*description: ulp/cocpu should start to work*/ 1930 #define RTC_CNTL_COCPU_STATE_START (BIT(13)) 1931 #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) 1932 #define RTC_CNTL_COCPU_STATE_START_V 0x1 1933 #define RTC_CNTL_COCPU_STATE_START_S 13 1934 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ 1935 /*description: touch is done*/ 1936 #define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) 1937 #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) 1938 #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 1939 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 1940 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ 1941 /*description: touch is in sleep state*/ 1942 #define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) 1943 #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) 1944 #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 1945 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 1946 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ 1947 /*description: touch is about to working. Switch rtc main state*/ 1948 #define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) 1949 #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) 1950 #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 1951 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 1952 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ 1953 /*description: touch should start to work*/ 1954 #define RTC_CNTL_TOUCH_STATE_START (BIT(9)) 1955 #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) 1956 #define RTC_CNTL_TOUCH_STATE_START_V 0x1 1957 #define RTC_CNTL_TOUCH_STATE_START_S 9 1958 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ 1959 /*description: digital wrap power down*/ 1960 #define RTC_CNTL_XPD_DIG (BIT(8)) 1961 #define RTC_CNTL_XPD_DIG_M (BIT(8)) 1962 #define RTC_CNTL_XPD_DIG_V 0x1 1963 #define RTC_CNTL_XPD_DIG_S 8 1964 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ 1965 /*description: digital wrap iso*/ 1966 #define RTC_CNTL_DIG_ISO (BIT(7)) 1967 #define RTC_CNTL_DIG_ISO_M (BIT(7)) 1968 #define RTC_CNTL_DIG_ISO_V 0x1 1969 #define RTC_CNTL_DIG_ISO_S 7 1970 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ 1971 /*description: wifi wrap power down*/ 1972 #define RTC_CNTL_XPD_WIFI (BIT(6)) 1973 #define RTC_CNTL_XPD_WIFI_M (BIT(6)) 1974 #define RTC_CNTL_XPD_WIFI_V 0x1 1975 #define RTC_CNTL_XPD_WIFI_S 6 1976 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ 1977 /*description: wifi iso*/ 1978 #define RTC_CNTL_WIFI_ISO (BIT(5)) 1979 #define RTC_CNTL_WIFI_ISO_M (BIT(5)) 1980 #define RTC_CNTL_WIFI_ISO_V 0x1 1981 #define RTC_CNTL_WIFI_ISO_S 5 1982 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ 1983 /*description: rtc peripheral power down*/ 1984 #define RTC_CNTL_XPD_RTC_PERI (BIT(4)) 1985 #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) 1986 #define RTC_CNTL_XPD_RTC_PERI_V 0x1 1987 #define RTC_CNTL_XPD_RTC_PERI_S 4 1988 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ 1989 /*description: rtc peripheral iso*/ 1990 #define RTC_CNTL_PERI_ISO (BIT(3)) 1991 #define RTC_CNTL_PERI_ISO_M (BIT(3)) 1992 #define RTC_CNTL_PERI_ISO_V 0x1 1993 #define RTC_CNTL_PERI_ISO_S 3 1994 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ 1995 /*description: External DCDC power down*/ 1996 #define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) 1997 #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) 1998 #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 1999 #define RTC_CNTL_XPD_DIG_DCDC_S 2 2000 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ 2001 /*description: rom0 power down*/ 2002 #define RTC_CNTL_XPD_ROM0 (BIT(0)) 2003 #define RTC_CNTL_XPD_ROM0_M (BIT(0)) 2004 #define RTC_CNTL_XPD_ROM0_V 0x1 2005 #define RTC_CNTL_XPD_ROM0_S 0 2006 2007 #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) 2008 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ 2009 /*description: */ 2010 #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF 2011 #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) 2012 #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF 2013 #define RTC_CNTL_LOW_POWER_DIAG1_S 0 2014 2015 #define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) 2016 /* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2017 /*description: */ 2018 #define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) 2019 #define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) 2020 #define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 2021 #define RTC_CNTL_GPIO_PIN5_HOLD_S 5 2022 /* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2023 /*description: */ 2024 #define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) 2025 #define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) 2026 #define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 2027 #define RTC_CNTL_GPIO_PIN4_HOLD_S 4 2028 /* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2029 /*description: */ 2030 #define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) 2031 #define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) 2032 #define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 2033 #define RTC_CNTL_GPIO_PIN3_HOLD_S 3 2034 /* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2035 /*description: */ 2036 #define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) 2037 #define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) 2038 #define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 2039 #define RTC_CNTL_GPIO_PIN2_HOLD_S 2 2040 /* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2041 /*description: */ 2042 #define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) 2043 #define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) 2044 #define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 2045 #define RTC_CNTL_GPIO_PIN1_HOLD_S 1 2046 /* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2047 /*description: */ 2048 #define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) 2049 #define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) 2050 #define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 2051 #define RTC_CNTL_GPIO_PIN0_HOLD_S 0 2052 2053 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) 2054 /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 2055 /*description: */ 2056 #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF 2057 #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) 2058 #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF 2059 #define RTC_CNTL_DIG_PAD_HOLD_S 0 2060 2061 #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) 2062 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ 2063 /*description: */ 2064 #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) 2065 #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) 2066 #define RTC_CNTL_BROWN_OUT_DET_V 0x1 2067 #define RTC_CNTL_BROWN_OUT_DET_S 31 2068 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ 2069 /*description: enable brown out*/ 2070 #define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) 2071 #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) 2072 #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 2073 #define RTC_CNTL_BROWN_OUT_ENA_S 30 2074 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 2075 /*description: clear brown out counter*/ 2076 #define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) 2077 #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) 2078 #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 2079 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 2080 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2081 /*description: */ 2082 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) 2083 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) 2084 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 2085 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 2086 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2087 /*description: 1: 4-pos reset*/ 2088 #define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) 2089 #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) 2090 #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 2091 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 2092 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2093 /*description: enable brown out reset*/ 2094 #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) 2095 #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) 2096 #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 2097 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 2098 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ 2099 /*description: brown out reset wait cycles*/ 2100 #define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF 2101 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) 2102 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF 2103 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 2104 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2105 /*description: enable power down RF when brown out happens*/ 2106 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) 2107 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) 2108 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 2109 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 2110 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2111 /*description: enable close flash when brown out happens*/ 2112 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) 2113 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) 2114 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 2115 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 2116 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ 2117 /*description: brown out interrupt wait cycles*/ 2118 #define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF 2119 #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) 2120 #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF 2121 #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 2122 2123 #define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) 2124 /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 2125 /*description: RTC timer low 32 bits*/ 2126 #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF 2127 #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) 2128 #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF 2129 #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 2130 2131 #define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) 2132 /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 2133 /*description: RTC timer high 16 bits*/ 2134 #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF 2135 #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) 2136 #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF 2137 #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 2138 2139 #define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) 2140 /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 2141 /*description: xtal 32k watch dog backup clock factor*/ 2142 #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF 2143 #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) 2144 #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF 2145 #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 2146 2147 #define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) 2148 /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ 2149 /*description: if restarted xtal32k period is smaller than this*/ 2150 #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F 2151 #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) 2152 #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF 2153 #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 2154 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ 2155 /*description: If no clock detected for this amount of time*/ 2156 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF 2157 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) 2158 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF 2159 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 2160 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ 2161 /*description: cycles to wait to repower on xtal 32k*/ 2162 #define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF 2163 #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) 2164 #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF 2165 #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 2166 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ 2167 /*description: cycles to wait to return noral xtal 32k*/ 2168 #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F 2169 #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) 2170 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF 2171 #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 2172 2173 #define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) 2174 /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ 2175 /*description: */ 2176 #define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) 2177 #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) 2178 #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 2179 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 2180 2181 #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) 2182 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ 2183 /*description: sleep reject cause*/ 2184 #define RTC_CNTL_REJECT_CAUSE 0x0003FFFF 2185 #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) 2186 #define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF 2187 #define RTC_CNTL_REJECT_CAUSE_S 0 2188 2189 #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) 2190 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 2191 /*description: */ 2192 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) 2193 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) 2194 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 2195 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 2196 2197 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) 2198 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 2199 /*description: sleep wakeup cause*/ 2200 #define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF 2201 #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) 2202 #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF 2203 #define RTC_CNTL_WAKEUP_CAUSE_S 0 2204 2205 #define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) 2206 /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ 2207 /*description: sleep cycles for ULP-coprocessor timer*/ 2208 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF 2209 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) 2210 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF 2211 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 2212 2213 #define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) 2214 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ 2215 /*description: */ 2216 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) 2217 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) 2218 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 2219 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 2220 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ 2221 /*description: enbale gitch det interrupt*/ 2222 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) 2223 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) 2224 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 2225 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 2226 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ 2227 /*description: enable xtal32k_dead interrupt*/ 2228 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) 2229 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) 2230 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 2231 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 2232 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ 2233 /*description: enable super watch dog interrupt*/ 2234 #define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) 2235 #define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) 2236 #define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 2237 #define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 2238 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ 2239 /*description: enable RTC main timer interrupt*/ 2240 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) 2241 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) 2242 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 2243 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 2244 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ 2245 /*description: enable brown out interrupt*/ 2246 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) 2247 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) 2248 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 2249 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 2250 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ 2251 /*description: enable RTC WDT interrupt*/ 2252 #define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) 2253 #define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) 2254 #define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 2255 #define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 2256 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ 2257 /*description: enable sleep reject interrupt*/ 2258 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) 2259 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) 2260 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 2261 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 2262 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ 2263 /*description: enable sleep wakeup interrupt*/ 2264 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) 2265 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) 2266 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 2267 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 2268 2269 #define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) 2270 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ 2271 /*description: */ 2272 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) 2273 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) 2274 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 2275 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 2276 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ 2277 /*description: enbale gitch det interrupt*/ 2278 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) 2279 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) 2280 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 2281 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 2282 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ 2283 /*description: enable xtal32k_dead interrupt*/ 2284 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) 2285 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) 2286 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 2287 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 2288 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ 2289 /*description: enable super watch dog interrupt*/ 2290 #define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) 2291 #define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) 2292 #define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 2293 #define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 2294 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ 2295 /*description: enable RTC main timer interrupt*/ 2296 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) 2297 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) 2298 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 2299 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 2300 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ 2301 /*description: enable brown out interrupt*/ 2302 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) 2303 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) 2304 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 2305 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 2306 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ 2307 /*description: enable RTC WDT interrupt*/ 2308 #define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) 2309 #define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) 2310 #define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 2311 #define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 2312 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ 2313 /*description: enable sleep reject interrupt*/ 2314 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) 2315 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) 2316 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 2317 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 2318 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ 2319 /*description: enable sleep wakeup interrupt*/ 2320 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) 2321 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) 2322 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 2323 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 2324 2325 #define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) 2326 /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ 2327 /*description: wait cycles for rention operation*/ 2328 #define RTC_CNTL_RETENTION_WAIT 0x0000001F 2329 #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) 2330 #define RTC_CNTL_RETENTION_WAIT_V 0x1F 2331 #define RTC_CNTL_RETENTION_WAIT_S 27 2332 /* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ 2333 /*description: */ 2334 #define RTC_CNTL_RETENTION_EN (BIT(26)) 2335 #define RTC_CNTL_RETENTION_EN_M (BIT(26)) 2336 #define RTC_CNTL_RETENTION_EN_V 0x1 2337 #define RTC_CNTL_RETENTION_EN_S 26 2338 /* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ 2339 /*description: */ 2340 #define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F 2341 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) 2342 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF 2343 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 2344 /* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ 2345 /*description: */ 2346 #define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 2347 #define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) 2348 #define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 2349 #define RTC_CNTL_RETENTION_DONE_WAIT_S 19 2350 /* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2351 /*description: */ 2352 #define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) 2353 #define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) 2354 #define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 2355 #define RTC_CNTL_RETENTION_CLK_SEL_S 18 2356 2357 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) 2358 /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 2359 /*description: select use analog fib signal*/ 2360 #define RTC_CNTL_FIB_SEL 0x00000007 2361 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) 2362 #define RTC_CNTL_FIB_SEL_V 0x7 2363 #define RTC_CNTL_FIB_SEL_S 0 2364 2365 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) 2366 #define RTC_CNTL_FIB_BOR_RST BIT(1) 2367 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) 2368 2369 #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) 2370 /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2371 /*description: */ 2372 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) 2373 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) 2374 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 2375 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 2376 /* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2377 /*description: */ 2378 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) 2379 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) 2380 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 2381 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 2382 /* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2383 /*description: */ 2384 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) 2385 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) 2386 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 2387 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 2388 /* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2389 /*description: */ 2390 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) 2391 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) 2392 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 2393 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 2394 /* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2395 /*description: */ 2396 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) 2397 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) 2398 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 2399 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 2400 /* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2401 /*description: */ 2402 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) 2403 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) 2404 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 2405 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 2406 /* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ 2407 /*description: */ 2408 #define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 2409 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) 2410 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 2411 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 2412 /* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 2413 /*description: */ 2414 #define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 2415 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) 2416 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 2417 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 2418 /* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ 2419 /*description: */ 2420 #define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 2421 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) 2422 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 2423 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 2424 /* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ 2425 /*description: */ 2426 #define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 2427 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) 2428 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 2429 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 2430 /* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ 2431 /*description: */ 2432 #define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 2433 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) 2434 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 2435 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 2436 /* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ 2437 /*description: */ 2438 #define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 2439 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) 2440 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 2441 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 2442 /* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2443 /*description: */ 2444 #define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) 2445 #define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) 2446 #define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 2447 #define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 2448 /* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2449 /*description: */ 2450 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) 2451 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) 2452 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 2453 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 2454 /* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ 2455 /*description: */ 2456 #define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F 2457 #define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) 2458 #define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F 2459 #define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 2460 2461 #define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) 2462 /* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ 2463 /*description: */ 2464 #define RTC_CNTL_DEBUG_SEL4 0x0000001F 2465 #define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) 2466 #define RTC_CNTL_DEBUG_SEL4_V 0x1F 2467 #define RTC_CNTL_DEBUG_SEL4_S 27 2468 /* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ 2469 /*description: */ 2470 #define RTC_CNTL_DEBUG_SEL3 0x0000001F 2471 #define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) 2472 #define RTC_CNTL_DEBUG_SEL3_V 0x1F 2473 #define RTC_CNTL_DEBUG_SEL3_S 22 2474 /* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ 2475 /*description: */ 2476 #define RTC_CNTL_DEBUG_SEL2 0x0000001F 2477 #define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) 2478 #define RTC_CNTL_DEBUG_SEL2_V 0x1F 2479 #define RTC_CNTL_DEBUG_SEL2_S 17 2480 /* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ 2481 /*description: */ 2482 #define RTC_CNTL_DEBUG_SEL1 0x0000001F 2483 #define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) 2484 #define RTC_CNTL_DEBUG_SEL1_V 0x1F 2485 #define RTC_CNTL_DEBUG_SEL1_S 12 2486 /* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ 2487 /*description: */ 2488 #define RTC_CNTL_DEBUG_SEL0 0x0000001F 2489 #define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) 2490 #define RTC_CNTL_DEBUG_SEL0_V 0x1F 2491 #define RTC_CNTL_DEBUG_SEL0_S 7 2492 /* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ 2493 /*description: */ 2494 #define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F 2495 #define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) 2496 #define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F 2497 #define RTC_CNTL_DEBUG_BIT_SEL_S 2 2498 /* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2499 /*description: */ 2500 #define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) 2501 #define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) 2502 #define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 2503 #define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 2504 2505 #define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) 2506 /* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ 2507 /*description: */ 2508 #define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F 2509 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) 2510 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF 2511 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 2512 /* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ 2513 /*description: */ 2514 #define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F 2515 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) 2516 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF 2517 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 2518 /* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ 2519 /*description: */ 2520 #define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F 2521 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) 2522 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF 2523 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 2524 /* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ 2525 /*description: */ 2526 #define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F 2527 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) 2528 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF 2529 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 2530 /* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ 2531 /*description: */ 2532 #define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F 2533 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) 2534 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF 2535 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 2536 /* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ 2537 /*description: */ 2538 #define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F 2539 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) 2540 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF 2541 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 2542 /* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2543 /*description: */ 2544 #define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) 2545 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) 2546 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 2547 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 2548 /* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2549 /*description: */ 2550 #define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) 2551 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) 2552 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 2553 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 2554 /* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2555 /*description: */ 2556 #define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) 2557 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) 2558 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 2559 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 2560 /* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2561 /*description: */ 2562 #define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) 2563 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) 2564 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 2565 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 2566 /* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2567 /*description: */ 2568 #define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) 2569 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) 2570 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 2571 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 2572 /* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2573 /*description: */ 2574 #define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) 2575 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) 2576 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 2577 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 2578 2579 #define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) 2580 /* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ 2581 /*description: */ 2582 #define RTC_CNTL_FORCE_XPD_SAR 0x00000003 2583 #define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) 2584 #define RTC_CNTL_FORCE_XPD_SAR_V 0x3 2585 #define RTC_CNTL_FORCE_XPD_SAR_S 30 2586 /* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ 2587 /*description: */ 2588 #define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 2589 #define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) 2590 #define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 2591 #define RTC_CNTL_SAR2_PWDET_CCT_S 27 2592 2593 #define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) 2594 /* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ 2595 /*description: */ 2596 #define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F 2597 #define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) 2598 #define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F 2599 #define RTC_CNTL_SAR_DEBUG_SEL_S 27 2600 2601 #define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) 2602 /* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2603 /*description: */ 2604 #define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) 2605 #define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) 2606 #define RTC_CNTL_POWER_GLITCH_EN_V 0x1 2607 #define RTC_CNTL_POWER_GLITCH_EN_S 31 2608 /* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2609 /*description: */ 2610 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) 2611 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) 2612 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 2613 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 2614 /* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2615 /*description: */ 2616 #define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) 2617 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) 2618 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 2619 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 2620 /* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2621 /*description: */ 2622 #define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) 2623 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) 2624 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 2625 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 2626 /* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ 2627 /*description: */ 2628 #define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 2629 #define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) 2630 #define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 2631 #define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 2632 2633 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) 2634 /* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ 2635 /*description: */ 2636 #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF 2637 #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) 2638 #define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF 2639 #define RTC_CNTL_CNTL_DATE_S 0 2640 2641 #ifdef __cplusplus 2642 } 2643 #endif 2644 2645 2646 2647 #endif /*_SOC_RTC_CNTL_REG_H_ */ 2648
