1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _SOC_PERIPH_DEFS_H_ 16 #define _SOC_PERIPH_DEFS_H_ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 typedef enum { 23 PERIPH_LEDC_MODULE = 0, 24 PERIPH_UART0_MODULE, 25 PERIPH_UART1_MODULE, 26 PERIPH_USB_MODULE, 27 PERIPH_I2C0_MODULE, 28 PERIPH_I2C1_MODULE, 29 PERIPH_I2S0_MODULE, 30 PERIPH_I2S1_MODULE, 31 PERIPH_TIMG0_MODULE, 32 PERIPH_TIMG1_MODULE, 33 PERIPH_PWM0_MODULE, 34 PERIPH_PWM1_MODULE, 35 PERIPH_PWM2_MODULE, 36 PERIPH_PWM3_MODULE, 37 PERIPH_UHCI0_MODULE, 38 PERIPH_UHCI1_MODULE, 39 PERIPH_RMT_MODULE, 40 PERIPH_PCNT_MODULE, 41 PERIPH_SPI_MODULE, //SPI1 42 PERIPH_FSPI_MODULE, //SPI2 43 PERIPH_HSPI_MODULE, //SPI3 44 PERIPH_SPI2_DMA_MODULE, 45 PERIPH_SPI3_DMA_MODULE, 46 PERIPH_TWAI_MODULE, 47 PERIPH_RNG_MODULE, 48 PERIPH_WIFI_MODULE, 49 PERIPH_WIFI_BT_COMMON_MODULE, 50 PERIPH_SYSTIMER_MODULE, 51 PERIPH_AES_MODULE, 52 PERIPH_SHA_MODULE, 53 PERIPH_RSA_MODULE, 54 PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA 55 PERIPH_AES_DMA_MODULE, 56 PERIPH_SHA_DMA_MODULE, 57 PERIPH_DEDIC_GPIO_MODULE, 58 PERIPH_MODULE_MAX 59 } periph_module_t; 60 61 typedef enum { 62 ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ 63 ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ 64 ETS_WIFI_PWR_INTR_SOURCE, /**< */ 65 ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ 66 ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ 67 ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ 68 ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ 69 ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ 70 ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ 71 ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ 72 ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ 73 ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ 74 ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ 75 ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ 76 ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ 77 ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ 78 79 ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ 80 ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ 81 ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ 82 ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ 83 ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ 84 ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ 85 ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ 86 ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ 87 ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ 88 ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ 89 ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ 90 ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ 91 ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ 92 ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ 93 ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ 94 ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ 95 96 ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ 97 ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ 98 ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ 99 ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ 100 ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ 101 ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ 102 ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ 103 ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ 104 ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ 105 ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ 106 ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ 107 ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/ 108 ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/ 109 ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ 110 ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ 111 ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ 112 113 ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ 114 ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ 115 ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ 116 ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ 117 ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ 118 ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ 119 ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ 120 ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ 121 ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ 122 ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ 123 ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ 124 ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ 125 ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ 126 ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ 127 ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ 128 ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ 129 130 ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ 131 ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 132 ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ 133 ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ 134 ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ 135 ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 136 ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ 137 ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ 138 ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ 139 ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ 140 ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ 141 ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/ 142 ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/ 143 ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/ 144 ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/ 145 ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/ 146 147 ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/ 148 ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/ 149 ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/ 150 ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ 151 ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ 152 ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/ 153 ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/ 154 ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ 155 ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ 156 ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ 157 ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ 158 ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/ 159 ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/ 160 ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ 161 ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ 162 ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ 163 164 } periph_interrput_t; 165 166 #ifdef __cplusplus 167 } 168 #endif 169 170 #endif /* _SOC_PERIPH_DEFS_H_ */ 171
