1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_EFUSE_REG_H_ 15 #define _SOC_EFUSE_REG_H_ 16 17 18 #include "soc.h" 19 #define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) 20 /* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ 21 /*description: read for flash_crypt_cnt*/ 22 #define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F 23 #define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) 24 #define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F 25 #define EFUSE_RD_FLASH_CRYPT_CNT_S 20 26 /* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ 27 /*description: read for efuse_rd_disable*/ 28 #define EFUSE_RD_EFUSE_RD_DIS 0x0000000F 29 #define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) 30 #define EFUSE_RD_EFUSE_RD_DIS_V 0xF 31 #define EFUSE_RD_EFUSE_RD_DIS_S 16 32 33 /* Read disable bits for efuse blocks 1-3 */ 34 #define EFUSE_RD_DIS_BLK1 (1<<16) 35 #define EFUSE_RD_DIS_BLK2 (1<<17) 36 #define EFUSE_RD_DIS_BLK3 (1<<18) 37 /* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS 38 in efuse block 0 39 */ 40 #define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) 41 42 /* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 43 /*description: read for efuse_wr_disable*/ 44 #define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF 45 #define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) 46 #define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF 47 #define EFUSE_RD_EFUSE_WR_DIS_S 0 48 49 /* Write disable bits */ 50 #define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ 51 #define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ 52 #define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) 53 #define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ 54 #define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ 55 #define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ 56 #define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ 57 #define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ 58 #define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ 59 #define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ 60 #define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ 61 #define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ 62 #define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ 63 #define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ 64 65 #define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) 66 /* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 67 /*description: read for low 32bit WIFI_MAC_Address*/ 68 #define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF 69 #define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) 70 #define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 71 #define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 72 73 #define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) 74 /* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 75 /*description: read for high 24bit WIFI_MAC_Address*/ 76 #define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF 77 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) 78 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 79 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 80 81 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) 82 /* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 83 /*description: bit is set to 1 for rev1 silicon*/ 84 #define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) 85 #define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) 86 #define EFUSE_RD_CHIP_VER_REV1_V 0x1 87 #define EFUSE_RD_CHIP_VER_REV1_S 15 88 /* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 89 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 90 #define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) 91 #define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) 92 #define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 93 #define EFUSE_RD_BLK3_PART_RESERVE_S 14 94 /* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 95 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 96 #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) 97 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) 98 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 99 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 100 /* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 101 /*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 102 #define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) 103 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) 104 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 105 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 106 /* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 107 /*description: least significant bits of chip package */ 108 #define EFUSE_RD_CHIP_VER_PKG 0x00000007 109 #define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) 110 #define EFUSE_RD_CHIP_VER_PKG_V 0x7 111 #define EFUSE_RD_CHIP_VER_PKG_S 9 112 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 113 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 114 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 115 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 116 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 117 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 118 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ 119 /*description: read for SPI_pad_config_hd*/ 120 #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F 121 #define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) 122 #define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F 123 #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 124 /* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ 125 /*description: */ 126 #define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) 127 #define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) 128 #define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 129 #define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 130 /* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 131 /*description: most significant bit of chip package */ 132 #define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) 133 #define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) 134 #define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 135 #define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 136 /* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ 137 /*description: */ 138 #define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) 139 #define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) 140 #define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 141 #define EFUSE_RD_CHIP_VER_DIS_BT_S 1 142 /* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ 143 /*description: */ 144 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) 145 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 146 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 147 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 148 149 #define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) 150 /* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ 151 /*description: read for sdio_force*/ 152 #define EFUSE_RD_SDIO_FORCE (BIT(16)) 153 #define EFUSE_RD_SDIO_FORCE_M (BIT(16)) 154 #define EFUSE_RD_SDIO_FORCE_V 0x1 155 #define EFUSE_RD_SDIO_FORCE_S 16 156 /* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ 157 /*description: read for SDIO_TIEH*/ 158 #define EFUSE_RD_SDIO_TIEH (BIT(15)) 159 #define EFUSE_RD_SDIO_TIEH_M (BIT(15)) 160 #define EFUSE_RD_SDIO_TIEH_V 0x1 161 #define EFUSE_RD_SDIO_TIEH_S 15 162 /* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ 163 /*description: read for XPD_SDIO_REG*/ 164 #define EFUSE_RD_XPD_SDIO_REG (BIT(14)) 165 #define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) 166 #define EFUSE_RD_XPD_SDIO_REG_V 0x1 167 #define EFUSE_RD_XPD_SDIO_REG_S 14 168 /* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 169 /*description: True ADC reference voltage */ 170 #define EFUSE_RD_ADC_VREF 0x0000001F 171 #define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) 172 #define EFUSE_RD_ADC_VREF_V 0x1F 173 #define EFUSE_RD_ADC_VREF_S 8 174 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 175 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 176 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 177 /* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ 178 /*description: */ 179 #define EFUSE_RD_SDIO_DREFL 0x00000003 180 #define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) 181 #define EFUSE_RD_SDIO_DREFL_V 0x3 182 #define EFUSE_RD_SDIO_DREFL_S 12 183 /* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ 184 /*description: */ 185 #define EFUSE_RD_SDIO_DREFM 0x00000003 186 #define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) 187 #define EFUSE_RD_SDIO_DREFM_V 0x3 188 #define EFUSE_RD_SDIO_DREFM_S 10 189 /* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ 190 /*description: */ 191 #define EFUSE_RD_SDIO_DREFH 0x00000003 192 #define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) 193 #define EFUSE_RD_SDIO_DREFH_V 0x3 194 #define EFUSE_RD_SDIO_DREFH_S 8 195 /* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 196 /*description: */ 197 #define EFUSE_RD_CK8M_FREQ 0x000000FF 198 #define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) 199 #define EFUSE_RD_CK8M_FREQ_V 0xFF 200 #define EFUSE_RD_CK8M_FREQ_S 0 201 202 #define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) 203 /* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ 204 /*description: read for flash_crypt_config*/ 205 #define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F 206 #define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) 207 #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF 208 #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 209 /* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ 210 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) 211 BIT[27] is the sign bit, 0: + , 1: - 212 BIT[26:24] is the difference value, unit: 0.017V 213 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 214 #define EFUSE_RD_DIG_VOL_L6 0x0F 215 #define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 216 #define EFUSE_RD_DIG_VOL_L6_V 0x0F 217 #define EFUSE_RD_DIG_VOL_L6_S 24 218 /* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ 219 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 220 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ 221 #define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 222 #define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 223 #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 224 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 225 /* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ 226 /* Deprecated */ 227 #define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ 228 #define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ 229 #define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ 230 #define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ 231 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ 232 /*description: read for SPI_pad_config_cs0*/ 233 #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F 234 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) 235 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F 236 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 237 /* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ 238 /*description: read for SPI_pad_config_d*/ 239 #define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F 240 #define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) 241 #define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F 242 #define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 243 /* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ 244 /*description: read for SPI_pad_config_q*/ 245 #define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F 246 #define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) 247 #define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F 248 #define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 249 /* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ 250 /*description: read for SPI_pad_config_clk*/ 251 #define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F 252 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) 253 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F 254 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 255 256 #define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) 257 /* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ 258 /*description: read for key_status*/ 259 #define EFUSE_RD_KEY_STATUS (BIT(10)) 260 #define EFUSE_RD_KEY_STATUS_M (BIT(10)) 261 #define EFUSE_RD_KEY_STATUS_V 0x1 262 #define EFUSE_RD_KEY_STATUS_S 10 263 /* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ 264 /*description: read for download_dis_cache*/ 265 #define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) 266 #define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) 267 #define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 268 #define EFUSE_RD_DISABLE_DL_CACHE_S 9 269 /* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ 270 /*description: read for download_dis_decrypt*/ 271 #define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) 272 #define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) 273 #define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 274 #define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 275 /* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ 276 /*description: read for download_dis_encrypt*/ 277 #define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) 278 #define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) 279 #define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 280 #define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 281 /* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ 282 /*description: read for JTAG_disable*/ 283 #define EFUSE_RD_DISABLE_JTAG (BIT(6)) 284 #define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) 285 #define EFUSE_RD_DISABLE_JTAG_V 0x1 286 #define EFUSE_RD_DISABLE_JTAG_S 6 287 /* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ 288 /*description: read for abstract_done_1*/ 289 #define EFUSE_RD_ABS_DONE_1 (BIT(5)) 290 #define EFUSE_RD_ABS_DONE_1_M (BIT(5)) 291 #define EFUSE_RD_ABS_DONE_1_V 0x1 292 #define EFUSE_RD_ABS_DONE_1_S 5 293 /* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ 294 /*description: read for abstract_done_0*/ 295 #define EFUSE_RD_ABS_DONE_0 (BIT(4)) 296 #define EFUSE_RD_ABS_DONE_0_M (BIT(4)) 297 #define EFUSE_RD_ABS_DONE_0_V 0x1 298 #define EFUSE_RD_ABS_DONE_0_S 4 299 /* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ 300 /*description: */ 301 #define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) 302 #define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) 303 #define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 304 #define EFUSE_RD_DISABLE_SDIO_HOST_S 3 305 /* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ 306 /*description: read for console_debug_disable*/ 307 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) 308 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 309 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 310 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 311 /* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ 312 /*description: read for coding_scheme*/ 313 #define EFUSE_RD_CODING_SCHEME 0x00000003 314 #define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) 315 #define EFUSE_RD_CODING_SCHEME_V 0x3 316 #define EFUSE_RD_CODING_SCHEME_S 0 317 318 #define EFUSE_CODING_SCHEME_VAL_NONE 0x0 319 #define EFUSE_CODING_SCHEME_VAL_34 0x1 320 #define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 321 322 #define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) 323 /* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ 324 /*description: program for flash_crypt_cnt*/ 325 #define EFUSE_FLASH_CRYPT_CNT 0x0000007F 326 #define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) 327 #define EFUSE_FLASH_CRYPT_CNT_V 0x7F 328 #define EFUSE_FLASH_CRYPT_CNT_S 20 329 /* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ 330 /*description: program for efuse_rd_disable*/ 331 #define EFUSE_RD_DIS 0x0000000F 332 #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) 333 #define EFUSE_RD_DIS_V 0xF 334 #define EFUSE_RD_DIS_S 16 335 /* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 336 /*description: program for efuse_wr_disable*/ 337 #define EFUSE_WR_DIS 0x0000FFFF 338 #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) 339 #define EFUSE_WR_DIS_V 0xFFFF 340 #define EFUSE_WR_DIS_S 0 341 342 #define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) 343 /* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 344 /*description: program for low 32bit WIFI_MAC_Address*/ 345 #define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF 346 #define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) 347 #define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 348 #define EFUSE_WIFI_MAC_CRC_LOW_S 0 349 350 #define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) 351 /* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ 352 /*description: program for high 24bit WIFI_MAC_Address*/ 353 #define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF 354 #define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) 355 #define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 356 #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 357 358 #define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) 359 /* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 360 /*description: */ 361 #define EFUSE_CHIP_VER_REV1 (BIT(15)) 362 #define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) 363 #define EFUSE_CHIP_VER_REV1_V 0x1 364 #define EFUSE_CHIP_VER_REV1_S 15 365 /* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 366 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 367 #define EFUSE_BLK3_PART_RESERVE (BIT(14)) 368 #define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) 369 #define EFUSE_BLK3_PART_RESERVE_V 0x1 370 #define EFUSE_BLK3_PART_RESERVE_S 14 371 /* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 372 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 373 #define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) 374 #define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) 375 #define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 376 #define EFUSE_CHIP_CPU_FREQ_RATED_S 13 377 /* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 378 /*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 379 #define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) 380 #define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) 381 #define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 382 #define EFUSE_CHIP_CPU_FREQ_LOW_S 12 383 /* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 384 /*description: least significant bits of chip package */ 385 #define EFUSE_CHIP_VER_PKG 0x00000007 386 #define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) 387 #define EFUSE_CHIP_VER_PKG_V 0x7 388 #define EFUSE_CHIP_VER_PKG_S 9 389 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 390 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 391 #define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 392 #define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 393 #define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 394 #define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 395 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ 396 /*description: program for SPI_pad_config_hd*/ 397 #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F 398 #define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) 399 #define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F 400 #define EFUSE_SPI_PAD_CONFIG_HD_S 4 401 /* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 402 /*description: */ 403 #define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) 404 #define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) 405 #define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 406 #define EFUSE_CHIP_VER_DIS_CACHE_S 3 407 /* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 408 /*description: most significant bit of chip package */ 409 #define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) 410 #define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) 411 #define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 412 #define EFUSE_CHIP_VER_PKG_4BIT_S 2 413 /* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 414 /*description: */ 415 #define EFUSE_CHIP_VER_DIS_BT (BIT(1)) 416 #define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) 417 #define EFUSE_CHIP_VER_DIS_BT_V 0x1 418 #define EFUSE_CHIP_VER_DIS_BT_S 1 419 /* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ 420 /*description: */ 421 #define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) 422 #define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 423 #define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 424 #define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 425 426 #define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) 427 /* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 428 /*description: program for sdio_force*/ 429 #define EFUSE_SDIO_FORCE (BIT(16)) 430 #define EFUSE_SDIO_FORCE_M (BIT(16)) 431 #define EFUSE_SDIO_FORCE_V 0x1 432 #define EFUSE_SDIO_FORCE_S 16 433 /* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ 434 /*description: program for SDIO_TIEH*/ 435 #define EFUSE_SDIO_TIEH (BIT(15)) 436 #define EFUSE_SDIO_TIEH_M (BIT(15)) 437 #define EFUSE_SDIO_TIEH_V 0x1 438 #define EFUSE_SDIO_TIEH_S 15 439 /* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ 440 /*description: program for XPD_SDIO_REG*/ 441 #define EFUSE_XPD_SDIO_REG (BIT(14)) 442 #define EFUSE_XPD_SDIO_REG_M (BIT(14)) 443 #define EFUSE_XPD_SDIO_REG_V 0x1 444 #define EFUSE_XPD_SDIO_REG_S 14 445 /* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 446 /*description: True ADC reference voltage */ 447 #define EFUSE_ADC_VREF 0x0000001F 448 #define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) 449 #define EFUSE_ADC_VREF_V 0x1F 450 #define EFUSE_ADC_VREF_S 8 451 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 452 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 453 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 454 /* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 455 /*description: */ 456 #define EFUSE_SDIO_DREFL 0x00000003 457 #define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) 458 #define EFUSE_SDIO_DREFL_V 0x3 459 #define EFUSE_SDIO_DREFL_S 12 460 /* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ 461 /*description: */ 462 #define EFUSE_SDIO_DREFM 0x00000003 463 #define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) 464 #define EFUSE_SDIO_DREFM_V 0x3 465 #define EFUSE_SDIO_DREFM_S 10 466 /* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ 467 /*description: */ 468 #define EFUSE_SDIO_DREFH 0x00000003 469 #define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) 470 #define EFUSE_SDIO_DREFH_V 0x3 471 #define EFUSE_SDIO_DREFH_S 8 472 /* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ 473 /*description: */ 474 #define EFUSE_CK8M_FREQ 0x000000FF 475 #define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) 476 #define EFUSE_CK8M_FREQ_V 0xFF 477 #define EFUSE_CK8M_FREQ_S 0 478 479 #define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) 480 /* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ 481 /*description: program for flash_crypt_config*/ 482 #define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F 483 #define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) 484 #define EFUSE_FLASH_CRYPT_CONFIG_V 0xF 485 #define EFUSE_FLASH_CRYPT_CONFIG_S 28 486 /* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ 487 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) 488 BIT[27] is the sign bit, 0: + , 1: - 489 BIT[26:24] is the difference value, unit: 0.017V 490 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 491 #define EFUSE_DIG_VOL_L6 0x0F 492 #define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 493 #define EFUSE_DIG_VOL_L6_V 0x0F 494 #define EFUSE_DIG_VOL_L6_S 24 495 /* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ 496 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 497 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ 498 #define EFUSE_VOL_LEVEL_HP_INV 0x03 499 #define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 500 #define EFUSE_VOL_LEVEL_HP_INV_V 0x03 501 #define EFUSE_VOL_LEVEL_HP_INV_S 22 502 /* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ 503 /* Deprecated */ 504 #define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ 505 #define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ 506 #define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ 507 #define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ 508 /* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ 509 /*description: program for SPI_pad_config_cs0*/ 510 #define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F 511 #define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) 512 #define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F 513 #define EFUSE_SPI_PAD_CONFIG_CS0_S 15 514 /* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ 515 /*description: program for SPI_pad_config_d*/ 516 #define EFUSE_SPI_PAD_CONFIG_D 0x0000001F 517 #define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) 518 #define EFUSE_SPI_PAD_CONFIG_D_V 0x1F 519 #define EFUSE_SPI_PAD_CONFIG_D_S 10 520 /* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ 521 /*description: program for SPI_pad_config_q*/ 522 #define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F 523 #define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) 524 #define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F 525 #define EFUSE_SPI_PAD_CONFIG_Q_S 5 526 /* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ 527 /*description: program for SPI_pad_config_clk*/ 528 #define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F 529 #define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) 530 #define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F 531 #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 532 533 #define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) 534 /* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ 535 /*description: program for key_status*/ 536 #define EFUSE_KEY_STATUS (BIT(10)) 537 #define EFUSE_KEY_STATUS_M (BIT(10)) 538 #define EFUSE_KEY_STATUS_V 0x1 539 #define EFUSE_KEY_STATUS_S 10 540 /* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 541 /*description: program for download_dis_cache*/ 542 #define EFUSE_DISABLE_DL_CACHE (BIT(9)) 543 #define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) 544 #define EFUSE_DISABLE_DL_CACHE_V 0x1 545 #define EFUSE_DISABLE_DL_CACHE_S 9 546 /* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ 547 /*description: program for download_dis_decrypt*/ 548 #define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) 549 #define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) 550 #define EFUSE_DISABLE_DL_DECRYPT_V 0x1 551 #define EFUSE_DISABLE_DL_DECRYPT_S 8 552 /* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ 553 /*description: program for download_dis_encrypt*/ 554 #define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) 555 #define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) 556 #define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 557 #define EFUSE_DISABLE_DL_ENCRYPT_S 7 558 /* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 559 /*description: program for JTAG_disable*/ 560 #define EFUSE_DISABLE_JTAG (BIT(6)) 561 #define EFUSE_DISABLE_JTAG_M (BIT(6)) 562 #define EFUSE_DISABLE_JTAG_V 0x1 563 #define EFUSE_DISABLE_JTAG_S 6 564 /* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 565 /*description: program for abstract_done_1*/ 566 #define EFUSE_ABS_DONE_1 (BIT(5)) 567 #define EFUSE_ABS_DONE_1_M (BIT(5)) 568 #define EFUSE_ABS_DONE_1_V 0x1 569 #define EFUSE_ABS_DONE_1_S 5 570 /* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 571 /*description: program for abstract_done_0*/ 572 #define EFUSE_ABS_DONE_0 (BIT(4)) 573 #define EFUSE_ABS_DONE_0_M (BIT(4)) 574 #define EFUSE_ABS_DONE_0_V 0x1 575 #define EFUSE_ABS_DONE_0_S 4 576 /* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 577 /*description: */ 578 #define EFUSE_DISABLE_SDIO_HOST (BIT(3)) 579 #define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) 580 #define EFUSE_DISABLE_SDIO_HOST_V 0x1 581 #define EFUSE_DISABLE_SDIO_HOST_S 3 582 /* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 583 /*description: program for console_debug_disable*/ 584 #define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) 585 #define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 586 #define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 587 #define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 588 /* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 589 /*description: program for coding_scheme*/ 590 #define EFUSE_CODING_SCHEME 0x00000003 591 #define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) 592 #define EFUSE_CODING_SCHEME_V 0x3 593 #define EFUSE_CODING_SCHEME_S 0 594 595 #define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) 596 /* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 597 /*description: read for BLOCK1*/ 598 #define EFUSE_BLK1_DOUT0 0xFFFFFFFF 599 #define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) 600 #define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF 601 #define EFUSE_BLK1_DOUT0_S 0 602 603 #define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) 604 /* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 605 /*description: read for BLOCK1*/ 606 #define EFUSE_BLK1_DOUT1 0xFFFFFFFF 607 #define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) 608 #define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF 609 #define EFUSE_BLK1_DOUT1_S 0 610 611 #define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) 612 /* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 613 /*description: read for BLOCK1*/ 614 #define EFUSE_BLK1_DOUT2 0xFFFFFFFF 615 #define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) 616 #define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF 617 #define EFUSE_BLK1_DOUT2_S 0 618 619 #define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) 620 /* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 621 /*description: read for BLOCK1*/ 622 #define EFUSE_BLK1_DOUT3 0xFFFFFFFF 623 #define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) 624 #define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF 625 #define EFUSE_BLK1_DOUT3_S 0 626 627 #define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) 628 /* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 629 /*description: read for BLOCK1*/ 630 #define EFUSE_BLK1_DOUT4 0xFFFFFFFF 631 #define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) 632 #define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF 633 #define EFUSE_BLK1_DOUT4_S 0 634 635 #define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) 636 /* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 637 /*description: read for BLOCK1*/ 638 #define EFUSE_BLK1_DOUT5 0xFFFFFFFF 639 #define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) 640 #define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF 641 #define EFUSE_BLK1_DOUT5_S 0 642 643 #define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) 644 /* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 645 /*description: read for BLOCK1*/ 646 #define EFUSE_BLK1_DOUT6 0xFFFFFFFF 647 #define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) 648 #define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF 649 #define EFUSE_BLK1_DOUT6_S 0 650 651 #define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) 652 /* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 653 /*description: read for BLOCK1*/ 654 #define EFUSE_BLK1_DOUT7 0xFFFFFFFF 655 #define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) 656 #define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF 657 #define EFUSE_BLK1_DOUT7_S 0 658 659 #define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) 660 /* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 661 /*description: read for BLOCK2*/ 662 #define EFUSE_BLK2_DOUT0 0xFFFFFFFF 663 #define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) 664 #define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF 665 #define EFUSE_BLK2_DOUT0_S 0 666 667 #define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) 668 /* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 669 /*description: read for BLOCK2*/ 670 #define EFUSE_BLK2_DOUT1 0xFFFFFFFF 671 #define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) 672 #define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF 673 #define EFUSE_BLK2_DOUT1_S 0 674 675 #define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) 676 /* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 677 /*description: read for BLOCK2*/ 678 #define EFUSE_BLK2_DOUT2 0xFFFFFFFF 679 #define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) 680 #define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF 681 #define EFUSE_BLK2_DOUT2_S 0 682 683 #define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) 684 /* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 685 /*description: read for BLOCK2*/ 686 #define EFUSE_BLK2_DOUT3 0xFFFFFFFF 687 #define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) 688 #define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF 689 #define EFUSE_BLK2_DOUT3_S 0 690 691 #define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) 692 /* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 693 /*description: read for BLOCK2*/ 694 #define EFUSE_BLK2_DOUT4 0xFFFFFFFF 695 #define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) 696 #define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF 697 #define EFUSE_BLK2_DOUT4_S 0 698 699 #define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) 700 /* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 701 /*description: read for BLOCK2*/ 702 #define EFUSE_BLK2_DOUT5 0xFFFFFFFF 703 #define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) 704 #define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF 705 #define EFUSE_BLK2_DOUT5_S 0 706 707 #define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) 708 /* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 709 /*description: read for BLOCK2*/ 710 #define EFUSE_BLK2_DOUT6 0xFFFFFFFF 711 #define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) 712 #define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF 713 #define EFUSE_BLK2_DOUT6_S 0 714 715 #define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) 716 /* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 717 /*description: read for BLOCK2*/ 718 #define EFUSE_BLK2_DOUT7 0xFFFFFFFF 719 #define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) 720 #define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF 721 #define EFUSE_BLK2_DOUT7_S 0 722 723 #define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) 724 /* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 725 /*description: read for BLOCK3*/ 726 #define EFUSE_BLK3_DOUT0 0xFFFFFFFF 727 #define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) 728 #define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF 729 #define EFUSE_BLK3_DOUT0_S 0 730 731 #define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) 732 /* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 733 /*description: read for BLOCK3*/ 734 #define EFUSE_BLK3_DOUT1 0xFFFFFFFF 735 #define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) 736 #define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF 737 #define EFUSE_BLK3_DOUT1_S 0 738 739 #define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) 740 /* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 741 /*description: read for BLOCK3*/ 742 #define EFUSE_BLK3_DOUT2 0xFFFFFFFF 743 #define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) 744 #define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF 745 #define EFUSE_BLK3_DOUT2_S 0 746 747 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 748 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 749 #define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) 750 /* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 751 /*description: read for BLOCK3*/ 752 #define EFUSE_BLK3_DOUT3 0xFFFFFFFF 753 #define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) 754 #define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF 755 #define EFUSE_BLK3_DOUT3_S 0 756 /* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 757 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 758 #define EFUSE_RD_ADC2_TP_HIGH 0x1FF 759 #define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) 760 #define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF 761 #define EFUSE_RD_ADC2_TP_HIGH_S 23 762 /* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 763 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 764 #define EFUSE_RD_ADC2_TP_LOW 0x7F 765 #define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) 766 #define EFUSE_RD_ADC2_TP_LOW_V 0x7F 767 #define EFUSE_RD_ADC2_TP_LOW_S 16 768 /* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 769 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 770 #define EFUSE_RD_ADC1_TP_HIGH 0x1FF 771 #define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) 772 #define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF 773 #define EFUSE_RD_ADC1_TP_HIGH_S 7 774 /* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 775 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 776 #define EFUSE_RD_ADC1_TP_LOW 0x7F 777 #define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) 778 #define EFUSE_RD_ADC1_TP_LOW_V 0x7F 779 #define EFUSE_RD_ADC1_TP_LOW_S 0 780 781 #define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) 782 /* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 783 /*description: read for BLOCK3*/ 784 #define EFUSE_BLK3_DOUT4 0xFFFFFFFF 785 #define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) 786 #define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF 787 #define EFUSE_BLK3_DOUT4_S 0 788 /* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 789 /*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ 790 #define EFUSE_RD_CAL_RESERVED 0x0000FFFF 791 #define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) 792 #define EFUSE_RD_CAL_RESERVED_V 0xFFFF 793 #define EFUSE_RD_CAL_RESERVED_S 0 794 795 #define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) 796 /* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 797 /*description: read for BLOCK3*/ 798 #define EFUSE_BLK3_DOUT5 0xFFFFFFFF 799 #define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) 800 #define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF 801 #define EFUSE_BLK3_DOUT5_S 0 802 803 #define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) 804 /* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 805 /*description: read for BLOCK3*/ 806 #define EFUSE_BLK3_DOUT6 0xFFFFFFFF 807 #define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) 808 #define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF 809 #define EFUSE_BLK3_DOUT6_S 0 810 811 #define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) 812 /* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 813 /*description: read for BLOCK3*/ 814 #define EFUSE_BLK3_DOUT7 0xFFFFFFFF 815 #define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) 816 #define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF 817 #define EFUSE_BLK3_DOUT7_S 0 818 819 #define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) 820 /* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 821 /*description: program for BLOCK1*/ 822 #define EFUSE_BLK1_DIN0 0xFFFFFFFF 823 #define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) 824 #define EFUSE_BLK1_DIN0_V 0xFFFFFFFF 825 #define EFUSE_BLK1_DIN0_S 0 826 827 #define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) 828 /* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 829 /*description: program for BLOCK1*/ 830 #define EFUSE_BLK1_DIN1 0xFFFFFFFF 831 #define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) 832 #define EFUSE_BLK1_DIN1_V 0xFFFFFFFF 833 #define EFUSE_BLK1_DIN1_S 0 834 835 #define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) 836 /* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 837 /*description: program for BLOCK1*/ 838 #define EFUSE_BLK1_DIN2 0xFFFFFFFF 839 #define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) 840 #define EFUSE_BLK1_DIN2_V 0xFFFFFFFF 841 #define EFUSE_BLK1_DIN2_S 0 842 843 #define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) 844 /* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 845 /*description: program for BLOCK1*/ 846 #define EFUSE_BLK1_DIN3 0xFFFFFFFF 847 #define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) 848 #define EFUSE_BLK1_DIN3_V 0xFFFFFFFF 849 #define EFUSE_BLK1_DIN3_S 0 850 851 #define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) 852 /* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 853 /*description: program for BLOCK1*/ 854 #define EFUSE_BLK1_DIN4 0xFFFFFFFF 855 #define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) 856 #define EFUSE_BLK1_DIN4_V 0xFFFFFFFF 857 #define EFUSE_BLK1_DIN4_S 0 858 859 #define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) 860 /* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 861 /*description: program for BLOCK1*/ 862 #define EFUSE_BLK1_DIN5 0xFFFFFFFF 863 #define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) 864 #define EFUSE_BLK1_DIN5_V 0xFFFFFFFF 865 #define EFUSE_BLK1_DIN5_S 0 866 867 #define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) 868 /* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 869 /*description: program for BLOCK1*/ 870 #define EFUSE_BLK1_DIN6 0xFFFFFFFF 871 #define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) 872 #define EFUSE_BLK1_DIN6_V 0xFFFFFFFF 873 #define EFUSE_BLK1_DIN6_S 0 874 875 #define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) 876 /* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 877 /*description: program for BLOCK1*/ 878 #define EFUSE_BLK1_DIN7 0xFFFFFFFF 879 #define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) 880 #define EFUSE_BLK1_DIN7_V 0xFFFFFFFF 881 #define EFUSE_BLK1_DIN7_S 0 882 883 #define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) 884 /* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 885 /*description: program for BLOCK2*/ 886 #define EFUSE_BLK2_DIN0 0xFFFFFFFF 887 #define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) 888 #define EFUSE_BLK2_DIN0_V 0xFFFFFFFF 889 #define EFUSE_BLK2_DIN0_S 0 890 891 #define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) 892 /* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 893 /*description: program for BLOCK2*/ 894 #define EFUSE_BLK2_DIN1 0xFFFFFFFF 895 #define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) 896 #define EFUSE_BLK2_DIN1_V 0xFFFFFFFF 897 #define EFUSE_BLK2_DIN1_S 0 898 899 #define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) 900 /* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 901 /*description: program for BLOCK2*/ 902 #define EFUSE_BLK2_DIN2 0xFFFFFFFF 903 #define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) 904 #define EFUSE_BLK2_DIN2_V 0xFFFFFFFF 905 #define EFUSE_BLK2_DIN2_S 0 906 907 #define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) 908 /* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 909 /*description: program for BLOCK2*/ 910 #define EFUSE_BLK2_DIN3 0xFFFFFFFF 911 #define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) 912 #define EFUSE_BLK2_DIN3_V 0xFFFFFFFF 913 #define EFUSE_BLK2_DIN3_S 0 914 915 #define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) 916 /* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 917 /*description: program for BLOCK2*/ 918 #define EFUSE_BLK2_DIN4 0xFFFFFFFF 919 #define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) 920 #define EFUSE_BLK2_DIN4_V 0xFFFFFFFF 921 #define EFUSE_BLK2_DIN4_S 0 922 923 #define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) 924 /* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 925 /*description: program for BLOCK2*/ 926 #define EFUSE_BLK2_DIN5 0xFFFFFFFF 927 #define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) 928 #define EFUSE_BLK2_DIN5_V 0xFFFFFFFF 929 #define EFUSE_BLK2_DIN5_S 0 930 931 #define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) 932 /* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 933 /*description: program for BLOCK2*/ 934 #define EFUSE_BLK2_DIN6 0xFFFFFFFF 935 #define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) 936 #define EFUSE_BLK2_DIN6_V 0xFFFFFFFF 937 #define EFUSE_BLK2_DIN6_S 0 938 939 #define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) 940 /* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 941 /*description: program for BLOCK2*/ 942 #define EFUSE_BLK2_DIN7 0xFFFFFFFF 943 #define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) 944 #define EFUSE_BLK2_DIN7_V 0xFFFFFFFF 945 #define EFUSE_BLK2_DIN7_S 0 946 947 #define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) 948 /* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 949 /*description: program for BLOCK3*/ 950 #define EFUSE_BLK3_DIN0 0xFFFFFFFF 951 #define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) 952 #define EFUSE_BLK3_DIN0_V 0xFFFFFFFF 953 #define EFUSE_BLK3_DIN0_S 0 954 955 #define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) 956 /* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 957 /*description: program for BLOCK3*/ 958 #define EFUSE_BLK3_DIN1 0xFFFFFFFF 959 #define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) 960 #define EFUSE_BLK3_DIN1_V 0xFFFFFFFF 961 #define EFUSE_BLK3_DIN1_S 0 962 963 #define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) 964 /* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 965 /*description: program for BLOCK3*/ 966 #define EFUSE_BLK3_DIN2 0xFFFFFFFF 967 #define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) 968 #define EFUSE_BLK3_DIN2_V 0xFFFFFFFF 969 #define EFUSE_BLK3_DIN2_S 0 970 971 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 972 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 973 #define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) 974 /* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 975 /*description: program for BLOCK3*/ 976 #define EFUSE_BLK3_DIN3 0xFFFFFFFF 977 #define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) 978 #define EFUSE_BLK3_DIN3_V 0xFFFFFFFF 979 #define EFUSE_BLK3_DIN3_S 0 980 /* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 981 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 982 #define EFUSE_ADC2_TP_HIGH 0x1FF 983 #define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) 984 #define EFUSE_ADC2_TP_HIGH_V 0x1FF 985 #define EFUSE_ADC2_TP_HIGH_S 23 986 /* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 987 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 988 #define EFUSE_ADC2_TP_LOW 0x7F 989 #define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) 990 #define EFUSE_ADC2_TP_LOW_V 0x7F 991 #define EFUSE_ADC2_TP_LOW_S 16 992 /* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 993 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 994 #define EFUSE_ADC1_TP_HIGH 0x1FF 995 #define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) 996 #define EFUSE_ADC1_TP_HIGH_V 0x1FF 997 #define EFUSE_ADC1_TP_HIGH_S 7 998 /* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 999 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 1000 #define EFUSE_ADC1_TP_LOW 0x7F 1001 #define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) 1002 #define EFUSE_ADC1_TP_LOW_V 0x7F 1003 #define EFUSE_ADC1_TP_LOW_S 0 1004 1005 #define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) 1006 /* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1007 /*description: program for BLOCK3*/ 1008 #define EFUSE_BLK3_DIN4 0xFFFFFFFF 1009 #define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) 1010 #define EFUSE_BLK3_DIN4_V 0xFFFFFFFF 1011 #define EFUSE_BLK3_DIN4_S 0 1012 /* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 1013 /*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ 1014 #define EFUSE_CAL_RESERVED 0x0000FFFF 1015 #define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) 1016 #define EFUSE_CAL_RESERVED_V 0xFFFF 1017 #define EFUSE_CAL_RESERVED_S 0 1018 1019 #define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) 1020 /* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1021 /*description: program for BLOCK3*/ 1022 #define EFUSE_BLK3_DIN5 0xFFFFFFFF 1023 #define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) 1024 #define EFUSE_BLK3_DIN5_V 0xFFFFFFFF 1025 #define EFUSE_BLK3_DIN5_S 0 1026 1027 #define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) 1028 /* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1029 /*description: program for BLOCK3*/ 1030 #define EFUSE_BLK3_DIN6 0xFFFFFFFF 1031 #define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) 1032 #define EFUSE_BLK3_DIN6_V 0xFFFFFFFF 1033 #define EFUSE_BLK3_DIN6_S 0 1034 1035 #define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) 1036 /* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1037 /*description: program for BLOCK3*/ 1038 #define EFUSE_BLK3_DIN7 0xFFFFFFFF 1039 #define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) 1040 #define EFUSE_BLK3_DIN7_V 0xFFFFFFFF 1041 #define EFUSE_BLK3_DIN7_S 0 1042 1043 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) 1044 /* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 1045 /*description: */ 1046 #define EFUSE_CLK_EN (BIT(16)) 1047 #define EFUSE_CLK_EN_M (BIT(16)) 1048 #define EFUSE_CLK_EN_V 0x1 1049 #define EFUSE_CLK_EN_S 16 1050 /* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ 1051 /*description: efuse timing configure*/ 1052 #define EFUSE_CLK_SEL1 0x000000FF 1053 #define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) 1054 #define EFUSE_CLK_SEL1_V 0xFF 1055 #define EFUSE_CLK_SEL1_S 8 1056 /* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ 1057 /*description: efuse timing configure*/ 1058 #define EFUSE_CLK_SEL0 0x000000FF 1059 #define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) 1060 #define EFUSE_CLK_SEL0_V 0xFF 1061 #define EFUSE_CLK_SEL0_S 0 1062 1063 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) 1064 /* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ 1065 /*description: */ 1066 #define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) 1067 #define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) 1068 #define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 1069 #define EFUSE_FORCE_NO_WR_RD_DIS_S 16 1070 /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 1071 /*description: efuse operation code*/ 1072 #define EFUSE_OP_CODE 0x0000FFFF 1073 #define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) 1074 #define EFUSE_OP_CODE_V 0xFFFF 1075 #define EFUSE_OP_CODE_S 0 1076 1077 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) 1078 /* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1079 /*description: */ 1080 #define EFUSE_DEBUG 0xFFFFFFFF 1081 #define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) 1082 #define EFUSE_DEBUG_V 0xFFFFFFFF 1083 #define EFUSE_DEBUG_S 0 1084 1085 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) 1086 /* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1087 /*description: command for program*/ 1088 #define EFUSE_PGM_CMD (BIT(1)) 1089 #define EFUSE_PGM_CMD_M (BIT(1)) 1090 #define EFUSE_PGM_CMD_V 0x1 1091 #define EFUSE_PGM_CMD_S 1 1092 /* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1093 /*description: command for read*/ 1094 #define EFUSE_READ_CMD (BIT(0)) 1095 #define EFUSE_READ_CMD_M (BIT(0)) 1096 #define EFUSE_READ_CMD_V 0x1 1097 #define EFUSE_READ_CMD_S 0 1098 1099 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) 1100 /* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1101 /*description: program done interrupt raw status*/ 1102 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 1103 #define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) 1104 #define EFUSE_PGM_DONE_INT_RAW_V 0x1 1105 #define EFUSE_PGM_DONE_INT_RAW_S 1 1106 /* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1107 /*description: read done interrupt raw status*/ 1108 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 1109 #define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) 1110 #define EFUSE_READ_DONE_INT_RAW_V 0x1 1111 #define EFUSE_READ_DONE_INT_RAW_S 0 1112 1113 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) 1114 /* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1115 /*description: program done interrupt status*/ 1116 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 1117 #define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) 1118 #define EFUSE_PGM_DONE_INT_ST_V 0x1 1119 #define EFUSE_PGM_DONE_INT_ST_S 1 1120 /* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1121 /*description: read done interrupt status*/ 1122 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 1123 #define EFUSE_READ_DONE_INT_ST_M (BIT(0)) 1124 #define EFUSE_READ_DONE_INT_ST_V 0x1 1125 #define EFUSE_READ_DONE_INT_ST_S 0 1126 1127 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) 1128 /* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1129 /*description: program done interrupt enable*/ 1130 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 1131 #define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) 1132 #define EFUSE_PGM_DONE_INT_ENA_V 0x1 1133 #define EFUSE_PGM_DONE_INT_ENA_S 1 1134 /* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1135 /*description: read done interrupt enable*/ 1136 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 1137 #define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) 1138 #define EFUSE_READ_DONE_INT_ENA_V 0x1 1139 #define EFUSE_READ_DONE_INT_ENA_S 0 1140 1141 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) 1142 /* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1143 /*description: program done interrupt clear*/ 1144 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 1145 #define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) 1146 #define EFUSE_PGM_DONE_INT_CLR_V 0x1 1147 #define EFUSE_PGM_DONE_INT_CLR_S 1 1148 /* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1149 /*description: read done interrupt clear*/ 1150 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 1151 #define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) 1152 #define EFUSE_READ_DONE_INT_CLR_V 0x1 1153 #define EFUSE_READ_DONE_INT_CLR_S 0 1154 1155 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) 1156 /* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1157 /*description: */ 1158 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 1159 #define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) 1160 #define EFUSE_DAC_CLK_PAD_SEL_V 0x1 1161 #define EFUSE_DAC_CLK_PAD_SEL_S 8 1162 /* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ 1163 /*description: efuse timing configure*/ 1164 #define EFUSE_DAC_CLK_DIV 0x000000FF 1165 #define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) 1166 #define EFUSE_DAC_CLK_DIV_V 0xFF 1167 #define EFUSE_DAC_CLK_DIV_S 0 1168 1169 #define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) 1170 /* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ 1171 /*description: the decode result of 3/4 coding scheme has warning*/ 1172 #define EFUSE_DEC_WARNINGS 0x00000FFF 1173 #define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) 1174 #define EFUSE_DEC_WARNINGS_V 0xFFF 1175 #define EFUSE_DEC_WARNINGS_S 0 1176 1177 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) 1178 /* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ 1179 /*description: */ 1180 #define EFUSE_DATE 0xFFFFFFFF 1181 #define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) 1182 #define EFUSE_DATE_V 0xFFFFFFFF 1183 #define EFUSE_DATE_S 0 1184 1185 1186 1187 1188 #endif /*_SOC_EFUSE_REG_H_ */ 1189
