1 /* 2 * xtensa/corebits.h - Xtensa Special Register field positions, masks, values. 3 * 4 * (In previous releases, these were defined in specreg.h, a generated file. 5 * This file is not generated, ie. it is processor configuration independent.) 6 */ 7 8 /* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/corebits.h#1 $ */ 9 10 /* 11 * Copyright (c) 2005-2011 Tensilica Inc. 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining 14 * a copy of this software and associated documentation files (the 15 * "Software"), to deal in the Software without restriction, including 16 * without limitation the rights to use, copy, modify, merge, publish, 17 * distribute, sublicense, and/or sell copies of the Software, and to 18 * permit persons to whom the Software is furnished to do so, subject to 19 * the following conditions: 20 * 21 * The above copyright notice and this permission notice shall be included 22 * in all copies or substantial portions of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 31 */ 32 33 #ifndef XTENSA_COREBITS_H 34 #define XTENSA_COREBITS_H 35 36 /* EXCCAUSE register fields: */ 37 #define EXCCAUSE_EXCCAUSE_SHIFT 0 38 #define EXCCAUSE_EXCCAUSE_MASK 0x3F 39 /* EXCCAUSE register values: */ 40 /* 41 * General Exception Causes 42 * (values of EXCCAUSE special register set by general exceptions, 43 * which vector to the user, kernel, or double-exception vectors). 44 */ 45 #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ 46 #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ 47 #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ 48 # define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ 49 #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ 50 # define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ 51 #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ 52 # define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ 53 #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ 54 #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ 55 # define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (deprecated) */ 56 #define EXCCAUSE_PC_ERROR 7 /* Next PC Value Illegal */ 57 #define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ 58 #define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ 59 #define EXCCAUSE_EXTREG_PRIVILEGE 10 /* External Register Privilege Error */ 60 #define EXCCAUSE_EXCLUSIVE_ERROR 11 /* Load exclusive to unsupported memory type or unaligned address */ 61 #define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ 62 #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ 63 #define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ 64 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ 65 #define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ 66 #define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ 67 #define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ 68 /* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ 69 #define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ 70 /* Reserved 21..23 */ 71 #define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ 72 #define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ 73 #define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ 74 /* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ 75 #define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ 76 #define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ 77 /* Reserved 30..31 */ 78 #define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ 79 #define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ 80 #define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ 81 #define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ 82 #define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ 83 #define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ 84 #define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ 85 #define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ 86 #define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ 87 /* Reserved 40..63 */ 88 89 /* PS register fields: */ 90 #define PS_WOE_SHIFT 18 91 #define PS_WOE_MASK 0x00040000 92 #define PS_WOE PS_WOE_MASK 93 #define PS_CALLINC_SHIFT 16 94 #define PS_CALLINC_MASK 0x00030000 95 #define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */ 96 #define PS_OWB_SHIFT 8 97 #define PS_OWB_MASK 0x00000F00 98 #define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */ 99 #define PS_RING_SHIFT 6 100 #define PS_RING_MASK 0x000000C0 101 #define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */ 102 #define PS_UM_SHIFT 5 103 #define PS_UM_MASK 0x00000020 104 #define PS_UM PS_UM_MASK 105 #define PS_EXCM_SHIFT 4 106 #define PS_EXCM_MASK 0x00000010 107 #define PS_EXCM PS_EXCM_MASK 108 #define PS_INTLEVEL_SHIFT 0 109 #define PS_INTLEVEL_MASK 0x0000000F 110 #define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */ 111 /* ABI-derived field values: */ 112 #ifdef __XTENSA_CALL0_ABI__ 113 #define PS_WOE_ABI 0 114 #define PS_WOECALL4_ABI 0 115 #else 116 #define PS_WOE_ABI PS_WOE /* 0x40000 */ 117 #define PS_WOECALL4_ABI (PS_WOE | PS_CALLINC(1)) /* 0x50000, per call4 */ 118 #endif 119 /* Backward compatibility (deprecated): */ 120 #define PS_PROGSTACK_SHIFT PS_UM_SHIFT 121 #define PS_PROGSTACK_MASK PS_UM_MASK 122 #define PS_PROG_SHIFT PS_UM_SHIFT 123 #define PS_PROG_MASK PS_UM_MASK 124 #define PS_PROG PS_UM 125 126 /* DBREAKCn register fields: */ 127 #define DBREAKC_MASK_SHIFT 0 128 #define DBREAKC_MASK_MASK 0x0000003F 129 #define DBREAKC_LOADBREAK_SHIFT 30 130 #define DBREAKC_LOADBREAK_MASK 0x40000000 131 #define DBREAKC_STOREBREAK_SHIFT 31 132 #define DBREAKC_STOREBREAK_MASK 0x80000000 133 134 /* DEBUGCAUSE register fields: */ 135 #define DEBUGCAUSE_DEBUGINT_SHIFT 5 136 #define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */ 137 #define DEBUGCAUSE_BREAKN_SHIFT 4 138 #define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */ 139 #define DEBUGCAUSE_BREAK_SHIFT 3 140 #define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */ 141 #define DEBUGCAUSE_DBREAK_SHIFT 2 142 #define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */ 143 #define DEBUGCAUSE_IBREAK_SHIFT 1 144 #define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */ 145 #define DEBUGCAUSE_ICOUNT_SHIFT 0 146 #define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */ 147 148 /* MESR register fields: */ 149 #define MESR_MEME 0x00000001 /* memory error */ 150 #define MESR_MEME_SHIFT 0 151 #define MESR_DME 0x00000002 /* double memory error */ 152 #define MESR_DME_SHIFT 1 153 #define MESR_RCE 0x00000010 /* recorded memory error */ 154 #define MESR_RCE_SHIFT 4 155 #define MESR_LCE 156 #define MESR_LCE_SHIFT ? 157 #define MESR_LCE_L 158 #define MESR_ERRENAB 0x00000100 159 #define MESR_ERRENAB_SHIFT 8 160 #define MESR_ERRTEST 0x00000200 161 #define MESR_ERRTEST_SHIFT 9 162 #define MESR_DATEXC 0x00000400 163 #define MESR_DATEXC_SHIFT 10 164 #define MESR_INSEXC 0x00000800 165 #define MESR_INSEXC_SHIFT 11 166 #define MESR_WAYNUM_SHIFT 16 167 #define MESR_ACCTYPE_SHIFT 20 168 #define MESR_MEMTYPE_SHIFT 24 169 #define MESR_ERRTYPE_SHIFT 30 170 171 /* MEMCTL register fields: */ 172 #define MEMCTL_SNOOP_EN_SHIFT 1 173 #define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */ 174 #define MEMCTL_L0IBUF_EN_SHIFT 0 175 #define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */ 176 #define MEMCTL_INV_EN_SHIFT 23 177 #define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */ 178 #define MEMCTL_DCWU_SHIFT 8 179 #define MEMCTL_DCWU_BITS 5 180 #define MEMCTL_DCWA_SHIFT 13 181 #define MEMCTL_DCWA_BITS 5 182 #define MEMCTL_ICWU_SHIFT 18 183 #define MEMCTL_ICWU_BITS 5 184 #define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */ 185 #define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */ 186 #define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */ 187 #define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK) 188 #define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK) 189 #define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK) 190 #define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK) 191 #define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK) 192 193 194 #endif /*XTENSA_COREBITS_H*/ 195
