Searched refs:BIT (Results 1 – 25 of 334) sorted by relevance
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22 #define SLC_SLC1_TOKEN_SEL (BIT(31))23 #define SLC_SLC1_TOKEN_SEL_M (BIT(31))28 #define SLC_SLC1_TOKEN_AUTO_CLR (BIT(30))29 #define SLC_SLC1_TOKEN_AUTO_CLR_M (BIT(30))34 #define SLC_SLC1_TXDATA_BURST_EN (BIT(29))35 #define SLC_SLC1_TXDATA_BURST_EN_M (BIT(29))40 #define SLC_SLC1_TXDSCR_BURST_EN (BIT(28))41 #define SLC_SLC1_TXDSCR_BURST_EN_M (BIT(28))46 #define SLC_SLC1_TXLINK_AUTO_RET (BIT(27))47 #define SLC_SLC1_TXLINK_AUTO_RET_M (BIT(27))[all …]
22 #define HOST_SLC_FUNC2_INT (BIT(24))23 #define HOST_SLC_FUNC2_INT_M (BIT(24))30 #define HOST_SLC_FUNC2_INT_EN (BIT(0))31 #define HOST_SLC_FUNC2_INT_EN_M (BIT(0))38 #define HOST_SLC_FUNC1_MDSTAT (BIT(0))39 #define HOST_SLC_FUNC1_MDSTAT_M (BIT(0))90 #define HOST_SLC0_RX_PF_VALID (BIT(12))91 #define HOST_SLC0_RX_PF_VALID_M (BIT(12))120 #define HOST_GPIO_SDIO_INT_RAW (BIT(25))121 #define HOST_GPIO_SDIO_INT_RAW_M (BIT(25))[all …]
34 #define RTC_CNTL_SW_SYS_RST (BIT(31))35 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))40 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))41 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))46 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))47 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))52 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))53 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))58 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))59 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))[all …]
102 #define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))103 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))115 #define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))116 #define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))123 #define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))124 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))136 #define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))137 #define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))144 #define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))145 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))[all …]
38 #define RMT_CLK_EN (BIT(31))39 #define RMT_CLK_EN_M (BIT(31))44 #define RMT_MEM_PD (BIT(30))45 #define RMT_MEM_PD_M (BIT(30))51 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29))52 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))57 #define RMT_CARRIER_EN_CH0 (BIT(28))58 #define RMT_CARRIER_EN_CH0_M (BIT(28))85 #define RMT_IDLE_OUT_EN_CH0 (BIT(19))86 #define RMT_IDLE_OUT_EN_CH0_M (BIT(19))[all …]
26 #define GDMA_MEM_TRANS_EN_CH0 (BIT(10))27 #define GDMA_MEM_TRANS_EN_CH0_M (BIT(10))33 #define GDMA_IN_DATA_BURST_EN_CH0 (BIT(9))34 #define GDMA_IN_DATA_BURST_EN_CH0_M (BIT(9))40 #define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(8))41 #define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(8))47 #define GDMA_INDSCR_BURST_EN_CH0 (BIT(7))48 #define GDMA_INDSCR_BURST_EN_CH0_M (BIT(7))54 #define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(6))55 #define GDMA_OUTDSCR_BURST_EN_CH0_M (BIT(6))[all …]
25 #define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18))26 #define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18))31 #define SLC_SLC0_TOKEN_SEL (BIT(15))32 #define SLC_SLC0_TOKEN_SEL_M (BIT(15))37 #define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14))38 #define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14))43 #define SLC_SLC0_TXDATA_BURST_EN (BIT(13))44 #define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13))49 #define SLC_SLC0_TXDSCR_BURST_EN (BIT(12))50 #define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12))[all …]
43 #define RTC_CNTL_SW_SYS_RST (BIT(31))44 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))49 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))50 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))55 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))56 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))61 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))62 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))67 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))68 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))[all …]
41 #define RMT_CONF_UPDATE_CH0 (BIT(24))42 #define RMT_CONF_UPDATE_CH0_M (BIT(24))47 #define RMT_AFIFO_RST_CH0 (BIT(23))48 #define RMT_AFIFO_RST_CH0_M (BIT(23))53 #define RMT_CARRIER_OUT_LV_CH0 (BIT(22))54 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(22))59 #define RMT_CARRIER_EN_CH0 (BIT(21))60 #define RMT_CARRIER_EN_CH0_M (BIT(21))65 #define RMT_CARRIER_EFF_EN_CH0 (BIT(20))66 #define RMT_CARRIER_EFF_EN_CH0_M (BIT(20))[all …]
105 #define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))106 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))118 #define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))119 #define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))126 #define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))127 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))139 #define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))140 #define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))147 #define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))148 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))[all …]
25 #define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON (BIT(2))26 #define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_M (BIT(2))39 #define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP (BIT(5))40 #define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_M (BIT(5))45 #define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN (BIT(4))46 #define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_M (BIT(4))89 #define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2))90 #define SYSTEM_CONTROL_CORE_1_RESETING_M (BIT(2))95 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1))96 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1))[all …]
26 #define SPI_USR (BIT(24))27 #define SPI_USR_M (BIT(24))33 #define SPI_UPDATE (BIT(23))34 #define SPI_UPDATE_M (BIT(23))56 #define SPI_WR_BIT_ORDER (BIT(26))57 #define SPI_WR_BIT_ORDER_M (BIT(26))63 #define SPI_RD_BIT_ORDER (BIT(25))64 #define SPI_RD_BIT_ORDER_M (BIT(25))70 #define SPI_WP_POL (BIT(21))71 #define SPI_WP_POL_M (BIT(21))[all …]
26 #define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12))27 #define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (BIT(12))33 #define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11))34 #define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (BIT(11))40 #define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10))41 #define DMA_INFIFO_UDF_CH0_INT_RAW_M (BIT(10))47 #define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9))48 #define DMA_INFIFO_OVF_CH0_INT_RAW_M (BIT(9))54 #define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8))55 #define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8))[all …]
25 #define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))26 #define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7))31 #define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))32 #define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6))39 #define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7))40 #define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7))45 #define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6))46 #define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6))59 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3))60 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))[all …]
33 #define RMT_CONF_UPDATE_CH0 (BIT(24))34 #define RMT_CONF_UPDATE_CH0_M (BIT(24))39 #define RMT_AFIFO_RST_CH0 (BIT(23))40 #define RMT_AFIFO_RST_CH0_M (BIT(23))45 #define RMT_CARRIER_OUT_LV_CH0 (BIT(22))46 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(22))51 #define RMT_CARRIER_EN_CH0 (BIT(21))52 #define RMT_CARRIER_EN_CH0_M (BIT(21))57 #define RMT_CARRIER_EFF_EN_CH0 (BIT(20))58 #define RMT_CARRIER_EFF_EN_CH0_M (BIT(20))[all …]
28 #define SPI_USR (BIT(24))29 #define SPI_USR_M (BIT(24))35 #define SPI_UPDATE (BIT(23))36 #define SPI_UPDATE_M (BIT(23))58 #define SPI_WR_BIT_ORDER (BIT(26))59 #define SPI_WR_BIT_ORDER_M (BIT(26))65 #define SPI_RD_BIT_ORDER (BIT(25))66 #define SPI_RD_BIT_ORDER_M (BIT(25))72 #define SPI_WP_POL (BIT(21))73 #define SPI_WP_POL_M (BIT(21))[all …]
34 #define UART_WAKEUP_INT_RAW (BIT(19))35 #define UART_WAKEUP_INT_RAW_M (BIT(19))41 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))42 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))48 #define UART_RS485_CLASH_INT_RAW (BIT(17))49 #define UART_RS485_CLASH_INT_RAW_M (BIT(17))55 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))56 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))62 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))63 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))[all …]
40 #define RTC_CNTL_SW_SYS_RST (BIT(31))41 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))46 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))47 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))52 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))53 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))58 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))59 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))64 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))65 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))[all …]
25 #define DPORT_PMS_SDIO_LOCK (BIT(0))26 #define DPORT_PMS_SDIO_LOCK_M (BIT(0))33 #define DPORT_PMS_SDIO_DISABLE (BIT(0))34 #define DPORT_PMS_SDIO_DISABLE_M (BIT(0))41 #define DPORT_PMS_MAC_DUMP_LOCK (BIT(0))42 #define DPORT_PMS_MAC_DUMP_LOCK_M (BIT(0))57 #define DPORT_PMS_PRO_IRAM0_LOCK (BIT(0))58 #define DPORT_PMS_PRO_IRAM0_LOCK_M (BIT(0))65 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W (BIT(11))66 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W_M (BIT(11))[all …]
33 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29))34 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))39 #define RMT_CARRIER_EN_CH0 (BIT(28))40 #define RMT_CARRIER_EN_CH0_M (BIT(28))45 #define RMT_CARRIER_EFF_EN_CH0 (BIT(27))46 #define RMT_CARRIER_EFF_EN_CH0_M (BIT(27))71 #define RMT_TX_STOP_CH0 (BIT(20))72 #define RMT_TX_STOP_CH0_M (BIT(20))77 #define RMT_IDLE_OUT_EN_CH0 (BIT(19))78 #define RMT_IDLE_OUT_EN_CH0_M (BIT(19))[all …]
33 #define UART_WAKEUP_INT_RAW (BIT(19))34 #define UART_WAKEUP_INT_RAW_M (BIT(19))39 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))40 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))45 #define UART_RS485_CLASH_INT_RAW (BIT(17))46 #define UART_RS485_CLASH_INT_RAW_M (BIT(17))51 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))52 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))57 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))58 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))[all …]
64 #define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7))65 #define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7))70 #define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6))71 #define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6))82 #define DPORT_RST_EN_DEDICATED_GPIO (BIT(7))83 #define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7))88 #define DPORT_RST_EN_ASSIST_DEBUG (BIT(6))89 #define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6))102 #define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3))103 #define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))[all …]
25 #define I2S_RX_RESET_ST (BIT(29))26 #define I2S_RX_RESET_ST_M (BIT(29))31 #define I2S_RX_BIG_ENDIAN (BIT(28))32 #define I2S_RX_BIG_ENDIAN_M (BIT(28))37 #define I2S_TX_BIG_ENDIAN (BIT(27))38 #define I2S_TX_BIG_ENDIAN_M (BIT(27))43 #define I2S_PRE_REQ_EN (BIT(26))44 #define I2S_PRE_REQ_EN_M (BIT(26))49 #define I2S_RX_DMA_EQUAL (BIT(25))50 #define I2S_RX_DMA_EQUAL_M (BIT(25))[all …]
