Searched refs:_L_ (Results 1 – 25 of 330) sorted by relevance
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385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…386 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function val…389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…[all …]
271 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…272 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function val…275 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …278 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …281 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…284 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…287 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…290 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…293 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux …296 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux …[all …]
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…386 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function val…389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …395 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…398 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…401 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…404 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…407 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux …410 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux …[all …]
271 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…272 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function val…275 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …278 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …281 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…284 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…287 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux …290 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux …293 #define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux …296 #define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux …[all …]
