Searched refs:WoReg (Results 1 – 25 of 337) sorted by relevance
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285 #define REG_GPIO_GPERS0 (*(WoReg *)0x400E1004UL) /**< \brief (GPIO) GPIO Enable Registe…286 #define REG_GPIO_GPERC0 (*(WoReg *)0x400E1008UL) /**< \brief (GPIO) GPIO Enable Registe…287 #define REG_GPIO_GPERT0 (*(WoReg *)0x400E100CUL) /**< \brief (GPIO) GPIO Enable Registe…289 #define REG_GPIO_PMR0S0 (*(WoReg *)0x400E1014UL) /**< \brief (GPIO) Peripheral Mux Regi…290 #define REG_GPIO_PMR0C0 (*(WoReg *)0x400E1018UL) /**< \brief (GPIO) Peripheral Mux Regi…291 #define REG_GPIO_PMR0T0 (*(WoReg *)0x400E101CUL) /**< \brief (GPIO) Peripheral Mux Regi…293 #define REG_GPIO_PMR1S0 (*(WoReg *)0x400E1024UL) /**< \brief (GPIO) Peripheral Mux Regi…294 #define REG_GPIO_PMR1C0 (*(WoReg *)0x400E1028UL) /**< \brief (GPIO) Peripheral Mux Regi…295 #define REG_GPIO_PMR1T0 (*(WoReg *)0x400E102CUL) /**< \brief (GPIO) Peripheral Mux Regi…297 #define REG_GPIO_PMR2S0 (*(WoReg *)0x400E1034UL) /**< \brief (GPIO) Peripheral Mux Regi…[all …]
187 #define REG_USBC_UDINTCLR (*(WoReg *)0x400A5008UL) /**< \brief (USBC) Device Global Inter…188 #define REG_USBC_UDINTSET (*(WoReg *)0x400A500CUL) /**< \brief (USBC) Device Global Inter…190 #define REG_USBC_UDINTECLR (*(WoReg *)0x400A5014UL) /**< \brief (USBC) Device Global Inter…191 #define REG_USBC_UDINTESET (*(WoReg *)0x400A5018UL) /**< \brief (USBC) Device Global Inter…210 #define REG_USBC_UESTA0CLR (*(WoReg *)0x400A5160UL) /**< \brief (USBC) Endpoint Status Cle…211 #define REG_USBC_UESTA1CLR (*(WoReg *)0x400A5164UL) /**< \brief (USBC) Endpoint Status Cle…212 #define REG_USBC_UESTA2CLR (*(WoReg *)0x400A5168UL) /**< \brief (USBC) Endpoint Status Cle…213 #define REG_USBC_UESTA3CLR (*(WoReg *)0x400A516CUL) /**< \brief (USBC) Endpoint Status Cle…214 #define REG_USBC_UESTA4CLR (*(WoReg *)0x400A5170UL) /**< \brief (USBC) Endpoint Status Cle…215 #define REG_USBC_UESTA5CLR (*(WoReg *)0x400A5174UL) /**< \brief (USBC) Endpoint Status Cle…[all …]
246 #define REG_PDCA_CR0 (*(WoReg *)0x400A2014UL) /**< \brief (PDCA) Control Register 0 …249 #define REG_PDCA_IER0 (*(WoReg *)0x400A2020UL) /**< \brief (PDCA) Interrupt Enable Re…250 #define REG_PDCA_IDR0 (*(WoReg *)0x400A2024UL) /**< \brief (PDCA) Interrupt Disable R…258 #define REG_PDCA_CR1 (*(WoReg *)0x400A2054UL) /**< \brief (PDCA) Control Register 1 …261 #define REG_PDCA_IER1 (*(WoReg *)0x400A2060UL) /**< \brief (PDCA) Interrupt Enable Re…262 #define REG_PDCA_IDR1 (*(WoReg *)0x400A2064UL) /**< \brief (PDCA) Interrupt Disable R…270 #define REG_PDCA_CR2 (*(WoReg *)0x400A2094UL) /**< \brief (PDCA) Control Register 2 …273 #define REG_PDCA_IER2 (*(WoReg *)0x400A20A0UL) /**< \brief (PDCA) Interrupt Enable Re…274 #define REG_PDCA_IDR2 (*(WoReg *)0x400A20A4UL) /**< \brief (PDCA) Interrupt Disable R…282 #define REG_PDCA_CR3 (*(WoReg *)0x400A20D4UL) /**< \brief (PDCA) Control Register 3 …[all …]
63 #define REG_AESA_IER (*(WoReg *)0x400B0010UL) /**< \brief (AESA) Interrupt Enable Re…64 #define REG_AESA_IDR (*(WoReg *)0x400B0014UL) /**< \brief (AESA) Interrupt Disable R…66 #define REG_AESA_KEY0 (*(WoReg *)0x400B0020UL) /**< \brief (AESA) Key Register 0 */67 #define REG_AESA_KEY1 (*(WoReg *)0x400B0024UL) /**< \brief (AESA) Key Register 1 */68 #define REG_AESA_KEY2 (*(WoReg *)0x400B0028UL) /**< \brief (AESA) Key Register 2 */69 #define REG_AESA_KEY3 (*(WoReg *)0x400B002CUL) /**< \brief (AESA) Key Register 3 */70 #define REG_AESA_KEY4 (*(WoReg *)0x400B0030UL) /**< \brief (AESA) Key Register 4 */71 #define REG_AESA_KEY5 (*(WoReg *)0x400B0034UL) /**< \brief (AESA) Key Register 5 */72 #define REG_AESA_KEY6 (*(WoReg *)0x400B0038UL) /**< \brief (AESA) Key Register 6 */73 #define REG_AESA_KEY7 (*(WoReg *)0x400B003CUL) /**< \brief (AESA) Key Register 7 */[all …]
153 #define REG_PWM_ENA (*(WoReg*)0x40000004U) /**< \brief (PWM) PWM Enable Register */154 #define REG_PWM_DIS (*(WoReg*)0x40000008U) /**< \brief (PWM) PWM Disable Register */156 #define REG_PWM_IER1 (*(WoReg*)0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */157 #define REG_PWM_IDR1 (*(WoReg*)0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 …163 #define REG_PWM_SCUPUPD (*(WoReg*)0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period U…164 #define REG_PWM_IER2 (*(WoReg*)0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */165 #define REG_PWM_IDR2 (*(WoReg*)0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 …170 #define REG_PWM_OSS (*(WoReg*)0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register…171 #define REG_PWM_OSC (*(WoReg*)0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Regist…172 #define REG_PWM_OSSUPD (*(WoReg*)0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update R…[all …]
90 #define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */91 #define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */93 #define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */94 #define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */96 #define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Reg…97 #define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Re…99 #define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */100 #define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */103 #define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */104 #define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */[all …]
90 #define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */91 #define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */93 #define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */94 #define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */96 #define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Reg…97 #define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Re…99 #define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */100 #define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */103 #define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */104 #define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */[all …]
90 #define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */91 #define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */93 #define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */94 #define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */96 #define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Reg…97 #define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Re…99 #define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */100 #define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */103 #define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */104 #define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */[all …]
90 #define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */91 #define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */93 #define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */94 #define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */96 #define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Reg…97 #define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Re…99 #define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */100 #define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */103 #define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */104 #define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */[all …]
96 #define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */97 #define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */99 #define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */100 #define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */102 #define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Reg…103 #define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Re…105 #define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */106 #define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */109 #define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */110 #define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */[all …]
101 #define REG_TC0_CCR0 (*(WoReg*)0x40090000U) /**< \brief (TC0) Channel Control Register (channel = …110 #define REG_TC0_IER0 (*(WoReg*)0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel =…111 #define REG_TC0_IDR0 (*(WoReg*)0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel …114 #define REG_TC0_CCR1 (*(WoReg*)0x40090040U) /**< \brief (TC0) Channel Control Register (channel = …123 #define REG_TC0_IER1 (*(WoReg*)0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel =…124 #define REG_TC0_IDR1 (*(WoReg*)0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel …127 #define REG_TC0_CCR2 (*(WoReg*)0x40090080U) /**< \brief (TC0) Channel Control Register (channel = …136 #define REG_TC0_IER2 (*(WoReg*)0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel =…137 #define REG_TC0_IDR2 (*(WoReg*)0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel …140 #define REG_TC0_BCR (*(WoReg*)0x400900C0U) /**< \brief (TC0) Block Control Register */[all …]
101 #define REG_TC1_CCR0 (*(WoReg*)0x40094000U) /**< \brief (TC1) Channel Control Register (channel = …110 #define REG_TC1_IER0 (*(WoReg*)0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel =…111 #define REG_TC1_IDR0 (*(WoReg*)0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel …114 #define REG_TC1_CCR1 (*(WoReg*)0x40094040U) /**< \brief (TC1) Channel Control Register (channel = …123 #define REG_TC1_IER1 (*(WoReg*)0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel =…124 #define REG_TC1_IDR1 (*(WoReg*)0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel …127 #define REG_TC1_CCR2 (*(WoReg*)0x40094080U) /**< \brief (TC1) Channel Control Register (channel = …136 #define REG_TC1_IER2 (*(WoReg*)0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel =…137 #define REG_TC1_IDR2 (*(WoReg*)0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel …140 #define REG_TC1_BCR (*(WoReg*)0x400940C0U) /**< \brief (TC1) Block Control Register */[all …]
83 #define REG_TC2_CCR0 (*(WoReg*)0x40098000U) /**< \brief (TC2) Channel Control Register (channel = …92 #define REG_TC2_IER0 (*(WoReg*)0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel =…93 #define REG_TC2_IDR0 (*(WoReg*)0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel …96 #define REG_TC2_CCR1 (*(WoReg*)0x40098040U) /**< \brief (TC2) Channel Control Register (channel = …105 #define REG_TC2_IER1 (*(WoReg*)0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel =…106 #define REG_TC2_IDR1 (*(WoReg*)0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel …109 #define REG_TC2_CCR2 (*(WoReg*)0x40098080U) /**< \brief (TC2) Channel Control Register (channel = …118 #define REG_TC2_IER2 (*(WoReg*)0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel =…119 #define REG_TC2_IDR2 (*(WoReg*)0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel …122 #define REG_TC2_BCR (*(WoReg*)0x400980C0U) /**< \brief (TC2) Block Control Register */[all …]
61 #define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */62 #define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */64 #define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 …65 #define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0…73 #define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */74 #define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */79 #define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */82 #define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 …83 #define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1…
55 #define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */57 #define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */58 #define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */64 #define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Va…65 #define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Va…66 #define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Va…67 #define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Va…68 #define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Va…69 #define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Va…70 #define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Va…[all …]
73 #define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */74 #define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */75 #define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */76 #define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */77 #define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */78 #define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */79 #define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */80 #define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */82 #define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vecto…83 #define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vecto…[all …]
73 #define REG_AES_KEYWORD0 (*(WoReg *)0x4200340CUL) /**< \brief (AES) Keyword 0 */74 #define REG_AES_KEYWORD1 (*(WoReg *)0x42003410UL) /**< \brief (AES) Keyword 1 */75 #define REG_AES_KEYWORD2 (*(WoReg *)0x42003414UL) /**< \brief (AES) Keyword 2 */76 #define REG_AES_KEYWORD3 (*(WoReg *)0x42003418UL) /**< \brief (AES) Keyword 3 */77 #define REG_AES_KEYWORD4 (*(WoReg *)0x4200341CUL) /**< \brief (AES) Keyword 4 */78 #define REG_AES_KEYWORD5 (*(WoReg *)0x42003420UL) /**< \brief (AES) Keyword 5 */79 #define REG_AES_KEYWORD6 (*(WoReg *)0x42003424UL) /**< \brief (AES) Keyword 6 */80 #define REG_AES_KEYWORD7 (*(WoReg *)0x42003428UL) /**< \brief (AES) Keyword 7 */82 #define REG_AES_INTVECTV0 (*(WoReg *)0x4200343CUL) /**< \brief (AES) Initialisation Vecto…83 #define REG_AES_INTVECTV1 (*(WoReg *)0x42003440UL) /**< \brief (AES) Initialisation Vecto…[all …]
