1 /** 2 * \file 3 * 4 * \brief Component description for WDT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_WDT_COMPONENT_ 30 #define _SAM4L_WDT_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR WDT */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_WDT Watchdog Timer */ 36 /*@{*/ 37 38 #define WDT_I7528 39 #define REV_WDT 0x501 40 41 /* -------- WDT_CTRL : (WDT Offset: 0x000) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 WDT Enable */ 46 uint32_t DAR:1; /*!< bit: 1 WDT Disable After Reset */ 47 uint32_t MODE:1; /*!< bit: 2 WDT Mode */ 48 uint32_t SFV:1; /*!< bit: 3 WDT Store Final Value */ 49 uint32_t IM:1; /*!< bit: 4 WDT Interruput Mode */ 50 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 51 uint32_t FCD:1; /*!< bit: 7 WDT Fuse Calibration Done */ 52 uint32_t PSEL:5; /*!< bit: 8..12 Timeout Prescale Select */ 53 uint32_t :1; /*!< bit: 13 Reserved */ 54 uint32_t CSSEL1:1; /*!< bit: 14 Clock Source Selection1 */ 55 uint32_t :1; /*!< bit: 15 Reserved */ 56 uint32_t CEN:1; /*!< bit: 16 Clock Enable */ 57 uint32_t CSSEL:1; /*!< bit: 17 Clock Source Selection0 */ 58 uint32_t TBAN:5; /*!< bit: 18..22 TBAN Prescale Select */ 59 uint32_t :1; /*!< bit: 23 Reserved */ 60 uint32_t KEY:8; /*!< bit: 24..31 Key */ 61 } bit; /*!< Structure used for bit access */ 62 uint32_t reg; /*!< Type used for register access */ 63 } WDT_CTRL_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define WDT_CTRL_OFFSET 0x000 /**< \brief (WDT_CTRL offset) Control Register */ 67 #define WDT_CTRL_RESETVALUE _U_(0x00010080); /**< \brief (WDT_CTRL reset_value) Control Register */ 68 69 #define WDT_CTRL_EN_Pos 0 /**< \brief (WDT_CTRL) WDT Enable */ 70 #define WDT_CTRL_EN (_U_(0x1) << WDT_CTRL_EN_Pos) 71 #define WDT_CTRL_EN_0_Val _U_(0x0) /**< \brief (WDT_CTRL) WDT is disabled. */ 72 #define WDT_CTRL_EN_1_Val _U_(0x1) /**< \brief (WDT_CTRL) WDT is enabled */ 73 #define WDT_CTRL_EN_0 (WDT_CTRL_EN_0_Val << WDT_CTRL_EN_Pos) 74 #define WDT_CTRL_EN_1 (WDT_CTRL_EN_1_Val << WDT_CTRL_EN_Pos) 75 #define WDT_CTRL_DAR_Pos 1 /**< \brief (WDT_CTRL) WDT Disable After Reset */ 76 #define WDT_CTRL_DAR (_U_(0x1) << WDT_CTRL_DAR_Pos) 77 #define WDT_CTRL_MODE_Pos 2 /**< \brief (WDT_CTRL) WDT Mode */ 78 #define WDT_CTRL_MODE (_U_(0x1) << WDT_CTRL_MODE_Pos) 79 #define WDT_CTRL_SFV_Pos 3 /**< \brief (WDT_CTRL) WDT Store Final Value */ 80 #define WDT_CTRL_SFV (_U_(0x1) << WDT_CTRL_SFV_Pos) 81 #define WDT_CTRL_IM_Pos 4 /**< \brief (WDT_CTRL) WDT Interruput Mode */ 82 #define WDT_CTRL_IM (_U_(0x1) << WDT_CTRL_IM_Pos) 83 #define WDT_CTRL_FCD_Pos 7 /**< \brief (WDT_CTRL) WDT Fuse Calibration Done */ 84 #define WDT_CTRL_FCD (_U_(0x1) << WDT_CTRL_FCD_Pos) 85 #define WDT_CTRL_PSEL_Pos 8 /**< \brief (WDT_CTRL) Timeout Prescale Select */ 86 #define WDT_CTRL_PSEL_Msk (_U_(0x1F) << WDT_CTRL_PSEL_Pos) 87 #define WDT_CTRL_PSEL(value) (WDT_CTRL_PSEL_Msk & ((value) << WDT_CTRL_PSEL_Pos)) 88 #define WDT_CTRL_CSSEL1_Pos 14 /**< \brief (WDT_CTRL) Clock Source Selection1 */ 89 #define WDT_CTRL_CSSEL1 (_U_(0x1) << WDT_CTRL_CSSEL1_Pos) 90 #define WDT_CTRL_CEN_Pos 16 /**< \brief (WDT_CTRL) Clock Enable */ 91 #define WDT_CTRL_CEN (_U_(0x1) << WDT_CTRL_CEN_Pos) 92 #define WDT_CTRL_CSSEL_Pos 17 /**< \brief (WDT_CTRL) Clock Source Selection0 */ 93 #define WDT_CTRL_CSSEL (_U_(0x1) << WDT_CTRL_CSSEL_Pos) 94 #define WDT_CTRL_TBAN_Pos 18 /**< \brief (WDT_CTRL) TBAN Prescale Select */ 95 #define WDT_CTRL_TBAN_Msk (_U_(0x1F) << WDT_CTRL_TBAN_Pos) 96 #define WDT_CTRL_TBAN(value) (WDT_CTRL_TBAN_Msk & ((value) << WDT_CTRL_TBAN_Pos)) 97 #define WDT_CTRL_KEY_Pos 24 /**< \brief (WDT_CTRL) Key */ 98 #define WDT_CTRL_KEY_Msk (_U_(0xFF) << WDT_CTRL_KEY_Pos) 99 #define WDT_CTRL_KEY(value) (WDT_CTRL_KEY_Msk & ((value) << WDT_CTRL_KEY_Pos)) 100 #define WDT_CTRL_MASK _U_(0xFF7F5F9F) /**< \brief (WDT_CTRL) MASK Register */ 101 102 /* -------- WDT_CLR : (WDT Offset: 0x004) ( /W 32) Clear Register -------- */ 103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 104 typedef union { 105 struct { 106 uint32_t WDTCLR:1; /*!< bit: 0 Clear WDT counter */ 107 uint32_t :23; /*!< bit: 1..23 Reserved */ 108 uint32_t KEY:8; /*!< bit: 24..31 Key */ 109 } bit; /*!< Structure used for bit access */ 110 uint32_t reg; /*!< Type used for register access */ 111 } WDT_CLR_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 114 #define WDT_CLR_OFFSET 0x004 /**< \brief (WDT_CLR offset) Clear Register */ 115 #define WDT_CLR_RESETVALUE _U_(0x00000000); /**< \brief (WDT_CLR reset_value) Clear Register */ 116 117 #define WDT_CLR_WDTCLR_Pos 0 /**< \brief (WDT_CLR) Clear WDT counter */ 118 #define WDT_CLR_WDTCLR (_U_(0x1) << WDT_CLR_WDTCLR_Pos) 119 #define WDT_CLR_KEY_Pos 24 /**< \brief (WDT_CLR) Key */ 120 #define WDT_CLR_KEY_Msk (_U_(0xFF) << WDT_CLR_KEY_Pos) 121 #define WDT_CLR_KEY(value) (WDT_CLR_KEY_Msk & ((value) << WDT_CLR_KEY_Pos)) 122 #define WDT_CLR_MASK _U_(0xFF000001) /**< \brief (WDT_CLR) MASK Register */ 123 124 /* -------- WDT_SR : (WDT Offset: 0x008) (R/ 32) Status Register -------- */ 125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 126 typedef union { 127 struct { 128 uint32_t WINDOW:1; /*!< bit: 0 WDT in window */ 129 uint32_t CLEARED:1; /*!< bit: 1 WDT cleared */ 130 uint32_t :30; /*!< bit: 2..31 Reserved */ 131 } bit; /*!< Structure used for bit access */ 132 uint32_t reg; /*!< Type used for register access */ 133 } WDT_SR_Type; 134 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 135 136 #define WDT_SR_OFFSET 0x008 /**< \brief (WDT_SR offset) Status Register */ 137 #define WDT_SR_RESETVALUE _U_(0x00000003); /**< \brief (WDT_SR reset_value) Status Register */ 138 139 #define WDT_SR_WINDOW_Pos 0 /**< \brief (WDT_SR) WDT in window */ 140 #define WDT_SR_WINDOW (_U_(0x1) << WDT_SR_WINDOW_Pos) 141 #define WDT_SR_CLEARED_Pos 1 /**< \brief (WDT_SR) WDT cleared */ 142 #define WDT_SR_CLEARED (_U_(0x1) << WDT_SR_CLEARED_Pos) 143 #define WDT_SR_MASK _U_(0x00000003) /**< \brief (WDT_SR) MASK Register */ 144 145 /* -------- WDT_IER : (WDT Offset: 0x00C) ( /W 32) Interrupt Enable Register -------- */ 146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 147 typedef union { 148 struct { 149 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 150 uint32_t WINT:1; /*!< bit: 2 Watchdog Interrupt */ 151 uint32_t :29; /*!< bit: 3..31 Reserved */ 152 } bit; /*!< Structure used for bit access */ 153 uint32_t reg; /*!< Type used for register access */ 154 } WDT_IER_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 #define WDT_IER_OFFSET 0x00C /**< \brief (WDT_IER offset) Interrupt Enable Register */ 158 #define WDT_IER_RESETVALUE _U_(0x00000000); /**< \brief (WDT_IER reset_value) Interrupt Enable Register */ 159 160 #define WDT_IER_WINT_Pos 2 /**< \brief (WDT_IER) Watchdog Interrupt */ 161 #define WDT_IER_WINT (_U_(0x1) << WDT_IER_WINT_Pos) 162 #define WDT_IER_MASK _U_(0x00000004) /**< \brief (WDT_IER) MASK Register */ 163 164 /* -------- WDT_IDR : (WDT Offset: 0x010) ( /W 32) Interrupt Disable Register -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 struct { 168 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 169 uint32_t WINT:1; /*!< bit: 2 Watchdog Interrupt */ 170 uint32_t :29; /*!< bit: 3..31 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } WDT_IDR_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define WDT_IDR_OFFSET 0x010 /**< \brief (WDT_IDR offset) Interrupt Disable Register */ 177 #define WDT_IDR_RESETVALUE _U_(0x00000000); /**< \brief (WDT_IDR reset_value) Interrupt Disable Register */ 178 179 #define WDT_IDR_WINT_Pos 2 /**< \brief (WDT_IDR) Watchdog Interrupt */ 180 #define WDT_IDR_WINT (_U_(0x1) << WDT_IDR_WINT_Pos) 181 #define WDT_IDR_MASK _U_(0x00000004) /**< \brief (WDT_IDR) MASK Register */ 182 183 /* -------- WDT_IMR : (WDT Offset: 0x014) (R/ 32) Interrupt Mask Register -------- */ 184 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 185 typedef union { 186 struct { 187 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 188 uint32_t WINT:1; /*!< bit: 2 Watchdog Interrupt */ 189 uint32_t :29; /*!< bit: 3..31 Reserved */ 190 } bit; /*!< Structure used for bit access */ 191 uint32_t reg; /*!< Type used for register access */ 192 } WDT_IMR_Type; 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 194 195 #define WDT_IMR_OFFSET 0x014 /**< \brief (WDT_IMR offset) Interrupt Mask Register */ 196 #define WDT_IMR_RESETVALUE _U_(0x00000000); /**< \brief (WDT_IMR reset_value) Interrupt Mask Register */ 197 198 #define WDT_IMR_WINT_Pos 2 /**< \brief (WDT_IMR) Watchdog Interrupt */ 199 #define WDT_IMR_WINT (_U_(0x1) << WDT_IMR_WINT_Pos) 200 #define WDT_IMR_MASK _U_(0x00000004) /**< \brief (WDT_IMR) MASK Register */ 201 202 /* -------- WDT_ISR : (WDT Offset: 0x018) (R/ 32) Interrupt Status Register -------- */ 203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 204 typedef union { 205 struct { 206 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 207 uint32_t WINT:1; /*!< bit: 2 Watchdog Interrupt */ 208 uint32_t :29; /*!< bit: 3..31 Reserved */ 209 } bit; /*!< Structure used for bit access */ 210 uint32_t reg; /*!< Type used for register access */ 211 } WDT_ISR_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 #define WDT_ISR_OFFSET 0x018 /**< \brief (WDT_ISR offset) Interrupt Status Register */ 215 #define WDT_ISR_RESETVALUE _U_(0x00000000); /**< \brief (WDT_ISR reset_value) Interrupt Status Register */ 216 217 #define WDT_ISR_WINT_Pos 2 /**< \brief (WDT_ISR) Watchdog Interrupt */ 218 #define WDT_ISR_WINT (_U_(0x1) << WDT_ISR_WINT_Pos) 219 #define WDT_ISR_MASK _U_(0x00000004) /**< \brief (WDT_ISR) MASK Register */ 220 221 /* -------- WDT_ICR : (WDT Offset: 0x01C) ( /W 32) Interrupt Clear Register -------- */ 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 223 typedef union { 224 struct { 225 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 226 uint32_t WINT:1; /*!< bit: 2 Watchdog Interrupt */ 227 uint32_t :29; /*!< bit: 3..31 Reserved */ 228 } bit; /*!< Structure used for bit access */ 229 uint32_t reg; /*!< Type used for register access */ 230 } WDT_ICR_Type; 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 232 233 #define WDT_ICR_OFFSET 0x01C /**< \brief (WDT_ICR offset) Interrupt Clear Register */ 234 #define WDT_ICR_RESETVALUE _U_(0x00000000); /**< \brief (WDT_ICR reset_value) Interrupt Clear Register */ 235 236 #define WDT_ICR_WINT_Pos 2 /**< \brief (WDT_ICR) Watchdog Interrupt */ 237 #define WDT_ICR_WINT (_U_(0x1) << WDT_ICR_WINT_Pos) 238 #define WDT_ICR_MASK _U_(0x00000004) /**< \brief (WDT_ICR) MASK Register */ 239 240 /* -------- WDT_VERSION : (WDT Offset: 0x3FC) (R/ 32) Version Register -------- */ 241 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 242 typedef union { 243 struct { 244 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 245 uint32_t :4; /*!< bit: 12..15 Reserved */ 246 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 247 uint32_t :12; /*!< bit: 20..31 Reserved */ 248 } bit; /*!< Structure used for bit access */ 249 uint32_t reg; /*!< Type used for register access */ 250 } WDT_VERSION_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define WDT_VERSION_OFFSET 0x3FC /**< \brief (WDT_VERSION offset) Version Register */ 254 #define WDT_VERSION_RESETVALUE _U_(0x00000501); /**< \brief (WDT_VERSION reset_value) Version Register */ 255 256 #define WDT_VERSION_VERSION_Pos 0 /**< \brief (WDT_VERSION) Version number */ 257 #define WDT_VERSION_VERSION_Msk (_U_(0xFFF) << WDT_VERSION_VERSION_Pos) 258 #define WDT_VERSION_VERSION(value) (WDT_VERSION_VERSION_Msk & ((value) << WDT_VERSION_VERSION_Pos)) 259 #define WDT_VERSION_VARIANT_Pos 16 /**< \brief (WDT_VERSION) Variant number */ 260 #define WDT_VERSION_VARIANT_Msk (_U_(0xF) << WDT_VERSION_VARIANT_Pos) 261 #define WDT_VERSION_VARIANT(value) (WDT_VERSION_VARIANT_Msk & ((value) << WDT_VERSION_VARIANT_Pos)) 262 #define WDT_VERSION_MASK _U_(0x000F0FFF) /**< \brief (WDT_VERSION) MASK Register */ 263 264 /** \brief WDT hardware registers */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef struct { 267 __IO uint32_t CTRL; /**< \brief Offset: 0x000 (R/W 32) Control Register */ 268 __O uint32_t CLR; /**< \brief Offset: 0x004 ( /W 32) Clear Register */ 269 __I uint32_t SR; /**< \brief Offset: 0x008 (R/ 32) Status Register */ 270 __O uint32_t IER; /**< \brief Offset: 0x00C ( /W 32) Interrupt Enable Register */ 271 __O uint32_t IDR; /**< \brief Offset: 0x010 ( /W 32) Interrupt Disable Register */ 272 __I uint32_t IMR; /**< \brief Offset: 0x014 (R/ 32) Interrupt Mask Register */ 273 __I uint32_t ISR; /**< \brief Offset: 0x018 (R/ 32) Interrupt Status Register */ 274 __O uint32_t ICR; /**< \brief Offset: 0x01C ( /W 32) Interrupt Clear Register */ 275 RoReg8 Reserved1[0x3DC]; 276 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) Version Register */ 277 } Wdt; 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 279 280 /*@}*/ 281 282 #endif /* _SAM4L_WDT_COMPONENT_ */ 283
