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Searched refs:TCC_INSTS (Results 1 – 25 of 94) sorted by relevance

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/hal_atmel-latest/asf/sam0/include/samd21/
Dsamd21e15a.h502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamd21e16a.h502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamd21e17a.h502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamd21e18a.h502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
/hal_atmel-latest/asf/sam0/include/samc20/
Dsamc20e15a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20e16a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20e17a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20e18a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j18a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j18au.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20g15a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20g16a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20g17a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20g18a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j15a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j16a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j17a.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamc20j17au.h538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
/hal_atmel-latest/asf/sam0/include/samr21/
Dsamr21g16a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21e16a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21e17a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21e18a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21e19a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21g17a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro
Dsamr21g18a.h524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ macro

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