Home
last modified time | relevance | path

Searched refs:TCC4 (Results 1 – 21 of 21) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd51/
Dsamd51j18a.h784 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
942 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51j19a.h784 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
942 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51j20a.h784 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
942 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51n20a.h821 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
984 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51p19a.h821 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
984 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51p20a.h821 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
984 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51n19a.h821 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
984 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same51/
Dsame51j18a.h795 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
958 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51j19a.h795 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
958 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51j20a.h795 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
958 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51n19a.h827 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
994 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51n20a.h827 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
994 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same53/
Dsame53j18a.h790 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
952 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53j19a.h790 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
952 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53j20a.h790 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
952 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53n19a.h827 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
994 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53n20a.h827 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
994 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same54/
Dsame54n19a.h838 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
1010 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54n20a.h838 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
1010 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54p19a.h838 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
1010 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54p20a.h838 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ macro
1010 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */