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Searched refs:TCC3 (Results 1 – 21 of 21) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd51/
Dsamd51j18a.h783 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
941 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51j19a.h783 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
941 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51j20a.h783 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
941 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51n20a.h820 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
983 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51p19a.h820 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
983 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51p20a.h820 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
983 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsamd51n19a.h820 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
983 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
986 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same51/
Dsame51j18a.h794 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
957 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51j19a.h794 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
957 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51j20a.h794 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
957 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
960 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51n19a.h826 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
993 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame51n20a.h826 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
993 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same53/
Dsame53j18a.h789 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
951 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53j19a.h789 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
951 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53j20a.h789 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
951 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
954 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53n19a.h826 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
993 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame53n20a.h826 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
993 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
996 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/same54/
Dsame54n19a.h837 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
1009 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54n20a.h837 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
1009 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54p19a.h837 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
1009 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
Dsame54p20a.h837 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ macro
1009 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ macro
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */