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/hal_atmel-latest/asf/sam0/include/samd21/
Dsamd21e15a.h395 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
499 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e16a.h395 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
499 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e17a.h395 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
499 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e18a.h395 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
499 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21j15a.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21j16a.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21j17a.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21j18a.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g15a.h405 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
511 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
514 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g16a.h405 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
511 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
514 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g17a.h405 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
511 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
514 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g17au.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g18a.h405 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
511 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
514 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21g18au.h415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/samr21/
Dsamr21e16a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21g16a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e17a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e18a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e19a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21g17a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21g18a.h413 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ macro
521 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/samc20/
Dsamc20e16a.h413 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ macro
535 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20e17a.h413 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ macro
535 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g16a.h413 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ macro
535 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g17a.h413 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ macro
535 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */

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