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/hal_atmel-latest/asf/sam0/include/samd21/
Dsamd21e15a.h394 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
498 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e16a.h394 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
498 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e17a.h394 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
498 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamd21e18a.h394 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
498 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
502 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/samc20/
Dsamc20e15a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20e16a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20e17a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20e18a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j18a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j18au.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g15a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g16a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g17a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20g18a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j15a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j16a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j17a.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamc20j17au.h412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ macro
534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ macro
538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
/hal_atmel-latest/asf/sam0/include/samr21/
Dsamr21g16a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e16a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e17a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e18a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21e19a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21g17a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
Dsamr21g18a.h412 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ macro
520 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ macro
524 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */

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