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Searched refs:SDHC_CCR_CLKGSEL_DIV_Val (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam0/include/same53/component/
Dsdhc.h670 #define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */ macro
672 #define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
/hal_atmel-latest/asf/sam0/include/same51/component/
Dsdhc.h670 #define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */ macro
672 #define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
/hal_atmel-latest/asf/sam0/include/samd51/component/
Dsdhc.h670 #define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */ macro
672 #define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
/hal_atmel-latest/asf/sam0/include/same54/component/
Dsdhc.h670 #define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */ macro
672 #define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)