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Searched refs:SDHC0 (Results 1 – 23 of 23) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd51/
Dsamd51g19a.h736 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
874 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
876 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsamd51g18a.h736 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
874 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
876 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsamd51j18a.h766 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
912 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
914 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsamd51j19a.h766 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
912 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
914 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsamd51j20a.h766 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
912 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
914 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsamd51n20a.h798 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
949 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
952 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsamd51p19a.h798 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
949 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
952 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsamd51p20a.h798 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
949 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
952 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsamd51n19a.h798 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
949 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
952 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
/hal_atmel-latest/asf/sam0/include/same51/
Dsame51j18a.h777 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
928 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
930 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame51j19a.h777 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
928 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
930 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame51j20a.h777 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
928 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
930 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame51n19a.h805 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
960 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
962 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame51n20a.h805 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
960 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
962 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
/hal_atmel-latest/asf/sam0/include/same53/
Dsame53j18a.h772 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
922 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
924 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame53j19a.h772 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
922 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
924 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame53j20a.h772 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
922 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
924 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
Dsame53n19a.h804 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
959 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
962 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsame53n20a.h804 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
959 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
962 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
/hal_atmel-latest/asf/sam0/include/same54/
Dsame54n19a.h815 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
975 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
978 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsame54n20a.h815 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
975 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
978 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsame54p19a.h815 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
975 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
978 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
Dsame54p20a.h815 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ macro
975 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ macro
978 #define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */