1 /** 2 * \file 3 * 4 * \brief Component description for SCIF 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_SCIF_COMPONENT_ 30 #define _SAM4L_SCIF_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR SCIF */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_SCIF System Control Interface */ 36 /*@{*/ 37 38 #define SCIF_I7149 39 #define REV_SCIF 0x130 40 41 /* -------- SCIF_IER : (SCIF Offset: 0x000) ( /W 32) Interrupt Enable Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 46 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Lock Coarse */ 47 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Lock Fine */ 48 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Ready */ 49 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 50 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Out Of Bounds */ 51 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Lock */ 52 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 Lock Lost */ 53 uint32_t :5; /*!< bit: 8..12 Reserved */ 54 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Lock */ 55 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST Lock Lost */ 56 uint32_t :16; /*!< bit: 15..30 Reserved */ 57 uint32_t AE:1; /*!< bit: 31 Access Error */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } SCIF_IER_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define SCIF_IER_OFFSET 0x000 /**< \brief (SCIF_IER offset) Interrupt Enable Register */ 64 #define SCIF_IER_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_IER reset_value) Interrupt Enable Register */ 65 66 #define SCIF_IER_OSC0RDY_Pos 0 /**< \brief (SCIF_IER) OSC0 Ready */ 67 #define SCIF_IER_OSC0RDY (_U_(0x1) << SCIF_IER_OSC0RDY_Pos) 68 #define SCIF_IER_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_IER) DFLL0 Lock Coarse */ 69 #define SCIF_IER_DFLL0LOCKC (_U_(0x1) << SCIF_IER_DFLL0LOCKC_Pos) 70 #define SCIF_IER_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_IER) DFLL0 Lock Fine */ 71 #define SCIF_IER_DFLL0LOCKF (_U_(0x1) << SCIF_IER_DFLL0LOCKF_Pos) 72 #define SCIF_IER_DFLL0RDY_Pos 3 /**< \brief (SCIF_IER) DFLL0 Ready */ 73 #define SCIF_IER_DFLL0RDY (_U_(0x1) << SCIF_IER_DFLL0RDY_Pos) 74 #define SCIF_IER_DFLL0RCS_Pos 4 /**< \brief (SCIF_IER) DFLL0 Reference Clock Stopped */ 75 #define SCIF_IER_DFLL0RCS (_U_(0x1) << SCIF_IER_DFLL0RCS_Pos) 76 #define SCIF_IER_DFLL0OOB_Pos 5 /**< \brief (SCIF_IER) DFLL0 Out Of Bounds */ 77 #define SCIF_IER_DFLL0OOB (_U_(0x1) << SCIF_IER_DFLL0OOB_Pos) 78 #define SCIF_IER_PLL0LOCK_Pos 6 /**< \brief (SCIF_IER) PLL0 Lock */ 79 #define SCIF_IER_PLL0LOCK (_U_(0x1) << SCIF_IER_PLL0LOCK_Pos) 80 #define SCIF_IER_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_IER) PLL0 Lock Lost */ 81 #define SCIF_IER_PLL0LOCKLOST (_U_(0x1) << SCIF_IER_PLL0LOCKLOST_Pos) 82 #define SCIF_IER_RCFASTLOCK_Pos 13 /**< \brief (SCIF_IER) RCFAST Lock */ 83 #define SCIF_IER_RCFASTLOCK (_U_(0x1) << SCIF_IER_RCFASTLOCK_Pos) 84 #define SCIF_IER_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_IER) RCFAST Lock Lost */ 85 #define SCIF_IER_RCFASTLOCKLOST (_U_(0x1) << SCIF_IER_RCFASTLOCKLOST_Pos) 86 #define SCIF_IER_AE_Pos 31 /**< \brief (SCIF_IER) Access Error */ 87 #define SCIF_IER_AE (_U_(0x1) << SCIF_IER_AE_Pos) 88 #define SCIF_IER_MASK _U_(0x800060FF) /**< \brief (SCIF_IER) MASK Register */ 89 90 /* -------- SCIF_IDR : (SCIF Offset: 0x004) ( /W 32) Interrupt Disable Register -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { 93 struct { 94 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 95 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Lock Coarse */ 96 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Lock Fine */ 97 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Ready */ 98 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 99 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Out Of Bounds */ 100 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Lock */ 101 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 Lock Lost */ 102 uint32_t :5; /*!< bit: 8..12 Reserved */ 103 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Lock */ 104 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST Lock Lost */ 105 uint32_t :16; /*!< bit: 15..30 Reserved */ 106 uint32_t AE:1; /*!< bit: 31 Access Error */ 107 } bit; /*!< Structure used for bit access */ 108 uint32_t reg; /*!< Type used for register access */ 109 } SCIF_IDR_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define SCIF_IDR_OFFSET 0x004 /**< \brief (SCIF_IDR offset) Interrupt Disable Register */ 113 #define SCIF_IDR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_IDR reset_value) Interrupt Disable Register */ 114 115 #define SCIF_IDR_OSC0RDY_Pos 0 /**< \brief (SCIF_IDR) OSC0 Ready */ 116 #define SCIF_IDR_OSC0RDY (_U_(0x1) << SCIF_IDR_OSC0RDY_Pos) 117 #define SCIF_IDR_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_IDR) DFLL0 Lock Coarse */ 118 #define SCIF_IDR_DFLL0LOCKC (_U_(0x1) << SCIF_IDR_DFLL0LOCKC_Pos) 119 #define SCIF_IDR_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_IDR) DFLL0 Lock Fine */ 120 #define SCIF_IDR_DFLL0LOCKF (_U_(0x1) << SCIF_IDR_DFLL0LOCKF_Pos) 121 #define SCIF_IDR_DFLL0RDY_Pos 3 /**< \brief (SCIF_IDR) DFLL0 Ready */ 122 #define SCIF_IDR_DFLL0RDY (_U_(0x1) << SCIF_IDR_DFLL0RDY_Pos) 123 #define SCIF_IDR_DFLL0RCS_Pos 4 /**< \brief (SCIF_IDR) DFLL0 Reference Clock Stopped */ 124 #define SCIF_IDR_DFLL0RCS (_U_(0x1) << SCIF_IDR_DFLL0RCS_Pos) 125 #define SCIF_IDR_DFLL0OOB_Pos 5 /**< \brief (SCIF_IDR) DFLL0 Out Of Bounds */ 126 #define SCIF_IDR_DFLL0OOB (_U_(0x1) << SCIF_IDR_DFLL0OOB_Pos) 127 #define SCIF_IDR_PLL0LOCK_Pos 6 /**< \brief (SCIF_IDR) PLL0 Lock */ 128 #define SCIF_IDR_PLL0LOCK (_U_(0x1) << SCIF_IDR_PLL0LOCK_Pos) 129 #define SCIF_IDR_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_IDR) PLL0 Lock Lost */ 130 #define SCIF_IDR_PLL0LOCKLOST (_U_(0x1) << SCIF_IDR_PLL0LOCKLOST_Pos) 131 #define SCIF_IDR_RCFASTLOCK_Pos 13 /**< \brief (SCIF_IDR) RCFAST Lock */ 132 #define SCIF_IDR_RCFASTLOCK (_U_(0x1) << SCIF_IDR_RCFASTLOCK_Pos) 133 #define SCIF_IDR_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_IDR) RCFAST Lock Lost */ 134 #define SCIF_IDR_RCFASTLOCKLOST (_U_(0x1) << SCIF_IDR_RCFASTLOCKLOST_Pos) 135 #define SCIF_IDR_AE_Pos 31 /**< \brief (SCIF_IDR) Access Error */ 136 #define SCIF_IDR_AE (_U_(0x1) << SCIF_IDR_AE_Pos) 137 #define SCIF_IDR_MASK _U_(0x800060FF) /**< \brief (SCIF_IDR) MASK Register */ 138 139 /* -------- SCIF_IMR : (SCIF Offset: 0x008) (R/ 32) Interrupt Mask Register -------- */ 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 141 typedef union { 142 struct { 143 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 144 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Lock Coarse */ 145 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Lock Fine */ 146 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Ready */ 147 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 148 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Out Of Bounds */ 149 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Lock */ 150 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 Lock Lost */ 151 uint32_t :5; /*!< bit: 8..12 Reserved */ 152 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Lock */ 153 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST Lock Lost */ 154 uint32_t :16; /*!< bit: 15..30 Reserved */ 155 uint32_t AE:1; /*!< bit: 31 Access Error */ 156 } bit; /*!< Structure used for bit access */ 157 uint32_t reg; /*!< Type used for register access */ 158 } SCIF_IMR_Type; 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 160 161 #define SCIF_IMR_OFFSET 0x008 /**< \brief (SCIF_IMR offset) Interrupt Mask Register */ 162 #define SCIF_IMR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_IMR reset_value) Interrupt Mask Register */ 163 164 #define SCIF_IMR_OSC0RDY_Pos 0 /**< \brief (SCIF_IMR) OSC0 Ready */ 165 #define SCIF_IMR_OSC0RDY (_U_(0x1) << SCIF_IMR_OSC0RDY_Pos) 166 #define SCIF_IMR_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_IMR) DFLL0 Lock Coarse */ 167 #define SCIF_IMR_DFLL0LOCKC (_U_(0x1) << SCIF_IMR_DFLL0LOCKC_Pos) 168 #define SCIF_IMR_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_IMR) DFLL0 Lock Fine */ 169 #define SCIF_IMR_DFLL0LOCKF (_U_(0x1) << SCIF_IMR_DFLL0LOCKF_Pos) 170 #define SCIF_IMR_DFLL0RDY_Pos 3 /**< \brief (SCIF_IMR) DFLL0 Ready */ 171 #define SCIF_IMR_DFLL0RDY (_U_(0x1) << SCIF_IMR_DFLL0RDY_Pos) 172 #define SCIF_IMR_DFLL0RCS_Pos 4 /**< \brief (SCIF_IMR) DFLL0 Reference Clock Stopped */ 173 #define SCIF_IMR_DFLL0RCS (_U_(0x1) << SCIF_IMR_DFLL0RCS_Pos) 174 #define SCIF_IMR_DFLL0OOB_Pos 5 /**< \brief (SCIF_IMR) DFLL0 Out Of Bounds */ 175 #define SCIF_IMR_DFLL0OOB (_U_(0x1) << SCIF_IMR_DFLL0OOB_Pos) 176 #define SCIF_IMR_PLL0LOCK_Pos 6 /**< \brief (SCIF_IMR) PLL0 Lock */ 177 #define SCIF_IMR_PLL0LOCK (_U_(0x1) << SCIF_IMR_PLL0LOCK_Pos) 178 #define SCIF_IMR_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_IMR) PLL0 Lock Lost */ 179 #define SCIF_IMR_PLL0LOCKLOST (_U_(0x1) << SCIF_IMR_PLL0LOCKLOST_Pos) 180 #define SCIF_IMR_RCFASTLOCK_Pos 13 /**< \brief (SCIF_IMR) RCFAST Lock */ 181 #define SCIF_IMR_RCFASTLOCK (_U_(0x1) << SCIF_IMR_RCFASTLOCK_Pos) 182 #define SCIF_IMR_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_IMR) RCFAST Lock Lost */ 183 #define SCIF_IMR_RCFASTLOCKLOST (_U_(0x1) << SCIF_IMR_RCFASTLOCKLOST_Pos) 184 #define SCIF_IMR_AE_Pos 31 /**< \brief (SCIF_IMR) Access Error */ 185 #define SCIF_IMR_AE (_U_(0x1) << SCIF_IMR_AE_Pos) 186 #define SCIF_IMR_MASK _U_(0x800060FF) /**< \brief (SCIF_IMR) MASK Register */ 187 188 /* -------- SCIF_ISR : (SCIF Offset: 0x00C) (R/ 32) Interrupt Status Register -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 193 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Lock Coarse */ 194 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Lock Fine */ 195 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Ready */ 196 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 197 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Out Of Bounds */ 198 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Lock */ 199 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 Lock Lost */ 200 uint32_t :5; /*!< bit: 8..12 Reserved */ 201 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Lock */ 202 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST Lock Lost */ 203 uint32_t :16; /*!< bit: 15..30 Reserved */ 204 uint32_t AE:1; /*!< bit: 31 Access Error */ 205 } bit; /*!< Structure used for bit access */ 206 uint32_t reg; /*!< Type used for register access */ 207 } SCIF_ISR_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #define SCIF_ISR_OFFSET 0x00C /**< \brief (SCIF_ISR offset) Interrupt Status Register */ 211 #define SCIF_ISR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_ISR reset_value) Interrupt Status Register */ 212 213 #define SCIF_ISR_OSC0RDY_Pos 0 /**< \brief (SCIF_ISR) OSC0 Ready */ 214 #define SCIF_ISR_OSC0RDY (_U_(0x1) << SCIF_ISR_OSC0RDY_Pos) 215 #define SCIF_ISR_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_ISR) DFLL0 Lock Coarse */ 216 #define SCIF_ISR_DFLL0LOCKC (_U_(0x1) << SCIF_ISR_DFLL0LOCKC_Pos) 217 #define SCIF_ISR_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_ISR) DFLL0 Lock Fine */ 218 #define SCIF_ISR_DFLL0LOCKF (_U_(0x1) << SCIF_ISR_DFLL0LOCKF_Pos) 219 #define SCIF_ISR_DFLL0RDY_Pos 3 /**< \brief (SCIF_ISR) DFLL0 Ready */ 220 #define SCIF_ISR_DFLL0RDY (_U_(0x1) << SCIF_ISR_DFLL0RDY_Pos) 221 #define SCIF_ISR_DFLL0RCS_Pos 4 /**< \brief (SCIF_ISR) DFLL0 Reference Clock Stopped */ 222 #define SCIF_ISR_DFLL0RCS (_U_(0x1) << SCIF_ISR_DFLL0RCS_Pos) 223 #define SCIF_ISR_DFLL0OOB_Pos 5 /**< \brief (SCIF_ISR) DFLL0 Out Of Bounds */ 224 #define SCIF_ISR_DFLL0OOB (_U_(0x1) << SCIF_ISR_DFLL0OOB_Pos) 225 #define SCIF_ISR_PLL0LOCK_Pos 6 /**< \brief (SCIF_ISR) PLL0 Lock */ 226 #define SCIF_ISR_PLL0LOCK (_U_(0x1) << SCIF_ISR_PLL0LOCK_Pos) 227 #define SCIF_ISR_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_ISR) PLL0 Lock Lost */ 228 #define SCIF_ISR_PLL0LOCKLOST (_U_(0x1) << SCIF_ISR_PLL0LOCKLOST_Pos) 229 #define SCIF_ISR_RCFASTLOCK_Pos 13 /**< \brief (SCIF_ISR) RCFAST Lock */ 230 #define SCIF_ISR_RCFASTLOCK (_U_(0x1) << SCIF_ISR_RCFASTLOCK_Pos) 231 #define SCIF_ISR_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_ISR) RCFAST Lock Lost */ 232 #define SCIF_ISR_RCFASTLOCKLOST (_U_(0x1) << SCIF_ISR_RCFASTLOCKLOST_Pos) 233 #define SCIF_ISR_AE_Pos 31 /**< \brief (SCIF_ISR) Access Error */ 234 #define SCIF_ISR_AE (_U_(0x1) << SCIF_ISR_AE_Pos) 235 #define SCIF_ISR_MASK _U_(0x800060FF) /**< \brief (SCIF_ISR) MASK Register */ 236 237 /* -------- SCIF_ICR : (SCIF Offset: 0x010) ( /W 32) Interrupt Clear Register -------- */ 238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 239 typedef union { 240 struct { 241 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 242 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Lock Coarse */ 243 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Lock Fine */ 244 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Ready */ 245 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 246 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Out Of Bounds */ 247 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Lock */ 248 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 Lock Lost */ 249 uint32_t :5; /*!< bit: 8..12 Reserved */ 250 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Lock */ 251 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST Lock Lost */ 252 uint32_t :16; /*!< bit: 15..30 Reserved */ 253 uint32_t AE:1; /*!< bit: 31 Access Error */ 254 } bit; /*!< Structure used for bit access */ 255 uint32_t reg; /*!< Type used for register access */ 256 } SCIF_ICR_Type; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 #define SCIF_ICR_OFFSET 0x010 /**< \brief (SCIF_ICR offset) Interrupt Clear Register */ 260 #define SCIF_ICR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_ICR reset_value) Interrupt Clear Register */ 261 262 #define SCIF_ICR_OSC0RDY_Pos 0 /**< \brief (SCIF_ICR) OSC0 Ready */ 263 #define SCIF_ICR_OSC0RDY (_U_(0x1) << SCIF_ICR_OSC0RDY_Pos) 264 #define SCIF_ICR_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_ICR) DFLL0 Lock Coarse */ 265 #define SCIF_ICR_DFLL0LOCKC (_U_(0x1) << SCIF_ICR_DFLL0LOCKC_Pos) 266 #define SCIF_ICR_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_ICR) DFLL0 Lock Fine */ 267 #define SCIF_ICR_DFLL0LOCKF (_U_(0x1) << SCIF_ICR_DFLL0LOCKF_Pos) 268 #define SCIF_ICR_DFLL0RDY_Pos 3 /**< \brief (SCIF_ICR) DFLL0 Ready */ 269 #define SCIF_ICR_DFLL0RDY (_U_(0x1) << SCIF_ICR_DFLL0RDY_Pos) 270 #define SCIF_ICR_DFLL0RCS_Pos 4 /**< \brief (SCIF_ICR) DFLL0 Reference Clock Stopped */ 271 #define SCIF_ICR_DFLL0RCS (_U_(0x1) << SCIF_ICR_DFLL0RCS_Pos) 272 #define SCIF_ICR_DFLL0OOB_Pos 5 /**< \brief (SCIF_ICR) DFLL0 Out Of Bounds */ 273 #define SCIF_ICR_DFLL0OOB (_U_(0x1) << SCIF_ICR_DFLL0OOB_Pos) 274 #define SCIF_ICR_PLL0LOCK_Pos 6 /**< \brief (SCIF_ICR) PLL0 Lock */ 275 #define SCIF_ICR_PLL0LOCK (_U_(0x1) << SCIF_ICR_PLL0LOCK_Pos) 276 #define SCIF_ICR_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_ICR) PLL0 Lock Lost */ 277 #define SCIF_ICR_PLL0LOCKLOST (_U_(0x1) << SCIF_ICR_PLL0LOCKLOST_Pos) 278 #define SCIF_ICR_RCFASTLOCK_Pos 13 /**< \brief (SCIF_ICR) RCFAST Lock */ 279 #define SCIF_ICR_RCFASTLOCK (_U_(0x1) << SCIF_ICR_RCFASTLOCK_Pos) 280 #define SCIF_ICR_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_ICR) RCFAST Lock Lost */ 281 #define SCIF_ICR_RCFASTLOCKLOST (_U_(0x1) << SCIF_ICR_RCFASTLOCKLOST_Pos) 282 #define SCIF_ICR_AE_Pos 31 /**< \brief (SCIF_ICR) Access Error */ 283 #define SCIF_ICR_AE (_U_(0x1) << SCIF_ICR_AE_Pos) 284 #define SCIF_ICR_MASK _U_(0x800060FF) /**< \brief (SCIF_ICR) MASK Register */ 285 286 /* -------- SCIF_PCLKSR : (SCIF Offset: 0x014) (R/ 32) Power and Clocks Status Register -------- */ 287 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 288 typedef union { 289 struct { 290 uint32_t OSC0RDY:1; /*!< bit: 0 OSC0 Ready */ 291 uint32_t DFLL0LOCKC:1; /*!< bit: 1 DFLL0 Locked on Coarse Value */ 292 uint32_t DFLL0LOCKF:1; /*!< bit: 2 DFLL0 Locked on Fine Value */ 293 uint32_t DFLL0RDY:1; /*!< bit: 3 DFLL0 Synchronization Ready */ 294 uint32_t DFLL0RCS:1; /*!< bit: 4 DFLL0 Reference Clock Stopped */ 295 uint32_t DFLL0OOB:1; /*!< bit: 5 DFLL0 Track Out Of Bounds */ 296 uint32_t PLL0LOCK:1; /*!< bit: 6 PLL0 Locked on Accurate value */ 297 uint32_t PLL0LOCKLOST:1; /*!< bit: 7 PLL0 lock lost value */ 298 uint32_t :5; /*!< bit: 8..12 Reserved */ 299 uint32_t RCFASTLOCK:1; /*!< bit: 13 RCFAST Locked on Accurate value */ 300 uint32_t RCFASTLOCKLOST:1; /*!< bit: 14 RCFAST lock lost value */ 301 uint32_t :17; /*!< bit: 15..31 Reserved */ 302 } bit; /*!< Structure used for bit access */ 303 uint32_t reg; /*!< Type used for register access */ 304 } SCIF_PCLKSR_Type; 305 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 306 307 #define SCIF_PCLKSR_OFFSET 0x014 /**< \brief (SCIF_PCLKSR offset) Power and Clocks Status Register */ 308 #define SCIF_PCLKSR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_PCLKSR reset_value) Power and Clocks Status Register */ 309 310 #define SCIF_PCLKSR_OSC0RDY_Pos 0 /**< \brief (SCIF_PCLKSR) OSC0 Ready */ 311 #define SCIF_PCLKSR_OSC0RDY (_U_(0x1) << SCIF_PCLKSR_OSC0RDY_Pos) 312 #define SCIF_PCLKSR_DFLL0LOCKC_Pos 1 /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Coarse Value */ 313 #define SCIF_PCLKSR_DFLL0LOCKC (_U_(0x1) << SCIF_PCLKSR_DFLL0LOCKC_Pos) 314 #define SCIF_PCLKSR_DFLL0LOCKF_Pos 2 /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Fine Value */ 315 #define SCIF_PCLKSR_DFLL0LOCKF (_U_(0x1) << SCIF_PCLKSR_DFLL0LOCKF_Pos) 316 #define SCIF_PCLKSR_DFLL0RDY_Pos 3 /**< \brief (SCIF_PCLKSR) DFLL0 Synchronization Ready */ 317 #define SCIF_PCLKSR_DFLL0RDY (_U_(0x1) << SCIF_PCLKSR_DFLL0RDY_Pos) 318 #define SCIF_PCLKSR_DFLL0RCS_Pos 4 /**< \brief (SCIF_PCLKSR) DFLL0 Reference Clock Stopped */ 319 #define SCIF_PCLKSR_DFLL0RCS (_U_(0x1) << SCIF_PCLKSR_DFLL0RCS_Pos) 320 #define SCIF_PCLKSR_DFLL0OOB_Pos 5 /**< \brief (SCIF_PCLKSR) DFLL0 Track Out Of Bounds */ 321 #define SCIF_PCLKSR_DFLL0OOB (_U_(0x1) << SCIF_PCLKSR_DFLL0OOB_Pos) 322 #define SCIF_PCLKSR_PLL0LOCK_Pos 6 /**< \brief (SCIF_PCLKSR) PLL0 Locked on Accurate value */ 323 #define SCIF_PCLKSR_PLL0LOCK (_U_(0x1) << SCIF_PCLKSR_PLL0LOCK_Pos) 324 #define SCIF_PCLKSR_PLL0LOCKLOST_Pos 7 /**< \brief (SCIF_PCLKSR) PLL0 lock lost value */ 325 #define SCIF_PCLKSR_PLL0LOCKLOST (_U_(0x1) << SCIF_PCLKSR_PLL0LOCKLOST_Pos) 326 #define SCIF_PCLKSR_RCFASTLOCK_Pos 13 /**< \brief (SCIF_PCLKSR) RCFAST Locked on Accurate value */ 327 #define SCIF_PCLKSR_RCFASTLOCK (_U_(0x1) << SCIF_PCLKSR_RCFASTLOCK_Pos) 328 #define SCIF_PCLKSR_RCFASTLOCKLOST_Pos 14 /**< \brief (SCIF_PCLKSR) RCFAST lock lost value */ 329 #define SCIF_PCLKSR_RCFASTLOCKLOST (_U_(0x1) << SCIF_PCLKSR_RCFASTLOCKLOST_Pos) 330 #define SCIF_PCLKSR_MASK _U_(0x000060FF) /**< \brief (SCIF_PCLKSR) MASK Register */ 331 332 /* -------- SCIF_UNLOCK : (SCIF Offset: 0x018) ( /W 32) Unlock Register -------- */ 333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 334 typedef union { 335 struct { 336 uint32_t ADDR:10; /*!< bit: 0.. 9 Unlock Address */ 337 uint32_t :14; /*!< bit: 10..23 Reserved */ 338 uint32_t KEY:8; /*!< bit: 24..31 Unlock Key */ 339 } bit; /*!< Structure used for bit access */ 340 uint32_t reg; /*!< Type used for register access */ 341 } SCIF_UNLOCK_Type; 342 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 343 344 #define SCIF_UNLOCK_OFFSET 0x018 /**< \brief (SCIF_UNLOCK offset) Unlock Register */ 345 #define SCIF_UNLOCK_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_UNLOCK reset_value) Unlock Register */ 346 347 #define SCIF_UNLOCK_ADDR_Pos 0 /**< \brief (SCIF_UNLOCK) Unlock Address */ 348 #define SCIF_UNLOCK_ADDR_Msk (_U_(0x3FF) << SCIF_UNLOCK_ADDR_Pos) 349 #define SCIF_UNLOCK_ADDR(value) (SCIF_UNLOCK_ADDR_Msk & ((value) << SCIF_UNLOCK_ADDR_Pos)) 350 #define SCIF_UNLOCK_KEY_Pos 24 /**< \brief (SCIF_UNLOCK) Unlock Key */ 351 #define SCIF_UNLOCK_KEY_Msk (_U_(0xFF) << SCIF_UNLOCK_KEY_Pos) 352 #define SCIF_UNLOCK_KEY(value) (SCIF_UNLOCK_KEY_Msk & ((value) << SCIF_UNLOCK_KEY_Pos)) 353 #define SCIF_UNLOCK_MASK _U_(0xFF0003FF) /**< \brief (SCIF_UNLOCK) MASK Register */ 354 355 /* -------- SCIF_CSCR : (SCIF Offset: 0x01C) (R/W 32) Chip Specific Configuration Register -------- */ 356 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 357 typedef union { 358 uint32_t reg; /*!< Type used for register access */ 359 } SCIF_CSCR_Type; 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 361 362 #define SCIF_CSCR_OFFSET 0x01C /**< \brief (SCIF_CSCR offset) Chip Specific Configuration Register */ 363 #define SCIF_CSCR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_CSCR reset_value) Chip Specific Configuration Register */ 364 #define SCIF_CSCR_MASK _U_(0xFFFFFFFF) /**< \brief (SCIF_CSCR) MASK Register */ 365 366 /* -------- SCIF_OSCCTRL0 : (SCIF Offset: 0x020) (R/W 32) Oscillator Control Register -------- */ 367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 368 typedef union { 369 struct { 370 uint32_t MODE:1; /*!< bit: 0 Oscillator Mode */ 371 uint32_t GAIN:2; /*!< bit: 1.. 2 Gain */ 372 uint32_t AGC:1; /*!< bit: 3 Automatic Gain Control */ 373 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 374 uint32_t STARTUP:4; /*!< bit: 8..11 Oscillator Start-up Time */ 375 uint32_t :4; /*!< bit: 12..15 Reserved */ 376 uint32_t OSCEN:1; /*!< bit: 16 Oscillator Enable */ 377 uint32_t :15; /*!< bit: 17..31 Reserved */ 378 } bit; /*!< Structure used for bit access */ 379 uint32_t reg; /*!< Type used for register access */ 380 } SCIF_OSCCTRL0_Type; 381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 382 383 #define SCIF_OSCCTRL0_OFFSET 0x020 /**< \brief (SCIF_OSCCTRL0 offset) Oscillator Control Register */ 384 #define SCIF_OSCCTRL0_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_OSCCTRL0 reset_value) Oscillator Control Register */ 385 386 #define SCIF_OSCCTRL0_MODE_Pos 0 /**< \brief (SCIF_OSCCTRL0) Oscillator Mode */ 387 #define SCIF_OSCCTRL0_MODE (_U_(0x1) << SCIF_OSCCTRL0_MODE_Pos) 388 #define SCIF_OSCCTRL0_GAIN_Pos 1 /**< \brief (SCIF_OSCCTRL0) Gain */ 389 #define SCIF_OSCCTRL0_GAIN_Msk (_U_(0x3) << SCIF_OSCCTRL0_GAIN_Pos) 390 #define SCIF_OSCCTRL0_GAIN(value) (SCIF_OSCCTRL0_GAIN_Msk & ((value) << SCIF_OSCCTRL0_GAIN_Pos)) 391 #define SCIF_OSCCTRL0_AGC_Pos 3 /**< \brief (SCIF_OSCCTRL0) Automatic Gain Control */ 392 #define SCIF_OSCCTRL0_AGC (_U_(0x1) << SCIF_OSCCTRL0_AGC_Pos) 393 #define SCIF_OSCCTRL0_STARTUP_Pos 8 /**< \brief (SCIF_OSCCTRL0) Oscillator Start-up Time */ 394 #define SCIF_OSCCTRL0_STARTUP_Msk (_U_(0xF) << SCIF_OSCCTRL0_STARTUP_Pos) 395 #define SCIF_OSCCTRL0_STARTUP(value) (SCIF_OSCCTRL0_STARTUP_Msk & ((value) << SCIF_OSCCTRL0_STARTUP_Pos)) 396 #define SCIF_OSCCTRL0_OSCEN_Pos 16 /**< \brief (SCIF_OSCCTRL0) Oscillator Enable */ 397 #define SCIF_OSCCTRL0_OSCEN (_U_(0x1) << SCIF_OSCCTRL0_OSCEN_Pos) 398 #define SCIF_OSCCTRL0_MASK _U_(0x00010F0F) /**< \brief (SCIF_OSCCTRL0) MASK Register */ 399 400 /* -------- SCIF_PLL : (SCIF Offset: 0x024) (R/W 32) pll PLL0 Control Register -------- */ 401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 402 typedef union { 403 struct { 404 uint32_t PLLEN:1; /*!< bit: 0 PLL Enable */ 405 uint32_t PLLOSC:2; /*!< bit: 1.. 2 PLL Oscillator Select */ 406 uint32_t PLLOPT:3; /*!< bit: 3.. 5 PLL Option */ 407 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 408 uint32_t PLLDIV:4; /*!< bit: 8..11 PLL Division Factor */ 409 uint32_t :4; /*!< bit: 12..15 Reserved */ 410 uint32_t PLLMUL:4; /*!< bit: 16..19 PLL Multiply Factor */ 411 uint32_t :4; /*!< bit: 20..23 Reserved */ 412 uint32_t PLLCOUNT:6; /*!< bit: 24..29 PLL Count */ 413 uint32_t :2; /*!< bit: 30..31 Reserved */ 414 } bit; /*!< Structure used for bit access */ 415 uint32_t reg; /*!< Type used for register access */ 416 } SCIF_PLL_Type; 417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 418 419 #define SCIF_PLL_OFFSET 0x024 /**< \brief (SCIF_PLL offset) PLL0 Control Register */ 420 #define SCIF_PLL_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_PLL reset_value) PLL0 Control Register */ 421 422 #define SCIF_PLL_PLLEN_Pos 0 /**< \brief (SCIF_PLL) PLL Enable */ 423 #define SCIF_PLL_PLLEN (_U_(0x1) << SCIF_PLL_PLLEN_Pos) 424 #define SCIF_PLL_PLLOSC_Pos 1 /**< \brief (SCIF_PLL) PLL Oscillator Select */ 425 #define SCIF_PLL_PLLOSC_Msk (_U_(0x3) << SCIF_PLL_PLLOSC_Pos) 426 #define SCIF_PLL_PLLOSC(value) (SCIF_PLL_PLLOSC_Msk & ((value) << SCIF_PLL_PLLOSC_Pos)) 427 #define SCIF_PLL_PLLOPT_Pos 3 /**< \brief (SCIF_PLL) PLL Option */ 428 #define SCIF_PLL_PLLOPT_Msk (_U_(0x7) << SCIF_PLL_PLLOPT_Pos) 429 #define SCIF_PLL_PLLOPT(value) (SCIF_PLL_PLLOPT_Msk & ((value) << SCIF_PLL_PLLOPT_Pos)) 430 #define SCIF_PLL_PLLDIV_Pos 8 /**< \brief (SCIF_PLL) PLL Division Factor */ 431 #define SCIF_PLL_PLLDIV_Msk (_U_(0xF) << SCIF_PLL_PLLDIV_Pos) 432 #define SCIF_PLL_PLLDIV(value) (SCIF_PLL_PLLDIV_Msk & ((value) << SCIF_PLL_PLLDIV_Pos)) 433 #define SCIF_PLL_PLLMUL_Pos 16 /**< \brief (SCIF_PLL) PLL Multiply Factor */ 434 #define SCIF_PLL_PLLMUL_Msk (_U_(0xF) << SCIF_PLL_PLLMUL_Pos) 435 #define SCIF_PLL_PLLMUL(value) (SCIF_PLL_PLLMUL_Msk & ((value) << SCIF_PLL_PLLMUL_Pos)) 436 #define SCIF_PLL_PLLCOUNT_Pos 24 /**< \brief (SCIF_PLL) PLL Count */ 437 #define SCIF_PLL_PLLCOUNT_Msk (_U_(0x3F) << SCIF_PLL_PLLCOUNT_Pos) 438 #define SCIF_PLL_PLLCOUNT(value) (SCIF_PLL_PLLCOUNT_Msk & ((value) << SCIF_PLL_PLLCOUNT_Pos)) 439 #define SCIF_PLL_MASK _U_(0x3F0F0F3F) /**< \brief (SCIF_PLL) MASK Register */ 440 441 /* -------- SCIF_DFLL0CONF : (SCIF Offset: 0x028) (R/W 32) DFLL0 Config Register -------- */ 442 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 443 typedef union { 444 struct { 445 uint32_t EN:1; /*!< bit: 0 Enable */ 446 uint32_t MODE:1; /*!< bit: 1 Mode Selection */ 447 uint32_t STABLE:1; /*!< bit: 2 Stable DFLL Frequency */ 448 uint32_t LLAW:1; /*!< bit: 3 Lose Lock After Wake */ 449 uint32_t :1; /*!< bit: 4 Reserved */ 450 uint32_t CCDIS:1; /*!< bit: 5 Chill Cycle Disable */ 451 uint32_t QLDIS:1; /*!< bit: 6 Quick Lock Disable */ 452 uint32_t :9; /*!< bit: 7..15 Reserved */ 453 uint32_t RANGE:2; /*!< bit: 16..17 Range Value */ 454 uint32_t :5; /*!< bit: 18..22 Reserved */ 455 uint32_t FCD:1; /*!< bit: 23 Fuse Calibration Done */ 456 uint32_t CALIB:4; /*!< bit: 24..27 Calibration Value */ 457 uint32_t :4; /*!< bit: 28..31 Reserved */ 458 } bit; /*!< Structure used for bit access */ 459 uint32_t reg; /*!< Type used for register access */ 460 } SCIF_DFLL0CONF_Type; 461 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 462 463 #define SCIF_DFLL0CONF_OFFSET 0x028 /**< \brief (SCIF_DFLL0CONF offset) DFLL0 Config Register */ 464 #define SCIF_DFLL0CONF_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0CONF reset_value) DFLL0 Config Register */ 465 466 #define SCIF_DFLL0CONF_EN_Pos 0 /**< \brief (SCIF_DFLL0CONF) Enable */ 467 #define SCIF_DFLL0CONF_EN (_U_(0x1) << SCIF_DFLL0CONF_EN_Pos) 468 #define SCIF_DFLL0CONF_MODE_Pos 1 /**< \brief (SCIF_DFLL0CONF) Mode Selection */ 469 #define SCIF_DFLL0CONF_MODE (_U_(0x1) << SCIF_DFLL0CONF_MODE_Pos) 470 #define SCIF_DFLL0CONF_STABLE_Pos 2 /**< \brief (SCIF_DFLL0CONF) Stable DFLL Frequency */ 471 #define SCIF_DFLL0CONF_STABLE (_U_(0x1) << SCIF_DFLL0CONF_STABLE_Pos) 472 #define SCIF_DFLL0CONF_LLAW_Pos 3 /**< \brief (SCIF_DFLL0CONF) Lose Lock After Wake */ 473 #define SCIF_DFLL0CONF_LLAW (_U_(0x1) << SCIF_DFLL0CONF_LLAW_Pos) 474 #define SCIF_DFLL0CONF_CCDIS_Pos 5 /**< \brief (SCIF_DFLL0CONF) Chill Cycle Disable */ 475 #define SCIF_DFLL0CONF_CCDIS (_U_(0x1) << SCIF_DFLL0CONF_CCDIS_Pos) 476 #define SCIF_DFLL0CONF_QLDIS_Pos 6 /**< \brief (SCIF_DFLL0CONF) Quick Lock Disable */ 477 #define SCIF_DFLL0CONF_QLDIS (_U_(0x1) << SCIF_DFLL0CONF_QLDIS_Pos) 478 #define SCIF_DFLL0CONF_RANGE_Pos 16 /**< \brief (SCIF_DFLL0CONF) Range Value */ 479 #define SCIF_DFLL0CONF_RANGE_Msk (_U_(0x3) << SCIF_DFLL0CONF_RANGE_Pos) 480 #define SCIF_DFLL0CONF_RANGE(value) (SCIF_DFLL0CONF_RANGE_Msk & ((value) << SCIF_DFLL0CONF_RANGE_Pos)) 481 #define SCIF_DFLL0CONF_FCD_Pos 23 /**< \brief (SCIF_DFLL0CONF) Fuse Calibration Done */ 482 #define SCIF_DFLL0CONF_FCD (_U_(0x1) << SCIF_DFLL0CONF_FCD_Pos) 483 #define SCIF_DFLL0CONF_CALIB_Pos 24 /**< \brief (SCIF_DFLL0CONF) Calibration Value */ 484 #define SCIF_DFLL0CONF_CALIB_Msk (_U_(0xF) << SCIF_DFLL0CONF_CALIB_Pos) 485 #define SCIF_DFLL0CONF_CALIB(value) (SCIF_DFLL0CONF_CALIB_Msk & ((value) << SCIF_DFLL0CONF_CALIB_Pos)) 486 #define SCIF_DFLL0CONF_MASK _U_(0x0F83006F) /**< \brief (SCIF_DFLL0CONF) MASK Register */ 487 488 /* -------- SCIF_DFLL0VAL : (SCIF Offset: 0x02C) (R/W 32) DFLL Value Register -------- */ 489 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 490 typedef union { 491 struct { 492 uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */ 493 uint32_t :8; /*!< bit: 8..15 Reserved */ 494 uint32_t COARSE:5; /*!< bit: 16..20 Coarse Value */ 495 uint32_t :11; /*!< bit: 21..31 Reserved */ 496 } bit; /*!< Structure used for bit access */ 497 uint32_t reg; /*!< Type used for register access */ 498 } SCIF_DFLL0VAL_Type; 499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 500 501 #define SCIF_DFLL0VAL_OFFSET 0x02C /**< \brief (SCIF_DFLL0VAL offset) DFLL Value Register */ 502 #define SCIF_DFLL0VAL_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0VAL reset_value) DFLL Value Register */ 503 504 #define SCIF_DFLL0VAL_FINE_Pos 0 /**< \brief (SCIF_DFLL0VAL) Fine Value */ 505 #define SCIF_DFLL0VAL_FINE_Msk (_U_(0xFF) << SCIF_DFLL0VAL_FINE_Pos) 506 #define SCIF_DFLL0VAL_FINE(value) (SCIF_DFLL0VAL_FINE_Msk & ((value) << SCIF_DFLL0VAL_FINE_Pos)) 507 #define SCIF_DFLL0VAL_COARSE_Pos 16 /**< \brief (SCIF_DFLL0VAL) Coarse Value */ 508 #define SCIF_DFLL0VAL_COARSE_Msk (_U_(0x1F) << SCIF_DFLL0VAL_COARSE_Pos) 509 #define SCIF_DFLL0VAL_COARSE(value) (SCIF_DFLL0VAL_COARSE_Msk & ((value) << SCIF_DFLL0VAL_COARSE_Pos)) 510 #define SCIF_DFLL0VAL_MASK _U_(0x001F00FF) /**< \brief (SCIF_DFLL0VAL) MASK Register */ 511 512 /* -------- SCIF_DFLL0MUL : (SCIF Offset: 0x030) (R/W 32) DFLL0 Multiplier Register -------- */ 513 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 514 typedef union { 515 struct { 516 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ 517 uint32_t :16; /*!< bit: 16..31 Reserved */ 518 } bit; /*!< Structure used for bit access */ 519 uint32_t reg; /*!< Type used for register access */ 520 } SCIF_DFLL0MUL_Type; 521 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 522 523 #define SCIF_DFLL0MUL_OFFSET 0x030 /**< \brief (SCIF_DFLL0MUL offset) DFLL0 Multiplier Register */ 524 #define SCIF_DFLL0MUL_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0MUL reset_value) DFLL0 Multiplier Register */ 525 526 #define SCIF_DFLL0MUL_MUL_Pos 0 /**< \brief (SCIF_DFLL0MUL) DFLL Multiply Factor */ 527 #define SCIF_DFLL0MUL_MUL_Msk (_U_(0xFFFF) << SCIF_DFLL0MUL_MUL_Pos) 528 #define SCIF_DFLL0MUL_MUL(value) (SCIF_DFLL0MUL_MUL_Msk & ((value) << SCIF_DFLL0MUL_MUL_Pos)) 529 #define SCIF_DFLL0MUL_MASK _U_(0x0000FFFF) /**< \brief (SCIF_DFLL0MUL) MASK Register */ 530 531 /* -------- SCIF_DFLL0STEP : (SCIF Offset: 0x034) (R/W 32) DFLL0 Step Register -------- */ 532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 533 typedef union { 534 struct { 535 uint32_t FSTEP:8; /*!< bit: 0.. 7 Fine Maximum Step */ 536 uint32_t :8; /*!< bit: 8..15 Reserved */ 537 uint32_t CSTEP:5; /*!< bit: 16..20 Coarse Maximum Step */ 538 uint32_t :11; /*!< bit: 21..31 Reserved */ 539 } bit; /*!< Structure used for bit access */ 540 uint32_t reg; /*!< Type used for register access */ 541 } SCIF_DFLL0STEP_Type; 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 543 544 #define SCIF_DFLL0STEP_OFFSET 0x034 /**< \brief (SCIF_DFLL0STEP offset) DFLL0 Step Register */ 545 #define SCIF_DFLL0STEP_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0STEP reset_value) DFLL0 Step Register */ 546 547 #define SCIF_DFLL0STEP_FSTEP_Pos 0 /**< \brief (SCIF_DFLL0STEP) Fine Maximum Step */ 548 #define SCIF_DFLL0STEP_FSTEP_Msk (_U_(0xFF) << SCIF_DFLL0STEP_FSTEP_Pos) 549 #define SCIF_DFLL0STEP_FSTEP(value) (SCIF_DFLL0STEP_FSTEP_Msk & ((value) << SCIF_DFLL0STEP_FSTEP_Pos)) 550 #define SCIF_DFLL0STEP_CSTEP_Pos 16 /**< \brief (SCIF_DFLL0STEP) Coarse Maximum Step */ 551 #define SCIF_DFLL0STEP_CSTEP_Msk (_U_(0x1F) << SCIF_DFLL0STEP_CSTEP_Pos) 552 #define SCIF_DFLL0STEP_CSTEP(value) (SCIF_DFLL0STEP_CSTEP_Msk & ((value) << SCIF_DFLL0STEP_CSTEP_Pos)) 553 #define SCIF_DFLL0STEP_MASK _U_(0x001F00FF) /**< \brief (SCIF_DFLL0STEP) MASK Register */ 554 555 /* -------- SCIF_DFLL0SSG : (SCIF Offset: 0x038) (R/W 32) DFLL0 Spread Spectrum Generator Control Register -------- */ 556 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 557 typedef union { 558 struct { 559 uint32_t EN:1; /*!< bit: 0 Enable */ 560 uint32_t PRBS:1; /*!< bit: 1 Pseudo Random Bit Sequence */ 561 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 562 uint32_t AMPLITUDE:5; /*!< bit: 8..12 SSG Amplitude */ 563 uint32_t :3; /*!< bit: 13..15 Reserved */ 564 uint32_t STEPSIZE:5; /*!< bit: 16..20 SSG Step Size */ 565 uint32_t :11; /*!< bit: 21..31 Reserved */ 566 } bit; /*!< Structure used for bit access */ 567 uint32_t reg; /*!< Type used for register access */ 568 } SCIF_DFLL0SSG_Type; 569 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 570 571 #define SCIF_DFLL0SSG_OFFSET 0x038 /**< \brief (SCIF_DFLL0SSG offset) DFLL0 Spread Spectrum Generator Control Register */ 572 #define SCIF_DFLL0SSG_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0SSG reset_value) DFLL0 Spread Spectrum Generator Control Register */ 573 574 #define SCIF_DFLL0SSG_EN_Pos 0 /**< \brief (SCIF_DFLL0SSG) Enable */ 575 #define SCIF_DFLL0SSG_EN (_U_(0x1) << SCIF_DFLL0SSG_EN_Pos) 576 #define SCIF_DFLL0SSG_PRBS_Pos 1 /**< \brief (SCIF_DFLL0SSG) Pseudo Random Bit Sequence */ 577 #define SCIF_DFLL0SSG_PRBS (_U_(0x1) << SCIF_DFLL0SSG_PRBS_Pos) 578 #define SCIF_DFLL0SSG_AMPLITUDE_Pos 8 /**< \brief (SCIF_DFLL0SSG) SSG Amplitude */ 579 #define SCIF_DFLL0SSG_AMPLITUDE_Msk (_U_(0x1F) << SCIF_DFLL0SSG_AMPLITUDE_Pos) 580 #define SCIF_DFLL0SSG_AMPLITUDE(value) (SCIF_DFLL0SSG_AMPLITUDE_Msk & ((value) << SCIF_DFLL0SSG_AMPLITUDE_Pos)) 581 #define SCIF_DFLL0SSG_STEPSIZE_Pos 16 /**< \brief (SCIF_DFLL0SSG) SSG Step Size */ 582 #define SCIF_DFLL0SSG_STEPSIZE_Msk (_U_(0x1F) << SCIF_DFLL0SSG_STEPSIZE_Pos) 583 #define SCIF_DFLL0SSG_STEPSIZE(value) (SCIF_DFLL0SSG_STEPSIZE_Msk & ((value) << SCIF_DFLL0SSG_STEPSIZE_Pos)) 584 #define SCIF_DFLL0SSG_MASK _U_(0x001F1F03) /**< \brief (SCIF_DFLL0SSG) MASK Register */ 585 586 /* -------- SCIF_DFLL0RATIO : (SCIF Offset: 0x03C) (R/ 32) DFLL0 Ratio Registe -------- */ 587 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 588 typedef union { 589 struct { 590 uint32_t RATIODIFF:16; /*!< bit: 0..15 Multiplication Ratio Difference */ 591 uint32_t :16; /*!< bit: 16..31 Reserved */ 592 } bit; /*!< Structure used for bit access */ 593 uint32_t reg; /*!< Type used for register access */ 594 } SCIF_DFLL0RATIO_Type; 595 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 596 597 #define SCIF_DFLL0RATIO_OFFSET 0x03C /**< \brief (SCIF_DFLL0RATIO offset) DFLL0 Ratio Registe */ 598 #define SCIF_DFLL0RATIO_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0RATIO reset_value) DFLL0 Ratio Registe */ 599 600 #define SCIF_DFLL0RATIO_RATIODIFF_Pos 0 /**< \brief (SCIF_DFLL0RATIO) Multiplication Ratio Difference */ 601 #define SCIF_DFLL0RATIO_RATIODIFF_Msk (_U_(0xFFFF) << SCIF_DFLL0RATIO_RATIODIFF_Pos) 602 #define SCIF_DFLL0RATIO_RATIODIFF(value) (SCIF_DFLL0RATIO_RATIODIFF_Msk & ((value) << SCIF_DFLL0RATIO_RATIODIFF_Pos)) 603 #define SCIF_DFLL0RATIO_MASK _U_(0x0000FFFF) /**< \brief (SCIF_DFLL0RATIO) MASK Register */ 604 605 /* -------- SCIF_DFLL0SYNC : (SCIF Offset: 0x040) ( /W 32) DFLL0 Synchronization Register -------- */ 606 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 607 typedef union { 608 struct { 609 uint32_t SYNC:1; /*!< bit: 0 Synchronization */ 610 uint32_t :31; /*!< bit: 1..31 Reserved */ 611 } bit; /*!< Structure used for bit access */ 612 uint32_t reg; /*!< Type used for register access */ 613 } SCIF_DFLL0SYNC_Type; 614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 615 616 #define SCIF_DFLL0SYNC_OFFSET 0x040 /**< \brief (SCIF_DFLL0SYNC offset) DFLL0 Synchronization Register */ 617 #define SCIF_DFLL0SYNC_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_DFLL0SYNC reset_value) DFLL0 Synchronization Register */ 618 619 #define SCIF_DFLL0SYNC_SYNC_Pos 0 /**< \brief (SCIF_DFLL0SYNC) Synchronization */ 620 #define SCIF_DFLL0SYNC_SYNC (_U_(0x1) << SCIF_DFLL0SYNC_SYNC_Pos) 621 #define SCIF_DFLL0SYNC_MASK _U_(0x00000001) /**< \brief (SCIF_DFLL0SYNC) MASK Register */ 622 623 /* -------- SCIF_RCCR : (SCIF Offset: 0x044) (R/W 32) System RC Oscillator Calibration Register -------- */ 624 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 625 typedef union { 626 struct { 627 uint32_t CALIB:10; /*!< bit: 0.. 9 Calibration Value */ 628 uint32_t :6; /*!< bit: 10..15 Reserved */ 629 uint32_t FCD:1; /*!< bit: 16 Flash Calibration Done */ 630 uint32_t :15; /*!< bit: 17..31 Reserved */ 631 } bit; /*!< Structure used for bit access */ 632 uint32_t reg; /*!< Type used for register access */ 633 } SCIF_RCCR_Type; 634 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 635 636 #define SCIF_RCCR_OFFSET 0x044 /**< \brief (SCIF_RCCR offset) System RC Oscillator Calibration Register */ 637 638 #define SCIF_RCCR_CALIB_Pos 0 /**< \brief (SCIF_RCCR) Calibration Value */ 639 #define SCIF_RCCR_CALIB_Msk (_U_(0x3FF) << SCIF_RCCR_CALIB_Pos) 640 #define SCIF_RCCR_CALIB(value) (SCIF_RCCR_CALIB_Msk & ((value) << SCIF_RCCR_CALIB_Pos)) 641 #define SCIF_RCCR_FCD_Pos 16 /**< \brief (SCIF_RCCR) Flash Calibration Done */ 642 #define SCIF_RCCR_FCD (_U_(0x1) << SCIF_RCCR_FCD_Pos) 643 #define SCIF_RCCR_MASK _U_(0x000103FF) /**< \brief (SCIF_RCCR) MASK Register */ 644 645 /* -------- SCIF_RCFASTCFG : (SCIF Offset: 0x048) (R/W 32) 4/8/12 MHz RC Oscillator Configuration Register -------- */ 646 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 647 typedef union { 648 struct { 649 uint32_t EN:1; /*!< bit: 0 Oscillator Enable */ 650 uint32_t TUNEEN:1; /*!< bit: 1 Tuner Enable */ 651 uint32_t JITMODE:1; /*!< bit: 2 Jitter Mode */ 652 uint32_t :1; /*!< bit: 3 Reserved */ 653 uint32_t NBPERIODS:3; /*!< bit: 4.. 6 Number of 32kHz Periods */ 654 uint32_t FCD:1; /*!< bit: 7 RCFAST Fuse Calibration Done */ 655 uint32_t FRANGE:2; /*!< bit: 8.. 9 Frequency Range */ 656 uint32_t :2; /*!< bit: 10..11 Reserved */ 657 uint32_t LOCKMARGIN:4; /*!< bit: 12..15 Accepted Count Error for Lock */ 658 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration Value */ 659 uint32_t :9; /*!< bit: 23..31 Reserved */ 660 } bit; /*!< Structure used for bit access */ 661 uint32_t reg; /*!< Type used for register access */ 662 } SCIF_RCFASTCFG_Type; 663 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 664 665 #define SCIF_RCFASTCFG_OFFSET 0x048 /**< \brief (SCIF_RCFASTCFG offset) 4/8/12 MHz RC Oscillator Configuration Register */ 666 #define SCIF_RCFASTCFG_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_RCFASTCFG reset_value) 4/8/12 MHz RC Oscillator Configuration Register */ 667 668 #define SCIF_RCFASTCFG_EN_Pos 0 /**< \brief (SCIF_RCFASTCFG) Oscillator Enable */ 669 #define SCIF_RCFASTCFG_EN (_U_(0x1) << SCIF_RCFASTCFG_EN_Pos) 670 #define SCIF_RCFASTCFG_TUNEEN_Pos 1 /**< \brief (SCIF_RCFASTCFG) Tuner Enable */ 671 #define SCIF_RCFASTCFG_TUNEEN (_U_(0x1) << SCIF_RCFASTCFG_TUNEEN_Pos) 672 #define SCIF_RCFASTCFG_JITMODE_Pos 2 /**< \brief (SCIF_RCFASTCFG) Jitter Mode */ 673 #define SCIF_RCFASTCFG_JITMODE (_U_(0x1) << SCIF_RCFASTCFG_JITMODE_Pos) 674 #define SCIF_RCFASTCFG_NBPERIODS_Pos 4 /**< \brief (SCIF_RCFASTCFG) Number of 32kHz Periods */ 675 #define SCIF_RCFASTCFG_NBPERIODS_Msk (_U_(0x7) << SCIF_RCFASTCFG_NBPERIODS_Pos) 676 #define SCIF_RCFASTCFG_NBPERIODS(value) (SCIF_RCFASTCFG_NBPERIODS_Msk & ((value) << SCIF_RCFASTCFG_NBPERIODS_Pos)) 677 #define SCIF_RCFASTCFG_FCD_Pos 7 /**< \brief (SCIF_RCFASTCFG) RCFAST Fuse Calibration Done */ 678 #define SCIF_RCFASTCFG_FCD (_U_(0x1) << SCIF_RCFASTCFG_FCD_Pos) 679 #define SCIF_RCFASTCFG_FRANGE_Pos 8 /**< \brief (SCIF_RCFASTCFG) Frequency Range */ 680 #define SCIF_RCFASTCFG_FRANGE_Msk (_U_(0x3) << SCIF_RCFASTCFG_FRANGE_Pos) 681 #define SCIF_RCFASTCFG_FRANGE(value) (SCIF_RCFASTCFG_FRANGE_Msk & ((value) << SCIF_RCFASTCFG_FRANGE_Pos)) 682 #define SCIF_RCFASTCFG_LOCKMARGIN_Pos 12 /**< \brief (SCIF_RCFASTCFG) Accepted Count Error for Lock */ 683 #define SCIF_RCFASTCFG_LOCKMARGIN_Msk (_U_(0xF) << SCIF_RCFASTCFG_LOCKMARGIN_Pos) 684 #define SCIF_RCFASTCFG_LOCKMARGIN(value) (SCIF_RCFASTCFG_LOCKMARGIN_Msk & ((value) << SCIF_RCFASTCFG_LOCKMARGIN_Pos)) 685 #define SCIF_RCFASTCFG_CALIB_Pos 16 /**< \brief (SCIF_RCFASTCFG) Oscillator Calibration Value */ 686 #define SCIF_RCFASTCFG_CALIB_Msk (_U_(0x7F) << SCIF_RCFASTCFG_CALIB_Pos) 687 #define SCIF_RCFASTCFG_CALIB(value) (SCIF_RCFASTCFG_CALIB_Msk & ((value) << SCIF_RCFASTCFG_CALIB_Pos)) 688 #define SCIF_RCFASTCFG_MASK _U_(0x007FF3F7) /**< \brief (SCIF_RCFASTCFG) MASK Register */ 689 690 /* -------- SCIF_RCFASTSR : (SCIF Offset: 0x04C) (R/W 32) 4/8/12 MHz RC Oscillator Status Register -------- */ 691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 692 typedef union { 693 struct { 694 uint32_t CURTRIM:7; /*!< bit: 0.. 6 Current Trim Value */ 695 uint32_t :9; /*!< bit: 7..15 Reserved */ 696 uint32_t CNTERR:5; /*!< bit: 16..20 Current Count Error */ 697 uint32_t SIGN:1; /*!< bit: 21 Sign of Current Count Error */ 698 uint32_t :2; /*!< bit: 22..23 Reserved */ 699 uint32_t LOCK:1; /*!< bit: 24 Lock */ 700 uint32_t LOCKLOST:1; /*!< bit: 25 Lock Lost */ 701 uint32_t :5; /*!< bit: 26..30 Reserved */ 702 uint32_t UPDATED:1; /*!< bit: 31 Current Trim Value Updated */ 703 } bit; /*!< Structure used for bit access */ 704 uint32_t reg; /*!< Type used for register access */ 705 } SCIF_RCFASTSR_Type; 706 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 707 708 #define SCIF_RCFASTSR_OFFSET 0x04C /**< \brief (SCIF_RCFASTSR offset) 4/8/12 MHz RC Oscillator Status Register */ 709 #define SCIF_RCFASTSR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_RCFASTSR reset_value) 4/8/12 MHz RC Oscillator Status Register */ 710 711 #define SCIF_RCFASTSR_CURTRIM_Pos 0 /**< \brief (SCIF_RCFASTSR) Current Trim Value */ 712 #define SCIF_RCFASTSR_CURTRIM_Msk (_U_(0x7F) << SCIF_RCFASTSR_CURTRIM_Pos) 713 #define SCIF_RCFASTSR_CURTRIM(value) (SCIF_RCFASTSR_CURTRIM_Msk & ((value) << SCIF_RCFASTSR_CURTRIM_Pos)) 714 #define SCIF_RCFASTSR_CNTERR_Pos 16 /**< \brief (SCIF_RCFASTSR) Current Count Error */ 715 #define SCIF_RCFASTSR_CNTERR_Msk (_U_(0x1F) << SCIF_RCFASTSR_CNTERR_Pos) 716 #define SCIF_RCFASTSR_CNTERR(value) (SCIF_RCFASTSR_CNTERR_Msk & ((value) << SCIF_RCFASTSR_CNTERR_Pos)) 717 #define SCIF_RCFASTSR_SIGN_Pos 21 /**< \brief (SCIF_RCFASTSR) Sign of Current Count Error */ 718 #define SCIF_RCFASTSR_SIGN (_U_(0x1) << SCIF_RCFASTSR_SIGN_Pos) 719 #define SCIF_RCFASTSR_LOCK_Pos 24 /**< \brief (SCIF_RCFASTSR) Lock */ 720 #define SCIF_RCFASTSR_LOCK (_U_(0x1) << SCIF_RCFASTSR_LOCK_Pos) 721 #define SCIF_RCFASTSR_LOCKLOST_Pos 25 /**< \brief (SCIF_RCFASTSR) Lock Lost */ 722 #define SCIF_RCFASTSR_LOCKLOST (_U_(0x1) << SCIF_RCFASTSR_LOCKLOST_Pos) 723 #define SCIF_RCFASTSR_UPDATED_Pos 31 /**< \brief (SCIF_RCFASTSR) Current Trim Value Updated */ 724 #define SCIF_RCFASTSR_UPDATED (_U_(0x1) << SCIF_RCFASTSR_UPDATED_Pos) 725 #define SCIF_RCFASTSR_MASK _U_(0x833F007F) /**< \brief (SCIF_RCFASTSR) MASK Register */ 726 727 /* -------- SCIF_RC80MCR : (SCIF Offset: 0x050) (R/W 32) 80 MHz RC Oscillator Register -------- */ 728 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 729 typedef union { 730 struct { 731 uint32_t EN:1; /*!< bit: 0 Enable */ 732 uint32_t :6; /*!< bit: 1.. 6 Reserved */ 733 uint32_t FCD:1; /*!< bit: 7 Flash Calibration Done */ 734 uint32_t :8; /*!< bit: 8..15 Reserved */ 735 uint32_t CALIB:2; /*!< bit: 16..17 Calibration Value */ 736 uint32_t :14; /*!< bit: 18..31 Reserved */ 737 } bit; /*!< Structure used for bit access */ 738 uint32_t reg; /*!< Type used for register access */ 739 } SCIF_RC80MCR_Type; 740 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 741 742 #define SCIF_RC80MCR_OFFSET 0x050 /**< \brief (SCIF_RC80MCR offset) 80 MHz RC Oscillator Register */ 743 #define SCIF_RC80MCR_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_RC80MCR reset_value) 80 MHz RC Oscillator Register */ 744 745 #define SCIF_RC80MCR_EN_Pos 0 /**< \brief (SCIF_RC80MCR) Enable */ 746 #define SCIF_RC80MCR_EN (_U_(0x1) << SCIF_RC80MCR_EN_Pos) 747 #define SCIF_RC80MCR_FCD_Pos 7 /**< \brief (SCIF_RC80MCR) Flash Calibration Done */ 748 #define SCIF_RC80MCR_FCD (_U_(0x1) << SCIF_RC80MCR_FCD_Pos) 749 #define SCIF_RC80MCR_CALIB_Pos 16 /**< \brief (SCIF_RC80MCR) Calibration Value */ 750 #define SCIF_RC80MCR_CALIB_Msk (_U_(0x3) << SCIF_RC80MCR_CALIB_Pos) 751 #define SCIF_RC80MCR_CALIB(value) (SCIF_RC80MCR_CALIB_Msk & ((value) << SCIF_RC80MCR_CALIB_Pos)) 752 #define SCIF_RC80MCR_MASK _U_(0x00030081) /**< \brief (SCIF_RC80MCR) MASK Register */ 753 754 /* -------- SCIF_HRPCR : (SCIF Offset: 0x064) (R/W 32) High Resolution Prescaler Control Register -------- */ 755 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 756 typedef union { 757 struct { 758 uint32_t HRPEN:1; /*!< bit: 0 High Resolution Prescaler Enable */ 759 uint32_t CKSEL:3; /*!< bit: 1.. 3 Clock Input Selection */ 760 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 761 uint32_t HRCOUNT:24; /*!< bit: 8..31 High Resolution Counter */ 762 } bit; /*!< Structure used for bit access */ 763 uint32_t reg; /*!< Type used for register access */ 764 } SCIF_HRPCR_Type; 765 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 766 767 #define SCIF_HRPCR_OFFSET 0x064 /**< \brief (SCIF_HRPCR offset) High Resolution Prescaler Control Register */ 768 769 #define SCIF_HRPCR_HRPEN_Pos 0 /**< \brief (SCIF_HRPCR) High Resolution Prescaler Enable */ 770 #define SCIF_HRPCR_HRPEN (_U_(0x1) << SCIF_HRPCR_HRPEN_Pos) 771 #define SCIF_HRPCR_CKSEL_Pos 1 /**< \brief (SCIF_HRPCR) Clock Input Selection */ 772 #define SCIF_HRPCR_CKSEL_Msk (_U_(0x7) << SCIF_HRPCR_CKSEL_Pos) 773 #define SCIF_HRPCR_CKSEL(value) (SCIF_HRPCR_CKSEL_Msk & ((value) << SCIF_HRPCR_CKSEL_Pos)) 774 #define SCIF_HRPCR_HRCOUNT_Pos 8 /**< \brief (SCIF_HRPCR) High Resolution Counter */ 775 #define SCIF_HRPCR_HRCOUNT_Msk (_U_(0xFFFFFF) << SCIF_HRPCR_HRCOUNT_Pos) 776 #define SCIF_HRPCR_HRCOUNT(value) (SCIF_HRPCR_HRCOUNT_Msk & ((value) << SCIF_HRPCR_HRCOUNT_Pos)) 777 #define SCIF_HRPCR_MASK _U_(0xFFFFFF0F) /**< \brief (SCIF_HRPCR) MASK Register */ 778 779 /* -------- SCIF_FPCR : (SCIF Offset: 0x068) (R/W 32) Fractional Prescaler Control Register -------- */ 780 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 781 typedef union { 782 struct { 783 uint32_t FPEN:1; /*!< bit: 0 High Resolution Prescaler Enable */ 784 uint32_t CKSEL:3; /*!< bit: 1.. 3 Clock Input Selection */ 785 uint32_t :28; /*!< bit: 4..31 Reserved */ 786 } bit; /*!< Structure used for bit access */ 787 uint32_t reg; /*!< Type used for register access */ 788 } SCIF_FPCR_Type; 789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 790 791 #define SCIF_FPCR_OFFSET 0x068 /**< \brief (SCIF_FPCR offset) Fractional Prescaler Control Register */ 792 793 #define SCIF_FPCR_FPEN_Pos 0 /**< \brief (SCIF_FPCR) High Resolution Prescaler Enable */ 794 #define SCIF_FPCR_FPEN (_U_(0x1) << SCIF_FPCR_FPEN_Pos) 795 #define SCIF_FPCR_CKSEL_Pos 1 /**< \brief (SCIF_FPCR) Clock Input Selection */ 796 #define SCIF_FPCR_CKSEL_Msk (_U_(0x7) << SCIF_FPCR_CKSEL_Pos) 797 #define SCIF_FPCR_CKSEL(value) (SCIF_FPCR_CKSEL_Msk & ((value) << SCIF_FPCR_CKSEL_Pos)) 798 #define SCIF_FPCR_MASK _U_(0x0000000F) /**< \brief (SCIF_FPCR) MASK Register */ 799 800 /* -------- SCIF_FPMUL : (SCIF Offset: 0x06C) (R/W 32) Fractional Prescaler Multiplier Register -------- */ 801 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 802 typedef union { 803 struct { 804 uint32_t FPMUL:16; /*!< bit: 0..15 Fractional Prescaler Multiplication Factor */ 805 uint32_t :16; /*!< bit: 16..31 Reserved */ 806 } bit; /*!< Structure used for bit access */ 807 uint32_t reg; /*!< Type used for register access */ 808 } SCIF_FPMUL_Type; 809 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 810 811 #define SCIF_FPMUL_OFFSET 0x06C /**< \brief (SCIF_FPMUL offset) Fractional Prescaler Multiplier Register */ 812 813 #define SCIF_FPMUL_FPMUL_Pos 0 /**< \brief (SCIF_FPMUL) Fractional Prescaler Multiplication Factor */ 814 #define SCIF_FPMUL_FPMUL_Msk (_U_(0xFFFF) << SCIF_FPMUL_FPMUL_Pos) 815 #define SCIF_FPMUL_FPMUL(value) (SCIF_FPMUL_FPMUL_Msk & ((value) << SCIF_FPMUL_FPMUL_Pos)) 816 #define SCIF_FPMUL_MASK _U_(0x0000FFFF) /**< \brief (SCIF_FPMUL) MASK Register */ 817 818 /* -------- SCIF_FPDIV : (SCIF Offset: 0x070) (R/W 32) Fractional Prescaler DIVIDER Register -------- */ 819 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 820 typedef union { 821 struct { 822 uint32_t FPDIV:16; /*!< bit: 0..15 Fractional Prescaler Division Factor */ 823 uint32_t :16; /*!< bit: 16..31 Reserved */ 824 } bit; /*!< Structure used for bit access */ 825 uint32_t reg; /*!< Type used for register access */ 826 } SCIF_FPDIV_Type; 827 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 828 829 #define SCIF_FPDIV_OFFSET 0x070 /**< \brief (SCIF_FPDIV offset) Fractional Prescaler DIVIDER Register */ 830 831 #define SCIF_FPDIV_FPDIV_Pos 0 /**< \brief (SCIF_FPDIV) Fractional Prescaler Division Factor */ 832 #define SCIF_FPDIV_FPDIV_Msk (_U_(0xFFFF) << SCIF_FPDIV_FPDIV_Pos) 833 #define SCIF_FPDIV_FPDIV(value) (SCIF_FPDIV_FPDIV_Msk & ((value) << SCIF_FPDIV_FPDIV_Pos)) 834 #define SCIF_FPDIV_MASK _U_(0x0000FFFF) /**< \brief (SCIF_FPDIV) MASK Register */ 835 836 /* -------- SCIF_GCCTRL : (SCIF Offset: 0x074) (R/W 32) gcctrl Generic Clock Control -------- */ 837 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 838 typedef union { 839 struct { 840 uint32_t CEN:1; /*!< bit: 0 Clock Enable */ 841 uint32_t DIVEN:1; /*!< bit: 1 Divide Enable */ 842 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 843 uint32_t OSCSEL:5; /*!< bit: 8..12 Clock Select */ 844 uint32_t :3; /*!< bit: 13..15 Reserved */ 845 uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ 846 } bit; /*!< Structure used for bit access */ 847 uint32_t reg; /*!< Type used for register access */ 848 } SCIF_GCCTRL_Type; 849 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 850 851 #define SCIF_GCCTRL_OFFSET 0x074 /**< \brief (SCIF_GCCTRL offset) Generic Clock Control */ 852 #define SCIF_GCCTRL_RESETVALUE _U_(0x00000000); /**< \brief (SCIF_GCCTRL reset_value) Generic Clock Control */ 853 854 #define SCIF_GCCTRL_CEN_Pos 0 /**< \brief (SCIF_GCCTRL) Clock Enable */ 855 #define SCIF_GCCTRL_CEN (_U_(0x1) << SCIF_GCCTRL_CEN_Pos) 856 #define SCIF_GCCTRL_DIVEN_Pos 1 /**< \brief (SCIF_GCCTRL) Divide Enable */ 857 #define SCIF_GCCTRL_DIVEN (_U_(0x1) << SCIF_GCCTRL_DIVEN_Pos) 858 #define SCIF_GCCTRL_OSCSEL_Pos 8 /**< \brief (SCIF_GCCTRL) Clock Select */ 859 #define SCIF_GCCTRL_OSCSEL_Msk (_U_(0x1F) << SCIF_GCCTRL_OSCSEL_Pos) 860 #define SCIF_GCCTRL_OSCSEL(value) (SCIF_GCCTRL_OSCSEL_Msk & ((value) << SCIF_GCCTRL_OSCSEL_Pos)) 861 #define SCIF_GCCTRL_DIV_Pos 16 /**< \brief (SCIF_GCCTRL) Division Factor */ 862 #define SCIF_GCCTRL_DIV_Msk (_U_(0xFFFF) << SCIF_GCCTRL_DIV_Pos) 863 #define SCIF_GCCTRL_DIV(value) (SCIF_GCCTRL_DIV_Msk & ((value) << SCIF_GCCTRL_DIV_Pos)) 864 #define SCIF_GCCTRL_MASK _U_(0xFFFF1F03) /**< \brief (SCIF_GCCTRL) MASK Register */ 865 866 /* -------- SCIF_RCFASTVERSION : (SCIF Offset: 0x3D8) (R/ 32) 4/8/12 MHz RC Oscillator Version Register -------- */ 867 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 868 typedef union { 869 struct { 870 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 871 uint32_t :4; /*!< bit: 12..15 Reserved */ 872 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 873 uint32_t :12; /*!< bit: 20..31 Reserved */ 874 } bit; /*!< Structure used for bit access */ 875 uint32_t reg; /*!< Type used for register access */ 876 } SCIF_RCFASTVERSION_Type; 877 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 878 879 #define SCIF_RCFASTVERSION_OFFSET 0x3D8 /**< \brief (SCIF_RCFASTVERSION offset) 4/8/12 MHz RC Oscillator Version Register */ 880 881 #define SCIF_RCFASTVERSION_VERSION_Pos 0 /**< \brief (SCIF_RCFASTVERSION) Version number */ 882 #define SCIF_RCFASTVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_RCFASTVERSION_VERSION_Pos) 883 #define SCIF_RCFASTVERSION_VERSION(value) (SCIF_RCFASTVERSION_VERSION_Msk & ((value) << SCIF_RCFASTVERSION_VERSION_Pos)) 884 #define SCIF_RCFASTVERSION_VARIANT_Pos 16 /**< \brief (SCIF_RCFASTVERSION) Variant number */ 885 #define SCIF_RCFASTVERSION_VARIANT_Msk (_U_(0xF) << SCIF_RCFASTVERSION_VARIANT_Pos) 886 #define SCIF_RCFASTVERSION_VARIANT(value) (SCIF_RCFASTVERSION_VARIANT_Msk & ((value) << SCIF_RCFASTVERSION_VARIANT_Pos)) 887 #define SCIF_RCFASTVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_RCFASTVERSION) MASK Register */ 888 889 /* -------- SCIF_GCLKPRESCVERSION : (SCIF Offset: 0x3DC) (R/ 32) Generic Clock Prescaler Version Register -------- */ 890 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 891 typedef union { 892 struct { 893 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 894 uint32_t :4; /*!< bit: 12..15 Reserved */ 895 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 896 uint32_t :12; /*!< bit: 20..31 Reserved */ 897 } bit; /*!< Structure used for bit access */ 898 uint32_t reg; /*!< Type used for register access */ 899 } SCIF_GCLKPRESCVERSION_Type; 900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 901 902 #define SCIF_GCLKPRESCVERSION_OFFSET 0x3DC /**< \brief (SCIF_GCLKPRESCVERSION offset) Generic Clock Prescaler Version Register */ 903 904 #define SCIF_GCLKPRESCVERSION_VERSION_Pos 0 /**< \brief (SCIF_GCLKPRESCVERSION) Version number */ 905 #define SCIF_GCLKPRESCVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_GCLKPRESCVERSION_VERSION_Pos) 906 #define SCIF_GCLKPRESCVERSION_VERSION(value) (SCIF_GCLKPRESCVERSION_VERSION_Msk & ((value) << SCIF_GCLKPRESCVERSION_VERSION_Pos)) 907 #define SCIF_GCLKPRESCVERSION_VARIANT_Pos 16 /**< \brief (SCIF_GCLKPRESCVERSION) Variant number */ 908 #define SCIF_GCLKPRESCVERSION_VARIANT_Msk (_U_(0xF) << SCIF_GCLKPRESCVERSION_VARIANT_Pos) 909 #define SCIF_GCLKPRESCVERSION_VARIANT(value) (SCIF_GCLKPRESCVERSION_VARIANT_Msk & ((value) << SCIF_GCLKPRESCVERSION_VARIANT_Pos)) 910 #define SCIF_GCLKPRESCVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_GCLKPRESCVERSION) MASK Register */ 911 912 /* -------- SCIF_PLLIFAVERSION : (SCIF Offset: 0x3E0) (R/ 32) PLL Version Register -------- */ 913 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 914 typedef union { 915 struct { 916 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 917 uint32_t :4; /*!< bit: 12..15 Reserved */ 918 uint32_t VARIANT:4; /*!< bit: 16..19 Variant nubmer */ 919 uint32_t :12; /*!< bit: 20..31 Reserved */ 920 } bit; /*!< Structure used for bit access */ 921 uint32_t reg; /*!< Type used for register access */ 922 } SCIF_PLLIFAVERSION_Type; 923 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 924 925 #define SCIF_PLLIFAVERSION_OFFSET 0x3E0 /**< \brief (SCIF_PLLIFAVERSION offset) PLL Version Register */ 926 927 #define SCIF_PLLIFAVERSION_VERSION_Pos 0 /**< \brief (SCIF_PLLIFAVERSION) Version number */ 928 #define SCIF_PLLIFAVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_PLLIFAVERSION_VERSION_Pos) 929 #define SCIF_PLLIFAVERSION_VERSION(value) (SCIF_PLLIFAVERSION_VERSION_Msk & ((value) << SCIF_PLLIFAVERSION_VERSION_Pos)) 930 #define SCIF_PLLIFAVERSION_VARIANT_Pos 16 /**< \brief (SCIF_PLLIFAVERSION) Variant nubmer */ 931 #define SCIF_PLLIFAVERSION_VARIANT_Msk (_U_(0xF) << SCIF_PLLIFAVERSION_VARIANT_Pos) 932 #define SCIF_PLLIFAVERSION_VARIANT(value) (SCIF_PLLIFAVERSION_VARIANT_Msk & ((value) << SCIF_PLLIFAVERSION_VARIANT_Pos)) 933 #define SCIF_PLLIFAVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_PLLIFAVERSION) MASK Register */ 934 935 /* -------- SCIF_OSCIFAVERSION : (SCIF Offset: 0x3E4) (R/ 32) Oscillator 0 Version Register -------- */ 936 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 937 typedef union { 938 struct { 939 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 940 uint32_t :4; /*!< bit: 12..15 Reserved */ 941 uint32_t VARIANT:4; /*!< bit: 16..19 Variant nubmer */ 942 uint32_t :12; /*!< bit: 20..31 Reserved */ 943 } bit; /*!< Structure used for bit access */ 944 uint32_t reg; /*!< Type used for register access */ 945 } SCIF_OSCIFAVERSION_Type; 946 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 947 948 #define SCIF_OSCIFAVERSION_OFFSET 0x3E4 /**< \brief (SCIF_OSCIFAVERSION offset) Oscillator 0 Version Register */ 949 950 #define SCIF_OSCIFAVERSION_VERSION_Pos 0 /**< \brief (SCIF_OSCIFAVERSION) Version number */ 951 #define SCIF_OSCIFAVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_OSCIFAVERSION_VERSION_Pos) 952 #define SCIF_OSCIFAVERSION_VERSION(value) (SCIF_OSCIFAVERSION_VERSION_Msk & ((value) << SCIF_OSCIFAVERSION_VERSION_Pos)) 953 #define SCIF_OSCIFAVERSION_VARIANT_Pos 16 /**< \brief (SCIF_OSCIFAVERSION) Variant nubmer */ 954 #define SCIF_OSCIFAVERSION_VARIANT_Msk (_U_(0xF) << SCIF_OSCIFAVERSION_VARIANT_Pos) 955 #define SCIF_OSCIFAVERSION_VARIANT(value) (SCIF_OSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_OSCIFAVERSION_VARIANT_Pos)) 956 #define SCIF_OSCIFAVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_OSCIFAVERSION) MASK Register */ 957 958 /* -------- SCIF_DFLLIFBVERSION : (SCIF Offset: 0x3E8) (R/ 32) DFLL Version Register -------- */ 959 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 960 typedef union { 961 struct { 962 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 963 uint32_t :4; /*!< bit: 12..15 Reserved */ 964 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 965 uint32_t :12; /*!< bit: 20..31 Reserved */ 966 } bit; /*!< Structure used for bit access */ 967 uint32_t reg; /*!< Type used for register access */ 968 } SCIF_DFLLIFBVERSION_Type; 969 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 970 971 #define SCIF_DFLLIFBVERSION_OFFSET 0x3E8 /**< \brief (SCIF_DFLLIFBVERSION offset) DFLL Version Register */ 972 973 #define SCIF_DFLLIFBVERSION_VERSION_Pos 0 /**< \brief (SCIF_DFLLIFBVERSION) Version number */ 974 #define SCIF_DFLLIFBVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_DFLLIFBVERSION_VERSION_Pos) 975 #define SCIF_DFLLIFBVERSION_VERSION(value) (SCIF_DFLLIFBVERSION_VERSION_Msk & ((value) << SCIF_DFLLIFBVERSION_VERSION_Pos)) 976 #define SCIF_DFLLIFBVERSION_VARIANT_Pos 16 /**< \brief (SCIF_DFLLIFBVERSION) Variant number */ 977 #define SCIF_DFLLIFBVERSION_VARIANT_Msk (_U_(0xF) << SCIF_DFLLIFBVERSION_VARIANT_Pos) 978 #define SCIF_DFLLIFBVERSION_VARIANT(value) (SCIF_DFLLIFBVERSION_VARIANT_Msk & ((value) << SCIF_DFLLIFBVERSION_VARIANT_Pos)) 979 #define SCIF_DFLLIFBVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_DFLLIFBVERSION) MASK Register */ 980 981 /* -------- SCIF_RCOSCIFAVERSION : (SCIF Offset: 0x3EC) (R/ 32) System RC Oscillator Version Register -------- */ 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 983 typedef union { 984 struct { 985 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 986 uint32_t :4; /*!< bit: 12..15 Reserved */ 987 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 988 uint32_t :12; /*!< bit: 20..31 Reserved */ 989 } bit; /*!< Structure used for bit access */ 990 uint32_t reg; /*!< Type used for register access */ 991 } SCIF_RCOSCIFAVERSION_Type; 992 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 993 994 #define SCIF_RCOSCIFAVERSION_OFFSET 0x3EC /**< \brief (SCIF_RCOSCIFAVERSION offset) System RC Oscillator Version Register */ 995 996 #define SCIF_RCOSCIFAVERSION_VERSION_Pos 0 /**< \brief (SCIF_RCOSCIFAVERSION) Version number */ 997 #define SCIF_RCOSCIFAVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_RCOSCIFAVERSION_VERSION_Pos) 998 #define SCIF_RCOSCIFAVERSION_VERSION(value) (SCIF_RCOSCIFAVERSION_VERSION_Msk & ((value) << SCIF_RCOSCIFAVERSION_VERSION_Pos)) 999 #define SCIF_RCOSCIFAVERSION_VARIANT_Pos 16 /**< \brief (SCIF_RCOSCIFAVERSION) Variant number */ 1000 #define SCIF_RCOSCIFAVERSION_VARIANT_Msk (_U_(0xF) << SCIF_RCOSCIFAVERSION_VARIANT_Pos) 1001 #define SCIF_RCOSCIFAVERSION_VARIANT(value) (SCIF_RCOSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_RCOSCIFAVERSION_VARIANT_Pos)) 1002 #define SCIF_RCOSCIFAVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_RCOSCIFAVERSION) MASK Register */ 1003 1004 /* -------- SCIF_FLOVERSION : (SCIF Offset: 0x3F0) (R/ 32) Frequency Locked Oscillator Version Register -------- */ 1005 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1006 typedef union { 1007 struct { 1008 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 1009 uint32_t :4; /*!< bit: 12..15 Reserved */ 1010 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 1011 uint32_t :12; /*!< bit: 20..31 Reserved */ 1012 } bit; /*!< Structure used for bit access */ 1013 uint32_t reg; /*!< Type used for register access */ 1014 } SCIF_FLOVERSION_Type; 1015 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1016 1017 #define SCIF_FLOVERSION_OFFSET 0x3F0 /**< \brief (SCIF_FLOVERSION offset) Frequency Locked Oscillator Version Register */ 1018 1019 #define SCIF_FLOVERSION_VERSION_Pos 0 /**< \brief (SCIF_FLOVERSION) Version number */ 1020 #define SCIF_FLOVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_FLOVERSION_VERSION_Pos) 1021 #define SCIF_FLOVERSION_VERSION(value) (SCIF_FLOVERSION_VERSION_Msk & ((value) << SCIF_FLOVERSION_VERSION_Pos)) 1022 #define SCIF_FLOVERSION_VARIANT_Pos 16 /**< \brief (SCIF_FLOVERSION) Variant number */ 1023 #define SCIF_FLOVERSION_VARIANT_Msk (_U_(0xF) << SCIF_FLOVERSION_VARIANT_Pos) 1024 #define SCIF_FLOVERSION_VARIANT(value) (SCIF_FLOVERSION_VARIANT_Msk & ((value) << SCIF_FLOVERSION_VARIANT_Pos)) 1025 #define SCIF_FLOVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_FLOVERSION) MASK Register */ 1026 1027 /* -------- SCIF_RC80MVERSION : (SCIF Offset: 0x3F4) (R/ 32) 80MHz RC Oscillator Version Register -------- */ 1028 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1029 typedef union { 1030 struct { 1031 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 1032 uint32_t :4; /*!< bit: 12..15 Reserved */ 1033 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 1034 uint32_t :12; /*!< bit: 20..31 Reserved */ 1035 } bit; /*!< Structure used for bit access */ 1036 uint32_t reg; /*!< Type used for register access */ 1037 } SCIF_RC80MVERSION_Type; 1038 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1039 1040 #define SCIF_RC80MVERSION_OFFSET 0x3F4 /**< \brief (SCIF_RC80MVERSION offset) 80MHz RC Oscillator Version Register */ 1041 1042 #define SCIF_RC80MVERSION_VERSION_Pos 0 /**< \brief (SCIF_RC80MVERSION) Version number */ 1043 #define SCIF_RC80MVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_RC80MVERSION_VERSION_Pos) 1044 #define SCIF_RC80MVERSION_VERSION(value) (SCIF_RC80MVERSION_VERSION_Msk & ((value) << SCIF_RC80MVERSION_VERSION_Pos)) 1045 #define SCIF_RC80MVERSION_VARIANT_Pos 16 /**< \brief (SCIF_RC80MVERSION) Variant number */ 1046 #define SCIF_RC80MVERSION_VARIANT_Msk (_U_(0xF) << SCIF_RC80MVERSION_VARIANT_Pos) 1047 #define SCIF_RC80MVERSION_VARIANT(value) (SCIF_RC80MVERSION_VARIANT_Msk & ((value) << SCIF_RC80MVERSION_VARIANT_Pos)) 1048 #define SCIF_RC80MVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_RC80MVERSION) MASK Register */ 1049 1050 /* -------- SCIF_GCLKIFVERSION : (SCIF Offset: 0x3F8) (R/ 32) Generic Clock Version Register -------- */ 1051 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1052 typedef union { 1053 struct { 1054 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 1055 uint32_t :4; /*!< bit: 12..15 Reserved */ 1056 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 1057 uint32_t :12; /*!< bit: 20..31 Reserved */ 1058 } bit; /*!< Structure used for bit access */ 1059 uint32_t reg; /*!< Type used for register access */ 1060 } SCIF_GCLKIFVERSION_Type; 1061 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1062 1063 #define SCIF_GCLKIFVERSION_OFFSET 0x3F8 /**< \brief (SCIF_GCLKIFVERSION offset) Generic Clock Version Register */ 1064 1065 #define SCIF_GCLKIFVERSION_VERSION_Pos 0 /**< \brief (SCIF_GCLKIFVERSION) Version number */ 1066 #define SCIF_GCLKIFVERSION_VERSION_Msk (_U_(0xFFF) << SCIF_GCLKIFVERSION_VERSION_Pos) 1067 #define SCIF_GCLKIFVERSION_VERSION(value) (SCIF_GCLKIFVERSION_VERSION_Msk & ((value) << SCIF_GCLKIFVERSION_VERSION_Pos)) 1068 #define SCIF_GCLKIFVERSION_VARIANT_Pos 16 /**< \brief (SCIF_GCLKIFVERSION) Variant number */ 1069 #define SCIF_GCLKIFVERSION_VARIANT_Msk (_U_(0xF) << SCIF_GCLKIFVERSION_VARIANT_Pos) 1070 #define SCIF_GCLKIFVERSION_VARIANT(value) (SCIF_GCLKIFVERSION_VARIANT_Msk & ((value) << SCIF_GCLKIFVERSION_VARIANT_Pos)) 1071 #define SCIF_GCLKIFVERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_GCLKIFVERSION) MASK Register */ 1072 1073 /* -------- SCIF_VERSION : (SCIF Offset: 0x3FC) (R/ 32) SCIF Version Register -------- */ 1074 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1075 typedef union { 1076 struct { 1077 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 1078 uint32_t :4; /*!< bit: 12..15 Reserved */ 1079 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 1080 uint32_t :12; /*!< bit: 20..31 Reserved */ 1081 } bit; /*!< Structure used for bit access */ 1082 uint32_t reg; /*!< Type used for register access */ 1083 } SCIF_VERSION_Type; 1084 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1085 1086 #define SCIF_VERSION_OFFSET 0x3FC /**< \brief (SCIF_VERSION offset) SCIF Version Register */ 1087 #define SCIF_VERSION_RESETVALUE _U_(0x00000130); /**< \brief (SCIF_VERSION reset_value) SCIF Version Register */ 1088 1089 #define SCIF_VERSION_VERSION_Pos 0 /**< \brief (SCIF_VERSION) Version number */ 1090 #define SCIF_VERSION_VERSION_Msk (_U_(0xFFF) << SCIF_VERSION_VERSION_Pos) 1091 #define SCIF_VERSION_VERSION(value) (SCIF_VERSION_VERSION_Msk & ((value) << SCIF_VERSION_VERSION_Pos)) 1092 #define SCIF_VERSION_VARIANT_Pos 16 /**< \brief (SCIF_VERSION) Variant number */ 1093 #define SCIF_VERSION_VARIANT_Msk (_U_(0xF) << SCIF_VERSION_VARIANT_Pos) 1094 #define SCIF_VERSION_VARIANT(value) (SCIF_VERSION_VARIANT_Msk & ((value) << SCIF_VERSION_VARIANT_Pos)) 1095 #define SCIF_VERSION_MASK _U_(0x000F0FFF) /**< \brief (SCIF_VERSION) MASK Register */ 1096 1097 /** \brief ScifGcctrl hardware registers */ 1098 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1099 typedef struct { 1100 __IO uint32_t GCCTRL; /**< \brief Offset: 0x000 (R/W 32) Generic Clock Control */ 1101 } ScifGcctrl; 1102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1103 1104 /** \brief ScifPll hardware registers */ 1105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1106 typedef struct { 1107 __IO uint32_t PLL; /**< \brief Offset: 0x000 (R/W 32) PLL0 Control Register */ 1108 } ScifPll; 1109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1110 1111 /** \brief SCIF hardware registers */ 1112 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1113 typedef struct { 1114 __O uint32_t IER; /**< \brief Offset: 0x000 ( /W 32) Interrupt Enable Register */ 1115 __O uint32_t IDR; /**< \brief Offset: 0x004 ( /W 32) Interrupt Disable Register */ 1116 __I uint32_t IMR; /**< \brief Offset: 0x008 (R/ 32) Interrupt Mask Register */ 1117 __I uint32_t ISR; /**< \brief Offset: 0x00C (R/ 32) Interrupt Status Register */ 1118 __O uint32_t ICR; /**< \brief Offset: 0x010 ( /W 32) Interrupt Clear Register */ 1119 __I uint32_t PCLKSR; /**< \brief Offset: 0x014 (R/ 32) Power and Clocks Status Register */ 1120 __O uint32_t UNLOCK; /**< \brief Offset: 0x018 ( /W 32) Unlock Register */ 1121 __IO uint32_t CSCR; /**< \brief Offset: 0x01C (R/W 32) Chip Specific Configuration Register */ 1122 __IO uint32_t OSCCTRL0; /**< \brief Offset: 0x020 (R/W 32) Oscillator Control Register */ 1123 uint32_t PLL[1]; /**< \brief Offset: 0x024 ScifPll groups */ 1124 __IO uint32_t DFLL0CONF; /**< \brief Offset: 0x028 (R/W 32) DFLL0 Config Register */ 1125 __IO uint32_t DFLL0VAL; /**< \brief Offset: 0x02C (R/W 32) DFLL Value Register */ 1126 __IO uint32_t DFLL0MUL; /**< \brief Offset: 0x030 (R/W 32) DFLL0 Multiplier Register */ 1127 __IO uint32_t DFLL0STEP; /**< \brief Offset: 0x034 (R/W 32) DFLL0 Step Register */ 1128 __IO uint32_t DFLL0SSG; /**< \brief Offset: 0x038 (R/W 32) DFLL0 Spread Spectrum Generator Control Register */ 1129 __I uint32_t DFLL0RATIO; /**< \brief Offset: 0x03C (R/ 32) DFLL0 Ratio Registe */ 1130 __O uint32_t DFLL0SYNC; /**< \brief Offset: 0x040 ( /W 32) DFLL0 Synchronization Register */ 1131 __IO uint32_t RCCR; /**< \brief Offset: 0x044 (R/W 32) System RC Oscillator Calibration Register */ 1132 __IO uint32_t RCFASTCFG; /**< \brief Offset: 0x048 (R/W 32) 4/8/12 MHz RC Oscillator Configuration Register */ 1133 __IO uint32_t RCFASTSR; /**< \brief Offset: 0x04C (R/W 32) 4/8/12 MHz RC Oscillator Status Register */ 1134 __IO uint32_t RC80MCR; /**< \brief Offset: 0x050 (R/W 32) 80 MHz RC Oscillator Register */ 1135 RoReg8 Reserved1[0x10]; 1136 __IO uint32_t HRPCR; /**< \brief Offset: 0x064 (R/W 32) High Resolution Prescaler Control Register */ 1137 __IO uint32_t FPCR; /**< \brief Offset: 0x068 (R/W 32) Fractional Prescaler Control Register */ 1138 __IO uint32_t FPMUL; /**< \brief Offset: 0x06C (R/W 32) Fractional Prescaler Multiplier Register */ 1139 __IO uint32_t FPDIV; /**< \brief Offset: 0x070 (R/W 32) Fractional Prescaler DIVIDER Register */ 1140 uint32_t GCCTRL[12]; /**< \brief Offset: 0x074 Generic Clock Control */ 1141 RoReg8 Reserved2[0x334]; 1142 __I uint32_t RCFASTVERSION; /**< \brief Offset: 0x3D8 (R/ 32) 4/8/12 MHz RC Oscillator Version Register */ 1143 __I uint32_t GCLKPRESCVERSION; /**< \brief Offset: 0x3DC (R/ 32) Generic Clock Prescaler Version Register */ 1144 __I uint32_t PLLIFAVERSION; /**< \brief Offset: 0x3E0 (R/ 32) PLL Version Register */ 1145 __I uint32_t OSCIFAVERSION; /**< \brief Offset: 0x3E4 (R/ 32) Oscillator 0 Version Register */ 1146 __I uint32_t DFLLIFBVERSION; /**< \brief Offset: 0x3E8 (R/ 32) DFLL Version Register */ 1147 __I uint32_t RCOSCIFAVERSION; /**< \brief Offset: 0x3EC (R/ 32) System RC Oscillator Version Register */ 1148 __I uint32_t FLOVERSION; /**< \brief Offset: 0x3F0 (R/ 32) Frequency Locked Oscillator Version Register */ 1149 __I uint32_t RC80MVERSION; /**< \brief Offset: 0x3F4 (R/ 32) 80MHz RC Oscillator Version Register */ 1150 __I uint32_t GCLKIFVERSION; /**< \brief Offset: 0x3F8 (R/ 32) Generic Clock Version Register */ 1151 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) SCIF Version Register */ 1152 } Scif; 1153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1154 1155 /*@}*/ 1156 1157 #endif /* _SAM4L_SCIF_COMPONENT_ */ 1158
