Searched refs:RwReg8 (Results 1 – 25 of 693) sorted by relevance
12345678910>>...28
311 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */312 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */323 #define REG_DMAC_CHCTRLB0 (*(RwReg8 *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B…324 #define REG_DMAC_CHPRILVL0 (*(RwReg8 *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority …325 #define REG_DMAC_CHEVCTRL0 (*(RwReg8 *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Con…326 #define REG_DMAC_CHINTENCLR0 (*(RwReg8 *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt…327 #define REG_DMAC_CHINTENSET0 (*(RwReg8 *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt…328 #define REG_DMAC_CHINTFLAG0 (*(RwReg8 *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt…329 #define REG_DMAC_CHSTATUS0 (*(RwReg8 *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */331 #define REG_DMAC_CHCTRLB1 (*(RwReg8 *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B…[all …]
179 #define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */181 #define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Servi…186 #define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Addres…193 #define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT …197 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPO…198 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDP…199 #define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDP…200 #define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT …204 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPO…205 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDP…[all …]
270 #define REG_EVSYS_CTRLA (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */272 #define REG_EVSYS_PRICTRL (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */278 #define REG_EVSYS_CHINTENCLR0 (*(RwReg8 *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrup…279 #define REG_EVSYS_CHINTENSET0 (*(RwReg8 *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrup…280 #define REG_EVSYS_CHINTFLAG0 (*(RwReg8 *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrup…283 #define REG_EVSYS_CHINTENCLR1 (*(RwReg8 *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrup…284 #define REG_EVSYS_CHINTENSET1 (*(RwReg8 *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrup…285 #define REG_EVSYS_CHINTFLAG1 (*(RwReg8 *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrup…288 #define REG_EVSYS_CHINTENCLR2 (*(RwReg8 *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrup…289 #define REG_EVSYS_CHINTENSET2 (*(RwReg8 *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrup…[all …]
178 #define REG_USB_CTRLA (*(RwReg8 *)0x41005000UL) /**< \brief (USB) Control A */180 #define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003UL) /**< \brief (USB) USB Quality Of Servi…185 #define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) DEVICE Device Addres…192 #define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) DEVICE_ENDPOINT …196 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) DEVICE_ENDPO…197 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) DEVICE_ENDP…198 #define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) DEVICE_ENDP…199 #define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) DEVICE_ENDPOINT …203 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) DEVICE_ENDPO…204 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) DEVICE_ENDP…[all …]
80 #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Interrupt E…81 #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CM Interrupt E…82 #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Interrupt F…86 #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CM Data */87 #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) I2CM Debug Contr…90 #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CS Interrupt E…91 #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CS Interrupt E…92 #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Interrupt F…96 #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CS Data */99 #define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Baud Rate */[all …]
80 #define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Interrupt E…81 #define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CM Interrupt E…82 #define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Interrupt F…86 #define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CM Data */87 #define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) I2CM Debug Contr…90 #define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CS Interrupt E…91 #define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CS Interrupt E…92 #define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Interrupt F…96 #define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CS Data */99 #define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Baud Rate */[all …]
80 #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt E…81 #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt E…82 #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt F…86 #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */87 #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Contr…90 #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt E…91 #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt E…92 #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt F…96 #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */99 #define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */[all …]
75 #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) I2CM Debug Contr…77 #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Interrupt E…78 #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CM Interrupt E…79 #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CM Interrupt F…81 #define REG_SERCOM0_I2CM_ADDR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Address */82 #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Data */85 #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CS Interrupt E…86 #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CS Interrupt E…87 #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CS Interrupt F…90 #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Data */[all …]
75 #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C08UL) /**< \brief (SERCOM1) I2CM Debug Contr…77 #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Interrupt E…78 #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) I2CM Interrupt E…79 #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) I2CM Interrupt F…81 #define REG_SERCOM1_I2CM_ADDR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Address */82 #define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Data */85 #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) I2CS Interrupt E…86 #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) I2CS Interrupt E…87 #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) I2CS Interrupt F…90 #define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Data */[all …]
75 #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001408UL) /**< \brief (SERCOM3) I2CM Debug Contr…77 #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Interrupt E…78 #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) I2CM Interrupt E…79 #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) I2CM Interrupt F…81 #define REG_SERCOM3_I2CM_ADDR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Address */82 #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Data */85 #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) I2CS Interrupt E…86 #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) I2CS Interrupt E…87 #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) I2CS Interrupt F…90 #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Data */[all …]
75 #define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001808UL) /**< \brief (SERCOM4) I2CM Debug Contr…77 #define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Interrupt E…78 #define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) I2CM Interrupt E…79 #define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) I2CM Interrupt F…81 #define REG_SERCOM4_I2CM_ADDR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Address */82 #define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Data */85 #define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) I2CS Interrupt E…86 #define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) I2CS Interrupt E…87 #define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) I2CS Interrupt F…90 #define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Data */[all …]
75 #define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001008UL) /**< \brief (SERCOM2) I2CM Debug Contr…77 #define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Interrupt E…78 #define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) I2CM Interrupt E…79 #define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) I2CM Interrupt F…81 #define REG_SERCOM2_I2CM_ADDR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Address */82 #define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Data */85 #define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) I2CS Interrupt E…86 #define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) I2CS Interrupt E…87 #define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) I2CS Interrupt F…90 #define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Data */[all …]
75 #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C08UL) /**< \brief (SERCOM5) I2CM Debug Contr…77 #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Interrupt E…78 #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) I2CM Interrupt E…79 #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) I2CM Interrupt F…81 #define REG_SERCOM5_I2CM_ADDR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Address */82 #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Data */85 #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) I2CS Interrupt E…86 #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) I2CS Interrupt E…87 #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) I2CS Interrupt F…90 #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Data */[all …]
