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Searched refs:REG_TC2_INTENSET (Results 1 – 12 of 12) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd20/instance/
Dtc2.h43 #define REG_TC2_INTENSET (0x4200280D) /**< \brief (TC2) Interrupt Enable Set */ macro
65 #define REG_TC2_INTENSET (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dtc2.h40 #define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */ macro
70 #define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set… macro