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Searched refs:REG_TC1_RB0 (Results 1 – 8 of 8) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4l/instance/
Dtc1.h39 #define REG_TC1_RB0 (0x40014018) /**< \brief (TC1) Register B Channel 0 */ macro
78 #define REG_TC1_RB0 (*(RwReg *)0x40014018UL) /**< \brief (TC1) Register B Channel 0… macro
/hal_atmel-latest/asf/sam/include/sam4s/instance/
Dtc1.h40 #define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ macro
82 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ macro
/hal_atmel-latest/asf/sam/include/sam3x/instance/
Dtc1.h40 #define REG_TC1_RB0 (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ macro
82 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ macro
/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dtc1.h41 #define REG_TC1_RB0 (0x40094018U) /**< \brief (TC1) Register B (channel = 0) */ macro
107 #define REG_TC1_RB0 (*(RwReg*)0x40094018U) /**< \brief (TC1) Register B (channel = 0) */ macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dtc1.h43 #define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ macro
93 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) … macro
/hal_atmel-latest/asf/sam/include/samv71/instance/
Dtc1.h43 #define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ macro
94 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) … macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dtc1.h43 #define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ macro
93 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) … macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dtc1.h43 #define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ macro
93 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) … macro