Searched refs:REG_TC1_QIMR (Results 1 – 7 of 7) sorted by relevance
72 …#define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Registe… macro114 …#define REG_TC1_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Registe… macro
72 …#define REG_TC1_QIMR (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Registe… macro114 …#define REG_TC1_QIMR (*(__I uint32_t*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Registe… macro
78 #define REG_TC1_QIMR (0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ macro144 #define REG_TC1_QIMR (*(RoReg*)0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ macro
80 #define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */ macro130 #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Regis… macro
80 #define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */ macro131 #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Regis… macro
