Home
last modified time | relevance | path

Searched refs:REG_TC1_INTENSET (Results 1 – 12 of 12) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd20/instance/
Dtc1.h43 #define REG_TC1_INTENSET (0x4200240D) /**< \brief (TC1) Interrupt Enable Set */ macro
65 #define REG_TC1_INTENSET (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dtc1.h40 #define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */ macro
70 #define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set… macro