Searched refs:REG_TC0_IMR1 (Results 1 – 8 of 8) sorted by relevance
55 #define REG_TC0_IMR1 (0x4001006C) /**< \brief (TC0) Interrupt Mask Register Channel 1… macro94 #define REG_TC0_IMR1 (*(RoReg *)0x4001006CUL) /**< \brief (TC0) Interrupt Mask Regis… macro
56 …#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (ch… macro98 …#define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (ch… macro
56 …#define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (ch… macro98 …#define REG_TC0_IMR1 (*(__I uint32_t*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (ch… macro
59 #define REG_TC0_IMR1 (0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1… macro125 #define REG_TC0_IMR1 (*(RoReg*)0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1… macro
61 #define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ macro111 #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (… macro
61 #define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ macro112 #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (… macro
