Searched refs:REG_SPI0_IMR (Results 1 – 5 of 5) sorted by relevance
42 #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ macro54 #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ macro
44 #define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */ macro62 #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register … macro
44 #define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */ macro63 #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register … macro
