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Searched refs:REG_SERCOM4_SPI_INTENSET (Results 1 – 13 of 13) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd20/instance/
Dsercom4.h58 #define REG_SERCOM4_SPI_INTENSET (0x4200180D) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
96 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samr21/instance/
Dsercom4.h58 #define REG_SERCOM4_SPI_INTENSET (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
101 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samd21/instance/
Dsercom4.h58 #define REG_SERCOM4_SPI_INTENSET (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
101 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
102 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
102 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
103 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
103 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
102 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dsercom4.h59 #define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
103 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dsercom4.h63 #define REG_SERCOM4_SPI_INTENSET (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
114 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dsercom4.h63 #define REG_SERCOM4_SPI_INTENSET (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
114 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dsercom4.h63 #define REG_SERCOM4_SPI_INTENSET (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
114 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dsercom4.h63 #define REG_SERCOM4_SPI_INTENSET (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ macro
114 #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt En… macro