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Searched refs:REG_CMCC_SR (Results 1 – 6 of 6) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dcmcc.h38 #define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */ macro
49 #define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */ macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dcmcc.h38 #define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */ macro
50 #define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Regist… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dcmcc.h38 #define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */ macro
50 #define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Regist… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dcmcc.h38 #define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */ macro
50 #define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Regist… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dcmcc.h38 #define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */ macro
50 #define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Regist… macro
/hal_atmel-latest/asf/sam/include/sam4s/instance/
Dcmcc.h38 …#define REG_CMCC_SR (0x4007C00CU) /**< \brief (CMCC) Cache Controller Status … macro
49 …#define REG_CMCC_SR (*(__I uint32_t*)0x4007C00CU) /**< \brief (CMCC) Cache Controller Status … macro