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Searched refs:REG_CMCC_MEN (Results 1 – 6 of 6) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dcmcc.h42 #define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
53 #define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dcmcc.h43 #define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
55 #define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enabl… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dcmcc.h43 #define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
55 #define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enabl… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dcmcc.h43 #define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
55 #define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enabl… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dcmcc.h43 #define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */ macro
55 #define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enabl… macro
/hal_atmel-latest/asf/sam/include/sam4s/instance/
Dcmcc.h42 …#define REG_CMCC_MEN (0x4007C02CU) /**< \brief (CMCC) Cache Controller Monitor… macro
53 …#define REG_CMCC_MEN (*(__IO uint32_t*)0x4007C02CU) /**< \brief (CMCC) Cache Controller Monitor… macro