Home
last modified time | relevance | path

Searched refs:REG_CMCC_MCTRL (Results 1 – 6 of 6) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dcmcc.h43 #define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ macro
54 #define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dcmcc.h44 #define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */ macro
56 #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Contr… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dcmcc.h44 #define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */ macro
56 #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Contr… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dcmcc.h44 #define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */ macro
56 #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Contr… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dcmcc.h44 #define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */ macro
56 #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Contr… macro
/hal_atmel-latest/asf/sam/include/sam4s/instance/
Dcmcc.h43 …#define REG_CMCC_MCTRL (0x4007C030U) /**< \brief (CMCC) Cache Controller Monitor… macro
54 …#define REG_CMCC_MCTRL (*(__O uint32_t*)0x4007C030U) /**< \brief (CMCC) Cache Controller Monitor… macro