Home
last modified time | relevance | path

Searched refs:REG_CMCC_CTRL (Results 1 – 6 of 6) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dcmcc.h37 #define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */ macro
48 #define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */ macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dcmcc.h37 #define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */ macro
49 #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Regis… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dcmcc.h37 #define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */ macro
49 #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Regis… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dcmcc.h37 #define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */ macro
49 #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Regis… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dcmcc.h37 #define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */ macro
49 #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Regis… macro
/hal_atmel-latest/asf/sam/include/sam4s/instance/
Dcmcc.h37 …#define REG_CMCC_CTRL (0x4007C008U) /**< \brief (CMCC) Cache Controller Control… macro
48 …#define REG_CMCC_CTRL (*(__O uint32_t*)0x4007C008U) /**< \brief (CMCC) Cache Controller Control… macro