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Searched refs:REG_CCL_SEQCTRL1 (Results 1 – 11 of 11) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x43001C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x43001C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dccl.h37 #define REG_CCL_SEQCTRL1 (0x43001C05) /**< \brief (CCL) SEQ Control x 1 */ macro
45 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05UL) /**< \brief (CCL) SEQ Control x 1 */ macro