Searched refs:REG_AFEC1_SEQ2R (Results 1 – 5 of 5) sorted by relevance
39 #define REG_AFEC1_SEQ2R (0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */ macro72 #define REG_AFEC1_SEQ2R (*(RwReg*)0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */ macro
41 #define REG_AFEC1_SEQ2R (0x40064010) /**< (AFEC1) AFEC Channel Sequence 2 Register */ macro74 #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< (AFEC1) AFEC Channel Sequence 2… macro
41 #define REG_AFEC1_SEQ2R (0x40064010) /**< (AFEC1) AFEC Channel Sequence 2 Register */ macro73 #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< (AFEC1) AFEC Channel Sequence 2… macro
