Searched refs:REG_AFEC1_IMR (Results 1 – 5 of 5) sorted by relevance
46 #define REG_AFEC1_IMR (0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */ macro79 #define REG_AFEC1_IMR (*(RoReg*)0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */ macro
48 #define REG_AFEC1_IMR (0x4006402C) /**< (AFEC1) AFEC Interrupt Mask Register */ macro81 #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< (AFEC1) AFEC Interrupt Mask Reg… macro
48 #define REG_AFEC1_IMR (0x4006402C) /**< (AFEC1) AFEC Interrupt Mask Register */ macro80 #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< (AFEC1) AFEC Interrupt Mask Reg… macro
