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Searched refs:REG_AFEC1_CHDR (Results 1 – 5 of 5) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/instance/
Dafec1.h41 #define REG_AFEC1_CHDR (0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */ macro
74 #define REG_AFEC1_CHDR (*(WoReg*)0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */ macro
/hal_atmel-latest/asf/sam/include/samv71/instance/
Dafec1.h43 #define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */ macro
76 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Re… macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dafec1.h43 #define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */ macro
75 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Re… macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dafec1.h43 #define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */ macro
75 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Re… macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dafec1.h43 #define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */ macro
75 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Re… macro