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Searched refs:REG_ADC1_DSEQSTAT (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam0/include/same53/instance/
Dadc1.h55 #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */ macro
80 #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Stat… macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dadc1.h55 #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */ macro
80 #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Stat… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dadc1.h55 #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */ macro
80 #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Stat… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dadc1.h55 #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */ macro
80 #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Stat… macro