Home
last modified time | relevance | path

Searched refs:MUX_PB15H_GCLK_IO1 (Results 1 – 25 of 43) sorted by relevance

12

/hal_atmel-latest/asf/sam0/include/samr21/pio/
Dsamr21e16a.h116 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
117 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21e17a.h116 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
117 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21e18a.h116 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
117 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21e19a.h132 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
133 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21g16a.h144 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
145 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21g17a.h144 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
145 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr21g18a.h144 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
145 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
/hal_atmel-latest/asf/sam0/include/samr34/pio/
Dsamr34j16b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr34j17b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr34j18b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
/hal_atmel-latest/asf/sam0/include/samc20/pio/
Dsamc20j17au.h212 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
213 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamc20j18au.h212 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
213 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamc20j15a.h228 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
229 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
/hal_atmel-latest/asf/sam0/include/samd20/pio/
Dsamd20j14.h163 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd20j15.h163 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd20j16.h163 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd20j17.h163 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd20j18.h163 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
/hal_atmel-latest/asf/sam0/include/samr35/pio/
Dsamr35j16b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr35j17b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamr35j18b.h169 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
/hal_atmel-latest/asf/sam0/include/samd21/pio/
Dsamd21j15a.h162 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
163 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd21j18a.h162 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
163 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd21j16a.h162 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
163 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
Dsamd21j17a.h162 #define MUX_PB15H_GCLK_IO1 _L_(7) macro
163 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)

12