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Searched refs:MUX_PA07O_ADC0_DRV5 (Results 1 – 23 of 23) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samd51/pio/
Dsamd51g18a.h1091 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1092 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51g19a.h1091 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1092 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51j18a.h1421 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1422 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51j19a.h1421 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1422 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51j20a.h1421 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1422 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51n19a.h2047 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2048 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51n20a.h2047 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2048 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51p19a.h2329 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2330 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsamd51p20a.h2329 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2330 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
/hal_atmel-latest/asf/sam0/include/same51/pio/
Dsame51j19a.h1455 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1456 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame51j20a.h1455 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1456 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame51j18a.h1455 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1456 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame51n19a.h2081 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2082 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame51n20a.h2081 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2082 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
/hal_atmel-latest/asf/sam0/include/same53/pio/
Dsame53j18a.h1474 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1475 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame53j19a.h1474 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1475 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame53j20a.h1474 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
1475 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame53n19a.h2136 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2137 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame53n20a.h2136 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2137 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
/hal_atmel-latest/asf/sam0/include/same54/pio/
Dsame54n19a.h2170 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2171 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame54n20a.h2170 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2171 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame54p20a.h2460 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2461 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
Dsame54p19a.h2460 #define MUX_PA07O_ADC0_DRV5 _L_(14) macro
2461 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)