1 /** 2 * \file 3 * 4 * \brief Component description for IISC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_IISC_COMPONENT_ 30 #define _SAM4L_IISC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR IISC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_IISC Inter-IC Sound (I2S) Controller */ 36 /*@{*/ 37 38 #define IISC_I7560 39 #define REV_IISC 0x100 40 41 /* -------- IISC_CR : (IISC Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t RXEN:1; /*!< bit: 0 Receive Enable */ 46 uint32_t RXDIS:1; /*!< bit: 1 Receive Disable */ 47 uint32_t CKEN:1; /*!< bit: 2 Clocks Enable */ 48 uint32_t CKDIS:1; /*!< bit: 3 Clocks Disable */ 49 uint32_t TXEN:1; /*!< bit: 4 Transmit Enable */ 50 uint32_t TXDIS:1; /*!< bit: 5 Transmit Disable */ 51 uint32_t :1; /*!< bit: 6 Reserved */ 52 uint32_t SWRST:1; /*!< bit: 7 Software Reset */ 53 uint32_t :24; /*!< bit: 8..31 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint32_t reg; /*!< Type used for register access */ 56 } IISC_CR_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define IISC_CR_OFFSET 0x00 /**< \brief (IISC_CR offset) Control Register */ 60 61 #define IISC_CR_RXEN_Pos 0 /**< \brief (IISC_CR) Receive Enable */ 62 #define IISC_CR_RXEN (_U_(0x1) << IISC_CR_RXEN_Pos) 63 #define IISC_CR_RXEN_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 64 #define IISC_CR_RXEN_ON_Val _U_(0x1) /**< \brief (IISC_CR) Enables Data Receive if RXDIS is not set */ 65 #define IISC_CR_RXEN_OFF (IISC_CR_RXEN_OFF_Val << IISC_CR_RXEN_Pos) 66 #define IISC_CR_RXEN_ON (IISC_CR_RXEN_ON_Val << IISC_CR_RXEN_Pos) 67 #define IISC_CR_RXDIS_Pos 1 /**< \brief (IISC_CR) Receive Disable */ 68 #define IISC_CR_RXDIS (_U_(0x1) << IISC_CR_RXDIS_Pos) 69 #define IISC_CR_RXDIS_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 70 #define IISC_CR_RXDIS_ON_Val _U_(0x1) /**< \brief (IISC_CR) Disables Data Receive */ 71 #define IISC_CR_RXDIS_OFF (IISC_CR_RXDIS_OFF_Val << IISC_CR_RXDIS_Pos) 72 #define IISC_CR_RXDIS_ON (IISC_CR_RXDIS_ON_Val << IISC_CR_RXDIS_Pos) 73 #define IISC_CR_CKEN_Pos 2 /**< \brief (IISC_CR) Clocks Enable */ 74 #define IISC_CR_CKEN (_U_(0x1) << IISC_CR_CKEN_Pos) 75 #define IISC_CR_CKEN_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 76 #define IISC_CR_CKEN_ON_Val _U_(0x1) /**< \brief (IISC_CR) Enables clocks if CKDIS is not set */ 77 #define IISC_CR_CKEN_OFF (IISC_CR_CKEN_OFF_Val << IISC_CR_CKEN_Pos) 78 #define IISC_CR_CKEN_ON (IISC_CR_CKEN_ON_Val << IISC_CR_CKEN_Pos) 79 #define IISC_CR_CKDIS_Pos 3 /**< \brief (IISC_CR) Clocks Disable */ 80 #define IISC_CR_CKDIS (_U_(0x1) << IISC_CR_CKDIS_Pos) 81 #define IISC_CR_CKDIS_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 82 #define IISC_CR_CKDIS_ON_Val _U_(0x1) /**< \brief (IISC_CR) Disables clocks */ 83 #define IISC_CR_CKDIS_OFF (IISC_CR_CKDIS_OFF_Val << IISC_CR_CKDIS_Pos) 84 #define IISC_CR_CKDIS_ON (IISC_CR_CKDIS_ON_Val << IISC_CR_CKDIS_Pos) 85 #define IISC_CR_TXEN_Pos 4 /**< \brief (IISC_CR) Transmit Enable */ 86 #define IISC_CR_TXEN (_U_(0x1) << IISC_CR_TXEN_Pos) 87 #define IISC_CR_TXEN_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 88 #define IISC_CR_TXEN_ON_Val _U_(0x1) /**< \brief (IISC_CR) Enables Data Transmit if TXDIS is not set */ 89 #define IISC_CR_TXEN_OFF (IISC_CR_TXEN_OFF_Val << IISC_CR_TXEN_Pos) 90 #define IISC_CR_TXEN_ON (IISC_CR_TXEN_ON_Val << IISC_CR_TXEN_Pos) 91 #define IISC_CR_TXDIS_Pos 5 /**< \brief (IISC_CR) Transmit Disable */ 92 #define IISC_CR_TXDIS (_U_(0x1) << IISC_CR_TXDIS_Pos) 93 #define IISC_CR_TXDIS_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 94 #define IISC_CR_TXDIS_ON_Val _U_(0x1) /**< \brief (IISC_CR) Disables Data Transmit */ 95 #define IISC_CR_TXDIS_OFF (IISC_CR_TXDIS_OFF_Val << IISC_CR_TXDIS_Pos) 96 #define IISC_CR_TXDIS_ON (IISC_CR_TXDIS_ON_Val << IISC_CR_TXDIS_Pos) 97 #define IISC_CR_SWRST_Pos 7 /**< \brief (IISC_CR) Software Reset */ 98 #define IISC_CR_SWRST (_U_(0x1) << IISC_CR_SWRST_Pos) 99 #define IISC_CR_SWRST_OFF_Val _U_(0x0) /**< \brief (IISC_CR) No effect */ 100 #define IISC_CR_SWRST_ON_Val _U_(0x1) /**< \brief (IISC_CR) Performs a software reset. Has priority on any other bit in CR */ 101 #define IISC_CR_SWRST_OFF (IISC_CR_SWRST_OFF_Val << IISC_CR_SWRST_Pos) 102 #define IISC_CR_SWRST_ON (IISC_CR_SWRST_ON_Val << IISC_CR_SWRST_Pos) 103 #define IISC_CR_MASK _U_(0x000000BF) /**< \brief (IISC_CR) MASK Register */ 104 105 /* -------- IISC_MR : (IISC Offset: 0x04) (R/W 32) Mode Register -------- */ 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 107 typedef union { 108 struct { 109 uint32_t MODE:1; /*!< bit: 0 Master/Slave/Controller Mode */ 110 uint32_t :1; /*!< bit: 1 Reserved */ 111 uint32_t DATALENGTH:3; /*!< bit: 2.. 4 Data Word Length */ 112 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 113 uint32_t RXMONO:1; /*!< bit: 8 Receiver Mono */ 114 uint32_t RXDMA:1; /*!< bit: 9 Single or Multiple DMA Channels for Receiver */ 115 uint32_t RXLOOP:1; /*!< bit: 10 Loop-back Test Mode */ 116 uint32_t :1; /*!< bit: 11 Reserved */ 117 uint32_t TXMONO:1; /*!< bit: 12 Transmitter Mono */ 118 uint32_t TXDMA:1; /*!< bit: 13 Single or Multiple DMA Channels for Transmitter */ 119 uint32_t TXSAME:1; /*!< bit: 14 Transmit Data when Underrun */ 120 uint32_t :9; /*!< bit: 15..23 Reserved */ 121 uint32_t IMCKFS:6; /*!< bit: 24..29 Master Clock to fs Ratio */ 122 uint32_t IMCKMODE:1; /*!< bit: 30 Master Clock Mode */ 123 uint32_t IWS24:1; /*!< bit: 31 IWS Data Slot Width */ 124 } bit; /*!< Structure used for bit access */ 125 uint32_t reg; /*!< Type used for register access */ 126 } IISC_MR_Type; 127 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 #define IISC_MR_OFFSET 0x04 /**< \brief (IISC_MR offset) Mode Register */ 130 #define IISC_MR_RESETVALUE _U_(0x00000000); /**< \brief (IISC_MR reset_value) Mode Register */ 131 132 #define IISC_MR_MODE_Pos 0 /**< \brief (IISC_MR) Master/Slave/Controller Mode */ 133 #define IISC_MR_MODE (_U_(0x1) << IISC_MR_MODE_Pos) 134 #define IISC_MR_MODE_SLAVE_Val _U_(0x0) /**< \brief (IISC_MR) Slave mode (only serial data handled, clocks received from external master or controller) */ 135 #define IISC_MR_MODE_MASTER_Val _U_(0x1) /**< \brief (IISC_MR) Master mode (clocks generated and output by IISC, serial data handled if CR.RXEN and/or CR.TXEN written to 1) */ 136 #define IISC_MR_MODE_SLAVE (IISC_MR_MODE_SLAVE_Val << IISC_MR_MODE_Pos) 137 #define IISC_MR_MODE_MASTER (IISC_MR_MODE_MASTER_Val << IISC_MR_MODE_Pos) 138 #define IISC_MR_DATALENGTH_Pos 2 /**< \brief (IISC_MR) Data Word Length */ 139 #define IISC_MR_DATALENGTH_Msk (_U_(0x7) << IISC_MR_DATALENGTH_Pos) 140 #define IISC_MR_DATALENGTH(value) (IISC_MR_DATALENGTH_Msk & ((value) << IISC_MR_DATALENGTH_Pos)) 141 #define IISC_MR_DATALENGTH_32_Val _U_(0x0) /**< \brief (IISC_MR) 32 bits */ 142 #define IISC_MR_DATALENGTH_24_Val _U_(0x1) /**< \brief (IISC_MR) 24 bits */ 143 #define IISC_MR_DATALENGTH_20_Val _U_(0x2) /**< \brief (IISC_MR) 20 bits */ 144 #define IISC_MR_DATALENGTH_18_Val _U_(0x3) /**< \brief (IISC_MR) 18 bits */ 145 #define IISC_MR_DATALENGTH_16_Val _U_(0x4) /**< \brief (IISC_MR) 16 bits */ 146 #define IISC_MR_DATALENGTH_16C_Val _U_(0x5) /**< \brief (IISC_MR) 16 bits compact stereo */ 147 #define IISC_MR_DATALENGTH_8_Val _U_(0x6) /**< \brief (IISC_MR) 8 bits */ 148 #define IISC_MR_DATALENGTH_8C_Val _U_(0x7) /**< \brief (IISC_MR) 8 bits compact stereo */ 149 #define IISC_MR_DATALENGTH_32 (IISC_MR_DATALENGTH_32_Val << IISC_MR_DATALENGTH_Pos) 150 #define IISC_MR_DATALENGTH_24 (IISC_MR_DATALENGTH_24_Val << IISC_MR_DATALENGTH_Pos) 151 #define IISC_MR_DATALENGTH_20 (IISC_MR_DATALENGTH_20_Val << IISC_MR_DATALENGTH_Pos) 152 #define IISC_MR_DATALENGTH_18 (IISC_MR_DATALENGTH_18_Val << IISC_MR_DATALENGTH_Pos) 153 #define IISC_MR_DATALENGTH_16 (IISC_MR_DATALENGTH_16_Val << IISC_MR_DATALENGTH_Pos) 154 #define IISC_MR_DATALENGTH_16C (IISC_MR_DATALENGTH_16C_Val << IISC_MR_DATALENGTH_Pos) 155 #define IISC_MR_DATALENGTH_8 (IISC_MR_DATALENGTH_8_Val << IISC_MR_DATALENGTH_Pos) 156 #define IISC_MR_DATALENGTH_8C (IISC_MR_DATALENGTH_8C_Val << IISC_MR_DATALENGTH_Pos) 157 #define IISC_MR_RXMONO_Pos 8 /**< \brief (IISC_MR) Receiver Mono */ 158 #define IISC_MR_RXMONO (_U_(0x1) << IISC_MR_RXMONO_Pos) 159 #define IISC_MR_RXMONO_STEREO_Val _U_(0x0) /**< \brief (IISC_MR) Normal mode */ 160 #define IISC_MR_RXMONO_MONO_Val _U_(0x1) /**< \brief (IISC_MR) Left channel data is duplicated to right channel */ 161 #define IISC_MR_RXMONO_STEREO (IISC_MR_RXMONO_STEREO_Val << IISC_MR_RXMONO_Pos) 162 #define IISC_MR_RXMONO_MONO (IISC_MR_RXMONO_MONO_Val << IISC_MR_RXMONO_Pos) 163 #define IISC_MR_RXDMA_Pos 9 /**< \brief (IISC_MR) Single or Multiple DMA Channels for Receiver */ 164 #define IISC_MR_RXDMA (_U_(0x1) << IISC_MR_RXDMA_Pos) 165 #define IISC_MR_RXDMA_SINGLE_Val _U_(0x0) /**< \brief (IISC_MR) Single DMA channel */ 166 #define IISC_MR_RXDMA_MULTIPLE_Val _U_(0x1) /**< \brief (IISC_MR) One DMA channel per data channel */ 167 #define IISC_MR_RXDMA_SINGLE (IISC_MR_RXDMA_SINGLE_Val << IISC_MR_RXDMA_Pos) 168 #define IISC_MR_RXDMA_MULTIPLE (IISC_MR_RXDMA_MULTIPLE_Val << IISC_MR_RXDMA_Pos) 169 #define IISC_MR_RXLOOP_Pos 10 /**< \brief (IISC_MR) Loop-back Test Mode */ 170 #define IISC_MR_RXLOOP (_U_(0x1) << IISC_MR_RXLOOP_Pos) 171 #define IISC_MR_RXLOOP_OFF_Val _U_(0x0) /**< \brief (IISC_MR) Normal mode */ 172 #define IISC_MR_RXLOOP_ON_Val _U_(0x1) /**< \brief (IISC_MR) ISDO internally connected to ISDI */ 173 #define IISC_MR_RXLOOP_OFF (IISC_MR_RXLOOP_OFF_Val << IISC_MR_RXLOOP_Pos) 174 #define IISC_MR_RXLOOP_ON (IISC_MR_RXLOOP_ON_Val << IISC_MR_RXLOOP_Pos) 175 #define IISC_MR_TXMONO_Pos 12 /**< \brief (IISC_MR) Transmitter Mono */ 176 #define IISC_MR_TXMONO (_U_(0x1) << IISC_MR_TXMONO_Pos) 177 #define IISC_MR_TXMONO_STEREO_Val _U_(0x0) /**< \brief (IISC_MR) Normal mode */ 178 #define IISC_MR_TXMONO_MONO_Val _U_(0x1) /**< \brief (IISC_MR) Left channel data is duplicated to right channel */ 179 #define IISC_MR_TXMONO_STEREO (IISC_MR_TXMONO_STEREO_Val << IISC_MR_TXMONO_Pos) 180 #define IISC_MR_TXMONO_MONO (IISC_MR_TXMONO_MONO_Val << IISC_MR_TXMONO_Pos) 181 #define IISC_MR_TXDMA_Pos 13 /**< \brief (IISC_MR) Single or Multiple DMA Channels for Transmitter */ 182 #define IISC_MR_TXDMA (_U_(0x1) << IISC_MR_TXDMA_Pos) 183 #define IISC_MR_TXDMA_SINGLE_Val _U_(0x0) /**< \brief (IISC_MR) Single DMA channel */ 184 #define IISC_MR_TXDMA_MULTIPLE_Val _U_(0x1) /**< \brief (IISC_MR) One DMA channel per data channel */ 185 #define IISC_MR_TXDMA_SINGLE (IISC_MR_TXDMA_SINGLE_Val << IISC_MR_TXDMA_Pos) 186 #define IISC_MR_TXDMA_MULTIPLE (IISC_MR_TXDMA_MULTIPLE_Val << IISC_MR_TXDMA_Pos) 187 #define IISC_MR_TXSAME_Pos 14 /**< \brief (IISC_MR) Transmit Data when Underrun */ 188 #define IISC_MR_TXSAME (_U_(0x1) << IISC_MR_TXSAME_Pos) 189 #define IISC_MR_TXSAME_ZERO_Val _U_(0x0) /**< \brief (IISC_MR) Zero data transmitted in case of underrun */ 190 #define IISC_MR_TXSAME_SAME_Val _U_(0x1) /**< \brief (IISC_MR) Last data transmitted in case of underrun */ 191 #define IISC_MR_TXSAME_ZERO (IISC_MR_TXSAME_ZERO_Val << IISC_MR_TXSAME_Pos) 192 #define IISC_MR_TXSAME_SAME (IISC_MR_TXSAME_SAME_Val << IISC_MR_TXSAME_Pos) 193 #define IISC_MR_IMCKFS_Pos 24 /**< \brief (IISC_MR) Master Clock to fs Ratio */ 194 #define IISC_MR_IMCKFS_Msk (_U_(0x3F) << IISC_MR_IMCKFS_Pos) 195 #define IISC_MR_IMCKFS(value) (IISC_MR_IMCKFS_Msk & ((value) << IISC_MR_IMCKFS_Pos)) 196 #define IISC_MR_IMCKFS_16_Val _U_(0x0) /**< \brief (IISC_MR) 16 fs */ 197 #define IISC_MR_IMCKFS_32_Val _U_(0x1) /**< \brief (IISC_MR) 32 fs */ 198 #define IISC_MR_IMCKFS_64_Val _U_(0x3) /**< \brief (IISC_MR) 64 fs */ 199 #define IISC_MR_IMCKFS_128_Val _U_(0x7) /**< \brief (IISC_MR) 128 fs */ 200 #define IISC_MR_IMCKFS_256_Val _U_(0xF) /**< \brief (IISC_MR) 256 fs */ 201 #define IISC_MR_IMCKFS_384_Val _U_(0x17) /**< \brief (IISC_MR) 384 fs */ 202 #define IISC_MR_IMCKFS_512_Val _U_(0x1F) /**< \brief (IISC_MR) 512 fs */ 203 #define IISC_MR_IMCKFS_768_Val _U_(0x2F) /**< \brief (IISC_MR) 768 fs */ 204 #define IISC_MR_IMCKFS_1024_Val _U_(0x3F) /**< \brief (IISC_MR) 1024 fs */ 205 #define IISC_MR_IMCKFS_16 (IISC_MR_IMCKFS_16_Val << IISC_MR_IMCKFS_Pos) 206 #define IISC_MR_IMCKFS_32 (IISC_MR_IMCKFS_32_Val << IISC_MR_IMCKFS_Pos) 207 #define IISC_MR_IMCKFS_64 (IISC_MR_IMCKFS_64_Val << IISC_MR_IMCKFS_Pos) 208 #define IISC_MR_IMCKFS_128 (IISC_MR_IMCKFS_128_Val << IISC_MR_IMCKFS_Pos) 209 #define IISC_MR_IMCKFS_256 (IISC_MR_IMCKFS_256_Val << IISC_MR_IMCKFS_Pos) 210 #define IISC_MR_IMCKFS_384 (IISC_MR_IMCKFS_384_Val << IISC_MR_IMCKFS_Pos) 211 #define IISC_MR_IMCKFS_512 (IISC_MR_IMCKFS_512_Val << IISC_MR_IMCKFS_Pos) 212 #define IISC_MR_IMCKFS_768 (IISC_MR_IMCKFS_768_Val << IISC_MR_IMCKFS_Pos) 213 #define IISC_MR_IMCKFS_1024 (IISC_MR_IMCKFS_1024_Val << IISC_MR_IMCKFS_Pos) 214 #define IISC_MR_IMCKMODE_Pos 30 /**< \brief (IISC_MR) Master Clock Mode */ 215 #define IISC_MR_IMCKMODE (_U_(0x1) << IISC_MR_IMCKMODE_Pos) 216 #define IISC_MR_IMCKMODE_NO_IMCK_Val _U_(0x0) /**< \brief (IISC_MR) No IMCK generated */ 217 #define IISC_MR_IMCKMODE_IMCK_Val _U_(0x1) /**< \brief (IISC_MR) IMCK generated */ 218 #define IISC_MR_IMCKMODE_NO_IMCK (IISC_MR_IMCKMODE_NO_IMCK_Val << IISC_MR_IMCKMODE_Pos) 219 #define IISC_MR_IMCKMODE_IMCK (IISC_MR_IMCKMODE_IMCK_Val << IISC_MR_IMCKMODE_Pos) 220 #define IISC_MR_IWS24_Pos 31 /**< \brief (IISC_MR) IWS Data Slot Width */ 221 #define IISC_MR_IWS24 (_U_(0x1) << IISC_MR_IWS24_Pos) 222 #define IISC_MR_IWS24_32_Val _U_(0x0) /**< \brief (IISC_MR) IWS Data Slot is 32-bit wide for DATALENGTH=18/20/24-bit */ 223 #define IISC_MR_IWS24_24_Val _U_(0x1) /**< \brief (IISC_MR) IWS Data Slot is 24-bit wide for DATALENGTH=18/20/24-bit */ 224 #define IISC_MR_IWS24_32 (IISC_MR_IWS24_32_Val << IISC_MR_IWS24_Pos) 225 #define IISC_MR_IWS24_24 (IISC_MR_IWS24_24_Val << IISC_MR_IWS24_Pos) 226 #define IISC_MR_MASK _U_(0xFF00771D) /**< \brief (IISC_MR) MASK Register */ 227 228 /* -------- IISC_SR : (IISC Offset: 0x08) (R/ 32) Status Register -------- */ 229 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 230 typedef union { 231 struct { 232 uint32_t RXEN:1; /*!< bit: 0 Receive Enable */ 233 uint32_t RXRDY:1; /*!< bit: 1 Receive Ready */ 234 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun */ 235 uint32_t :1; /*!< bit: 3 Reserved */ 236 uint32_t TXEN:1; /*!< bit: 4 Transmit Enable */ 237 uint32_t TXRDY:1; /*!< bit: 5 Transmit Ready */ 238 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun */ 239 uint32_t :1; /*!< bit: 7 Reserved */ 240 uint32_t RXORCH:2; /*!< bit: 8.. 9 Receive Overrun Channels */ 241 uint32_t :10; /*!< bit: 10..19 Reserved */ 242 uint32_t TXURCH:2; /*!< bit: 20..21 Transmit Underrun Channels */ 243 uint32_t :10; /*!< bit: 22..31 Reserved */ 244 } bit; /*!< Structure used for bit access */ 245 uint32_t reg; /*!< Type used for register access */ 246 } IISC_SR_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define IISC_SR_OFFSET 0x08 /**< \brief (IISC_SR offset) Status Register */ 250 #define IISC_SR_RESETVALUE _U_(0x00000000); /**< \brief (IISC_SR reset_value) Status Register */ 251 252 #define IISC_SR_RXEN_Pos 0 /**< \brief (IISC_SR) Receive Enable */ 253 #define IISC_SR_RXEN (_U_(0x1) << IISC_SR_RXEN_Pos) 254 #define IISC_SR_RXEN_OFF_Val _U_(0x0) /**< \brief (IISC_SR) Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request */ 255 #define IISC_SR_RXEN_ON_Val _U_(0x1) /**< \brief (IISC_SR) Receiver is effectively enabled, following a CR.RXEN request */ 256 #define IISC_SR_RXEN_OFF (IISC_SR_RXEN_OFF_Val << IISC_SR_RXEN_Pos) 257 #define IISC_SR_RXEN_ON (IISC_SR_RXEN_ON_Val << IISC_SR_RXEN_Pos) 258 #define IISC_SR_RXRDY_Pos 1 /**< \brief (IISC_SR) Receive Ready */ 259 #define IISC_SR_RXRDY (_U_(0x1) << IISC_SR_RXRDY_Pos) 260 #define IISC_SR_RXRDY_EMPTY_Val _U_(0x0) /**< \brief (IISC_SR) The register RHR is empty and can't be read */ 261 #define IISC_SR_RXRDY_FULL_Val _U_(0x1) /**< \brief (IISC_SR) The register RHR is full and is ready to be read */ 262 #define IISC_SR_RXRDY_EMPTY (IISC_SR_RXRDY_EMPTY_Val << IISC_SR_RXRDY_Pos) 263 #define IISC_SR_RXRDY_FULL (IISC_SR_RXRDY_FULL_Val << IISC_SR_RXRDY_Pos) 264 #define IISC_SR_RXOR_Pos 2 /**< \brief (IISC_SR) Receive Overrun */ 265 #define IISC_SR_RXOR (_U_(0x1) << IISC_SR_RXOR_Pos) 266 #define IISC_SR_RXOR_NO_Val _U_(0x0) /**< \brief (IISC_SR) No overrun */ 267 #define IISC_SR_RXOR_YES_Val _U_(0x1) /**< \brief (IISC_SR) The previous received data has not been read. This data is lost */ 268 #define IISC_SR_RXOR_NO (IISC_SR_RXOR_NO_Val << IISC_SR_RXOR_Pos) 269 #define IISC_SR_RXOR_YES (IISC_SR_RXOR_YES_Val << IISC_SR_RXOR_Pos) 270 #define IISC_SR_TXEN_Pos 4 /**< \brief (IISC_SR) Transmit Enable */ 271 #define IISC_SR_TXEN (_U_(0x1) << IISC_SR_TXEN_Pos) 272 #define IISC_SR_TXEN_OFF_Val _U_(0x0) /**< \brief (IISC_SR) Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request */ 273 #define IISC_SR_TXEN_ON_Val _U_(0x1) /**< \brief (IISC_SR) Transmitter is effectively enabled, following a CR.TXEN request */ 274 #define IISC_SR_TXEN_OFF (IISC_SR_TXEN_OFF_Val << IISC_SR_TXEN_Pos) 275 #define IISC_SR_TXEN_ON (IISC_SR_TXEN_ON_Val << IISC_SR_TXEN_Pos) 276 #define IISC_SR_TXRDY_Pos 5 /**< \brief (IISC_SR) Transmit Ready */ 277 #define IISC_SR_TXRDY (_U_(0x1) << IISC_SR_TXRDY_Pos) 278 #define IISC_SR_TXRDY_FULL_Val _U_(0x0) /**< \brief (IISC_SR) The register THR is full and can't be written */ 279 #define IISC_SR_TXRDY_EMPTY_Val _U_(0x1) /**< \brief (IISC_SR) The register THR is empty and is ready to be written */ 280 #define IISC_SR_TXRDY_FULL (IISC_SR_TXRDY_FULL_Val << IISC_SR_TXRDY_Pos) 281 #define IISC_SR_TXRDY_EMPTY (IISC_SR_TXRDY_EMPTY_Val << IISC_SR_TXRDY_Pos) 282 #define IISC_SR_TXUR_Pos 6 /**< \brief (IISC_SR) Transmit Underrun */ 283 #define IISC_SR_TXUR (_U_(0x1) << IISC_SR_TXUR_Pos) 284 #define IISC_SR_TXUR_NO_Val _U_(0x0) /**< \brief (IISC_SR) No underrun */ 285 #define IISC_SR_TXUR_YES_Val _U_(0x1) /**< \brief (IISC_SR) The last bit of the last data written to the register THR has been set. Until the next write to THR, data will be sent according to MR.TXSAME field */ 286 #define IISC_SR_TXUR_NO (IISC_SR_TXUR_NO_Val << IISC_SR_TXUR_Pos) 287 #define IISC_SR_TXUR_YES (IISC_SR_TXUR_YES_Val << IISC_SR_TXUR_Pos) 288 #define IISC_SR_RXORCH_Pos 8 /**< \brief (IISC_SR) Receive Overrun Channels */ 289 #define IISC_SR_RXORCH_Msk (_U_(0x3) << IISC_SR_RXORCH_Pos) 290 #define IISC_SR_RXORCH(value) (IISC_SR_RXORCH_Msk & ((value) << IISC_SR_RXORCH_Pos)) 291 #define IISC_SR_RXORCH_LEFT_Val _U_(0x0) /**< \brief (IISC_SR) Overrun first occurred on left channel */ 292 #define IISC_SR_RXORCH_RIGHT_Val _U_(0x1) /**< \brief (IISC_SR) Overrun first occurred on right channel */ 293 #define IISC_SR_RXORCH_LEFT (IISC_SR_RXORCH_LEFT_Val << IISC_SR_RXORCH_Pos) 294 #define IISC_SR_RXORCH_RIGHT (IISC_SR_RXORCH_RIGHT_Val << IISC_SR_RXORCH_Pos) 295 #define IISC_SR_TXURCH_Pos 20 /**< \brief (IISC_SR) Transmit Underrun Channels */ 296 #define IISC_SR_TXURCH_Msk (_U_(0x3) << IISC_SR_TXURCH_Pos) 297 #define IISC_SR_TXURCH(value) (IISC_SR_TXURCH_Msk & ((value) << IISC_SR_TXURCH_Pos)) 298 #define IISC_SR_TXURCH_LEFT_Val _U_(0x0) /**< \brief (IISC_SR) Underrun first occurred on left channel */ 299 #define IISC_SR_TXURCH_RIGHT_Val _U_(0x1) /**< \brief (IISC_SR) Underrun first occurred on right channel */ 300 #define IISC_SR_TXURCH_LEFT (IISC_SR_TXURCH_LEFT_Val << IISC_SR_TXURCH_Pos) 301 #define IISC_SR_TXURCH_RIGHT (IISC_SR_TXURCH_RIGHT_Val << IISC_SR_TXURCH_Pos) 302 #define IISC_SR_MASK _U_(0x00300377) /**< \brief (IISC_SR) MASK Register */ 303 304 /* -------- IISC_SCR : (IISC Offset: 0x0C) ( /W 32) Status Clear Register -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 struct { 308 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 309 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun */ 310 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 311 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun */ 312 uint32_t :1; /*!< bit: 7 Reserved */ 313 uint32_t RXORCH:2; /*!< bit: 8.. 9 Receive Overrun Channels */ 314 uint32_t :10; /*!< bit: 10..19 Reserved */ 315 uint32_t TXURCH:2; /*!< bit: 20..21 Transmit Underrun Channels */ 316 uint32_t :10; /*!< bit: 22..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } IISC_SCR_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define IISC_SCR_OFFSET 0x0C /**< \brief (IISC_SCR offset) Status Clear Register */ 323 324 #define IISC_SCR_RXOR_Pos 2 /**< \brief (IISC_SCR) Receive Overrun */ 325 #define IISC_SCR_RXOR (_U_(0x1) << IISC_SCR_RXOR_Pos) 326 #define IISC_SCR_RXOR_NO_Val _U_(0x0) /**< \brief (IISC_SCR) No effect */ 327 #define IISC_SCR_RXOR_CLEAR_Val _U_(0x1) /**< \brief (IISC_SCR) Clears the corresponding SR bit */ 328 #define IISC_SCR_RXOR_NO (IISC_SCR_RXOR_NO_Val << IISC_SCR_RXOR_Pos) 329 #define IISC_SCR_RXOR_CLEAR (IISC_SCR_RXOR_CLEAR_Val << IISC_SCR_RXOR_Pos) 330 #define IISC_SCR_TXUR_Pos 6 /**< \brief (IISC_SCR) Transmit Underrun */ 331 #define IISC_SCR_TXUR (_U_(0x1) << IISC_SCR_TXUR_Pos) 332 #define IISC_SCR_TXUR_NO_Val _U_(0x0) /**< \brief (IISC_SCR) No effect */ 333 #define IISC_SCR_TXUR_CLEAR_Val _U_(0x1) /**< \brief (IISC_SCR) Clears the corresponding SR bit */ 334 #define IISC_SCR_TXUR_NO (IISC_SCR_TXUR_NO_Val << IISC_SCR_TXUR_Pos) 335 #define IISC_SCR_TXUR_CLEAR (IISC_SCR_TXUR_CLEAR_Val << IISC_SCR_TXUR_Pos) 336 #define IISC_SCR_RXORCH_Pos 8 /**< \brief (IISC_SCR) Receive Overrun Channels */ 337 #define IISC_SCR_RXORCH_Msk (_U_(0x3) << IISC_SCR_RXORCH_Pos) 338 #define IISC_SCR_RXORCH(value) (IISC_SCR_RXORCH_Msk & ((value) << IISC_SCR_RXORCH_Pos)) 339 #define IISC_SCR_TXURCH_Pos 20 /**< \brief (IISC_SCR) Transmit Underrun Channels */ 340 #define IISC_SCR_TXURCH_Msk (_U_(0x3) << IISC_SCR_TXURCH_Pos) 341 #define IISC_SCR_TXURCH(value) (IISC_SCR_TXURCH_Msk & ((value) << IISC_SCR_TXURCH_Pos)) 342 #define IISC_SCR_MASK _U_(0x00300344) /**< \brief (IISC_SCR) MASK Register */ 343 344 /* -------- IISC_SSR : (IISC Offset: 0x10) ( /W 32) Status Set Register -------- */ 345 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 346 typedef union { 347 struct { 348 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 349 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun */ 350 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 351 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun */ 352 uint32_t :1; /*!< bit: 7 Reserved */ 353 uint32_t RXORCH:2; /*!< bit: 8.. 9 Receive Overrun Channels */ 354 uint32_t :10; /*!< bit: 10..19 Reserved */ 355 uint32_t TXURCH:2; /*!< bit: 20..21 Transmit Underrun Channels */ 356 uint32_t :10; /*!< bit: 22..31 Reserved */ 357 } bit; /*!< Structure used for bit access */ 358 uint32_t reg; /*!< Type used for register access */ 359 } IISC_SSR_Type; 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 361 362 #define IISC_SSR_OFFSET 0x10 /**< \brief (IISC_SSR offset) Status Set Register */ 363 364 #define IISC_SSR_RXOR_Pos 2 /**< \brief (IISC_SSR) Receive Overrun */ 365 #define IISC_SSR_RXOR (_U_(0x1) << IISC_SSR_RXOR_Pos) 366 #define IISC_SSR_RXOR_NO_Val _U_(0x0) /**< \brief (IISC_SSR) No effect */ 367 #define IISC_SSR_RXOR_SET_Val _U_(0x1) /**< \brief (IISC_SSR) Sets corresponding SR bit */ 368 #define IISC_SSR_RXOR_NO (IISC_SSR_RXOR_NO_Val << IISC_SSR_RXOR_Pos) 369 #define IISC_SSR_RXOR_SET (IISC_SSR_RXOR_SET_Val << IISC_SSR_RXOR_Pos) 370 #define IISC_SSR_TXUR_Pos 6 /**< \brief (IISC_SSR) Transmit Underrun */ 371 #define IISC_SSR_TXUR (_U_(0x1) << IISC_SSR_TXUR_Pos) 372 #define IISC_SSR_TXUR_NO_Val _U_(0x0) /**< \brief (IISC_SSR) No effect */ 373 #define IISC_SSR_TXUR_SET_Val _U_(0x1) /**< \brief (IISC_SSR) Sets corresponding SR bit */ 374 #define IISC_SSR_TXUR_NO (IISC_SSR_TXUR_NO_Val << IISC_SSR_TXUR_Pos) 375 #define IISC_SSR_TXUR_SET (IISC_SSR_TXUR_SET_Val << IISC_SSR_TXUR_Pos) 376 #define IISC_SSR_RXORCH_Pos 8 /**< \brief (IISC_SSR) Receive Overrun Channels */ 377 #define IISC_SSR_RXORCH_Msk (_U_(0x3) << IISC_SSR_RXORCH_Pos) 378 #define IISC_SSR_RXORCH(value) (IISC_SSR_RXORCH_Msk & ((value) << IISC_SSR_RXORCH_Pos)) 379 #define IISC_SSR_TXURCH_Pos 20 /**< \brief (IISC_SSR) Transmit Underrun Channels */ 380 #define IISC_SSR_TXURCH_Msk (_U_(0x3) << IISC_SSR_TXURCH_Pos) 381 #define IISC_SSR_TXURCH(value) (IISC_SSR_TXURCH_Msk & ((value) << IISC_SSR_TXURCH_Pos)) 382 #define IISC_SSR_MASK _U_(0x00300344) /**< \brief (IISC_SSR) MASK Register */ 383 384 /* -------- IISC_IER : (IISC Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ 385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 386 typedef union { 387 struct { 388 uint32_t :1; /*!< bit: 0 Reserved */ 389 uint32_t RXRDY:1; /*!< bit: 1 Receiver Ready Interrupt Enable */ 390 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun Interrupt Enable */ 391 uint32_t :2; /*!< bit: 3.. 4 Reserved */ 392 uint32_t TXRDY:1; /*!< bit: 5 Transmit Ready Interrupt Enable */ 393 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun Interrupt Enable */ 394 uint32_t :25; /*!< bit: 7..31 Reserved */ 395 } bit; /*!< Structure used for bit access */ 396 uint32_t reg; /*!< Type used for register access */ 397 } IISC_IER_Type; 398 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 399 400 #define IISC_IER_OFFSET 0x14 /**< \brief (IISC_IER offset) Interrupt Enable Register */ 401 402 #define IISC_IER_RXRDY_Pos 1 /**< \brief (IISC_IER) Receiver Ready Interrupt Enable */ 403 #define IISC_IER_RXRDY (_U_(0x1) << IISC_IER_RXRDY_Pos) 404 #define IISC_IER_RXRDY_OFF_Val _U_(0x0) /**< \brief (IISC_IER) No effect */ 405 #define IISC_IER_RXRDY_ON_Val _U_(0x1) /**< \brief (IISC_IER) Enables the corresponding interrupt */ 406 #define IISC_IER_RXRDY_OFF (IISC_IER_RXRDY_OFF_Val << IISC_IER_RXRDY_Pos) 407 #define IISC_IER_RXRDY_ON (IISC_IER_RXRDY_ON_Val << IISC_IER_RXRDY_Pos) 408 #define IISC_IER_RXOR_Pos 2 /**< \brief (IISC_IER) Receive Overrun Interrupt Enable */ 409 #define IISC_IER_RXOR (_U_(0x1) << IISC_IER_RXOR_Pos) 410 #define IISC_IER_RXOR_OFF_Val _U_(0x0) /**< \brief (IISC_IER) No effect */ 411 #define IISC_IER_RXOR_ON_Val _U_(0x1) /**< \brief (IISC_IER) Enables the corresponding interrupt */ 412 #define IISC_IER_RXOR_OFF (IISC_IER_RXOR_OFF_Val << IISC_IER_RXOR_Pos) 413 #define IISC_IER_RXOR_ON (IISC_IER_RXOR_ON_Val << IISC_IER_RXOR_Pos) 414 #define IISC_IER_TXRDY_Pos 5 /**< \brief (IISC_IER) Transmit Ready Interrupt Enable */ 415 #define IISC_IER_TXRDY (_U_(0x1) << IISC_IER_TXRDY_Pos) 416 #define IISC_IER_TXRDY_OFF_Val _U_(0x0) /**< \brief (IISC_IER) No effect */ 417 #define IISC_IER_TXRDY_ON_Val _U_(0x1) /**< \brief (IISC_IER) Enables the corresponding interrupt */ 418 #define IISC_IER_TXRDY_OFF (IISC_IER_TXRDY_OFF_Val << IISC_IER_TXRDY_Pos) 419 #define IISC_IER_TXRDY_ON (IISC_IER_TXRDY_ON_Val << IISC_IER_TXRDY_Pos) 420 #define IISC_IER_TXUR_Pos 6 /**< \brief (IISC_IER) Transmit Underrun Interrupt Enable */ 421 #define IISC_IER_TXUR (_U_(0x1) << IISC_IER_TXUR_Pos) 422 #define IISC_IER_TXUR_OFF_Val _U_(0x0) /**< \brief (IISC_IER) No effect */ 423 #define IISC_IER_TXUR_ON_Val _U_(0x1) /**< \brief (IISC_IER) Enables the corresponding interrupt */ 424 #define IISC_IER_TXUR_OFF (IISC_IER_TXUR_OFF_Val << IISC_IER_TXUR_Pos) 425 #define IISC_IER_TXUR_ON (IISC_IER_TXUR_ON_Val << IISC_IER_TXUR_Pos) 426 #define IISC_IER_MASK _U_(0x00000066) /**< \brief (IISC_IER) MASK Register */ 427 428 /* -------- IISC_IDR : (IISC Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ 429 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 430 typedef union { 431 struct { 432 uint32_t :1; /*!< bit: 0 Reserved */ 433 uint32_t RXRDY:1; /*!< bit: 1 Receive Ready Interrupt Disable */ 434 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun Interrupt Disable */ 435 uint32_t :2; /*!< bit: 3.. 4 Reserved */ 436 uint32_t TXRDY:1; /*!< bit: 5 Transmit Ready Interrupt Disable */ 437 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun Interrupt Disable */ 438 uint32_t :25; /*!< bit: 7..31 Reserved */ 439 } bit; /*!< Structure used for bit access */ 440 uint32_t reg; /*!< Type used for register access */ 441 } IISC_IDR_Type; 442 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 443 444 #define IISC_IDR_OFFSET 0x18 /**< \brief (IISC_IDR offset) Interrupt Disable Register */ 445 446 #define IISC_IDR_RXRDY_Pos 1 /**< \brief (IISC_IDR) Receive Ready Interrupt Disable */ 447 #define IISC_IDR_RXRDY (_U_(0x1) << IISC_IDR_RXRDY_Pos) 448 #define IISC_IDR_RXRDY_OFF_Val _U_(0x0) /**< \brief (IISC_IDR) No effect */ 449 #define IISC_IDR_RXRDY_ON_Val _U_(0x1) /**< \brief (IISC_IDR) Disables the corresponding interrupt */ 450 #define IISC_IDR_RXRDY_OFF (IISC_IDR_RXRDY_OFF_Val << IISC_IDR_RXRDY_Pos) 451 #define IISC_IDR_RXRDY_ON (IISC_IDR_RXRDY_ON_Val << IISC_IDR_RXRDY_Pos) 452 #define IISC_IDR_RXOR_Pos 2 /**< \brief (IISC_IDR) Receive Overrun Interrupt Disable */ 453 #define IISC_IDR_RXOR (_U_(0x1) << IISC_IDR_RXOR_Pos) 454 #define IISC_IDR_RXOR_OFF_Val _U_(0x0) /**< \brief (IISC_IDR) No effect */ 455 #define IISC_IDR_RXOR_ON_Val _U_(0x1) /**< \brief (IISC_IDR) Disables the corresponding interrupt */ 456 #define IISC_IDR_RXOR_OFF (IISC_IDR_RXOR_OFF_Val << IISC_IDR_RXOR_Pos) 457 #define IISC_IDR_RXOR_ON (IISC_IDR_RXOR_ON_Val << IISC_IDR_RXOR_Pos) 458 #define IISC_IDR_TXRDY_Pos 5 /**< \brief (IISC_IDR) Transmit Ready Interrupt Disable */ 459 #define IISC_IDR_TXRDY (_U_(0x1) << IISC_IDR_TXRDY_Pos) 460 #define IISC_IDR_TXRDY_OFF_Val _U_(0x0) /**< \brief (IISC_IDR) No effect */ 461 #define IISC_IDR_TXRDY_ON_Val _U_(0x1) /**< \brief (IISC_IDR) Disables the corresponding interrupt */ 462 #define IISC_IDR_TXRDY_OFF (IISC_IDR_TXRDY_OFF_Val << IISC_IDR_TXRDY_Pos) 463 #define IISC_IDR_TXRDY_ON (IISC_IDR_TXRDY_ON_Val << IISC_IDR_TXRDY_Pos) 464 #define IISC_IDR_TXUR_Pos 6 /**< \brief (IISC_IDR) Transmit Underrun Interrupt Disable */ 465 #define IISC_IDR_TXUR (_U_(0x1) << IISC_IDR_TXUR_Pos) 466 #define IISC_IDR_TXUR_OFF_Val _U_(0x0) /**< \brief (IISC_IDR) No effect */ 467 #define IISC_IDR_TXUR_ON_Val _U_(0x1) /**< \brief (IISC_IDR) Disables the corresponding interrupt */ 468 #define IISC_IDR_TXUR_OFF (IISC_IDR_TXUR_OFF_Val << IISC_IDR_TXUR_Pos) 469 #define IISC_IDR_TXUR_ON (IISC_IDR_TXUR_ON_Val << IISC_IDR_TXUR_Pos) 470 #define IISC_IDR_MASK _U_(0x00000066) /**< \brief (IISC_IDR) MASK Register */ 471 472 /* -------- IISC_IMR : (IISC Offset: 0x1C) (R/ 32) Interrupt Mask Register -------- */ 473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 474 typedef union { 475 struct { 476 uint32_t :1; /*!< bit: 0 Reserved */ 477 uint32_t RXRDY:1; /*!< bit: 1 Receive Ready Interrupt Mask */ 478 uint32_t RXOR:1; /*!< bit: 2 Receive Overrun Interrupt Mask */ 479 uint32_t :2; /*!< bit: 3.. 4 Reserved */ 480 uint32_t TXRDY:1; /*!< bit: 5 Transmit Ready Interrupt Mask */ 481 uint32_t TXUR:1; /*!< bit: 6 Transmit Underrun Interrupt Mask */ 482 uint32_t :25; /*!< bit: 7..31 Reserved */ 483 } bit; /*!< Structure used for bit access */ 484 uint32_t reg; /*!< Type used for register access */ 485 } IISC_IMR_Type; 486 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 487 488 #define IISC_IMR_OFFSET 0x1C /**< \brief (IISC_IMR offset) Interrupt Mask Register */ 489 #define IISC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (IISC_IMR reset_value) Interrupt Mask Register */ 490 491 #define IISC_IMR_RXRDY_Pos 1 /**< \brief (IISC_IMR) Receive Ready Interrupt Mask */ 492 #define IISC_IMR_RXRDY (_U_(0x1) << IISC_IMR_RXRDY_Pos) 493 #define IISC_IMR_RXRDY_DISABLED_Val _U_(0x0) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */ 494 #define IISC_IMR_RXRDY_ENABLED_Val _U_(0x1) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */ 495 #define IISC_IMR_RXRDY_DISABLED (IISC_IMR_RXRDY_DISABLED_Val << IISC_IMR_RXRDY_Pos) 496 #define IISC_IMR_RXRDY_ENABLED (IISC_IMR_RXRDY_ENABLED_Val << IISC_IMR_RXRDY_Pos) 497 #define IISC_IMR_RXOR_Pos 2 /**< \brief (IISC_IMR) Receive Overrun Interrupt Mask */ 498 #define IISC_IMR_RXOR (_U_(0x1) << IISC_IMR_RXOR_Pos) 499 #define IISC_IMR_RXOR_DISABLED_Val _U_(0x0) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */ 500 #define IISC_IMR_RXOR_ENABLED_Val _U_(0x1) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */ 501 #define IISC_IMR_RXOR_DISABLED (IISC_IMR_RXOR_DISABLED_Val << IISC_IMR_RXOR_Pos) 502 #define IISC_IMR_RXOR_ENABLED (IISC_IMR_RXOR_ENABLED_Val << IISC_IMR_RXOR_Pos) 503 #define IISC_IMR_TXRDY_Pos 5 /**< \brief (IISC_IMR) Transmit Ready Interrupt Mask */ 504 #define IISC_IMR_TXRDY (_U_(0x1) << IISC_IMR_TXRDY_Pos) 505 #define IISC_IMR_TXRDY_DISABLED_Val _U_(0x0) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */ 506 #define IISC_IMR_TXRDY_ENABLED_Val _U_(0x1) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */ 507 #define IISC_IMR_TXRDY_DISABLED (IISC_IMR_TXRDY_DISABLED_Val << IISC_IMR_TXRDY_Pos) 508 #define IISC_IMR_TXRDY_ENABLED (IISC_IMR_TXRDY_ENABLED_Val << IISC_IMR_TXRDY_Pos) 509 #define IISC_IMR_TXUR_Pos 6 /**< \brief (IISC_IMR) Transmit Underrun Interrupt Mask */ 510 #define IISC_IMR_TXUR (_U_(0x1) << IISC_IMR_TXUR_Pos) 511 #define IISC_IMR_TXUR_DISABLED_Val _U_(0x0) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */ 512 #define IISC_IMR_TXUR_ENABLED_Val _U_(0x1) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */ 513 #define IISC_IMR_TXUR_DISABLED (IISC_IMR_TXUR_DISABLED_Val << IISC_IMR_TXUR_Pos) 514 #define IISC_IMR_TXUR_ENABLED (IISC_IMR_TXUR_ENABLED_Val << IISC_IMR_TXUR_Pos) 515 #define IISC_IMR_MASK _U_(0x00000066) /**< \brief (IISC_IMR) MASK Register */ 516 517 /* -------- IISC_RHR : (IISC Offset: 0x20) (R/ 32) Receive Holding Register -------- */ 518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 519 typedef union { 520 struct { 521 uint32_t RDAT:32; /*!< bit: 0..31 Receive Data */ 522 } bit; /*!< Structure used for bit access */ 523 uint32_t reg; /*!< Type used for register access */ 524 } IISC_RHR_Type; 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 #define IISC_RHR_OFFSET 0x20 /**< \brief (IISC_RHR offset) Receive Holding Register */ 528 #define IISC_RHR_RESETVALUE _U_(0x00000000); /**< \brief (IISC_RHR reset_value) Receive Holding Register */ 529 530 #define IISC_RHR_RDAT_Pos 0 /**< \brief (IISC_RHR) Receive Data */ 531 #define IISC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << IISC_RHR_RDAT_Pos) 532 #define IISC_RHR_RDAT(value) (IISC_RHR_RDAT_Msk & ((value) << IISC_RHR_RDAT_Pos)) 533 #define IISC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (IISC_RHR) MASK Register */ 534 535 /* -------- IISC_THR : (IISC Offset: 0x24) ( /W 32) Transmit Holding Register -------- */ 536 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 537 typedef union { 538 struct { 539 uint32_t TDAT:32; /*!< bit: 0..31 Transmit Data */ 540 } bit; /*!< Structure used for bit access */ 541 uint32_t reg; /*!< Type used for register access */ 542 } IISC_THR_Type; 543 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 544 545 #define IISC_THR_OFFSET 0x24 /**< \brief (IISC_THR offset) Transmit Holding Register */ 546 547 #define IISC_THR_TDAT_Pos 0 /**< \brief (IISC_THR) Transmit Data */ 548 #define IISC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << IISC_THR_TDAT_Pos) 549 #define IISC_THR_TDAT(value) (IISC_THR_TDAT_Msk & ((value) << IISC_THR_TDAT_Pos)) 550 #define IISC_THR_MASK _U_(0xFFFFFFFF) /**< \brief (IISC_THR) MASK Register */ 551 552 /* -------- IISC_VERSION : (IISC Offset: 0x28) (R/ 32) Version Register -------- */ 553 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 554 typedef union { 555 struct { 556 uint32_t VERSION:12; /*!< bit: 0..11 Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */ 557 uint32_t :4; /*!< bit: 12..15 Reserved */ 558 uint32_t VARIANT:4; /*!< bit: 16..19 Reserved. Value subject to change. No functionality associated. */ 559 uint32_t :12; /*!< bit: 20..31 Reserved */ 560 } bit; /*!< Structure used for bit access */ 561 uint32_t reg; /*!< Type used for register access */ 562 } IISC_VERSION_Type; 563 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 564 565 #define IISC_VERSION_OFFSET 0x28 /**< \brief (IISC_VERSION offset) Version Register */ 566 #define IISC_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (IISC_VERSION reset_value) Version Register */ 567 568 #define IISC_VERSION_VERSION_Pos 0 /**< \brief (IISC_VERSION) Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */ 569 #define IISC_VERSION_VERSION_Msk (_U_(0xFFF) << IISC_VERSION_VERSION_Pos) 570 #define IISC_VERSION_VERSION(value) (IISC_VERSION_VERSION_Msk & ((value) << IISC_VERSION_VERSION_Pos)) 571 #define IISC_VERSION_VARIANT_Pos 16 /**< \brief (IISC_VERSION) Reserved. Value subject to change. No functionality associated. */ 572 #define IISC_VERSION_VARIANT_Msk (_U_(0xF) << IISC_VERSION_VARIANT_Pos) 573 #define IISC_VERSION_VARIANT(value) (IISC_VERSION_VARIANT_Msk & ((value) << IISC_VERSION_VARIANT_Pos)) 574 #define IISC_VERSION_MASK _U_(0x000F0FFF) /**< \brief (IISC_VERSION) MASK Register */ 575 576 /* -------- IISC_PARAMETER : (IISC Offset: 0x2C) (R/ 32) Parameter Register -------- */ 577 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 578 typedef union { 579 struct { 580 uint32_t :7; /*!< bit: 0.. 6 Reserved */ 581 uint32_t FORMAT:1; /*!< bit: 7 Data protocol format */ 582 uint32_t :8; /*!< bit: 8..15 Reserved */ 583 uint32_t NBCHAN:5; /*!< bit: 16..20 Maximum number of channels - 1 */ 584 uint32_t :11; /*!< bit: 21..31 Reserved */ 585 } bit; /*!< Structure used for bit access */ 586 uint32_t reg; /*!< Type used for register access */ 587 } IISC_PARAMETER_Type; 588 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 589 590 #define IISC_PARAMETER_OFFSET 0x2C /**< \brief (IISC_PARAMETER offset) Parameter Register */ 591 #define IISC_PARAMETER_RESETVALUE _U_(0x00010000); /**< \brief (IISC_PARAMETER reset_value) Parameter Register */ 592 593 #define IISC_PARAMETER_FORMAT_Pos 7 /**< \brief (IISC_PARAMETER) Data protocol format */ 594 #define IISC_PARAMETER_FORMAT (_U_(0x1) << IISC_PARAMETER_FORMAT_Pos) 595 #define IISC_PARAMETER_FORMAT_I2S_Val _U_(0x0) /**< \brief (IISC_PARAMETER) I2S format, stereo with IWS low for left channel */ 596 #define IISC_PARAMETER_FORMAT_I2S (IISC_PARAMETER_FORMAT_I2S_Val << IISC_PARAMETER_FORMAT_Pos) 597 #define IISC_PARAMETER_NBCHAN_Pos 16 /**< \brief (IISC_PARAMETER) Maximum number of channels - 1 */ 598 #define IISC_PARAMETER_NBCHAN_Msk (_U_(0x1F) << IISC_PARAMETER_NBCHAN_Pos) 599 #define IISC_PARAMETER_NBCHAN(value) (IISC_PARAMETER_NBCHAN_Msk & ((value) << IISC_PARAMETER_NBCHAN_Pos)) 600 #define IISC_PARAMETER_MASK _U_(0x001F0080) /**< \brief (IISC_PARAMETER) MASK Register */ 601 602 /** \brief IISC hardware registers */ 603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 604 typedef struct { 605 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 606 __IO uint32_t MR; /**< \brief Offset: 0x04 (R/W 32) Mode Register */ 607 __I uint32_t SR; /**< \brief Offset: 0x08 (R/ 32) Status Register */ 608 __O uint32_t SCR; /**< \brief Offset: 0x0C ( /W 32) Status Clear Register */ 609 __O uint32_t SSR; /**< \brief Offset: 0x10 ( /W 32) Status Set Register */ 610 __O uint32_t IER; /**< \brief Offset: 0x14 ( /W 32) Interrupt Enable Register */ 611 __O uint32_t IDR; /**< \brief Offset: 0x18 ( /W 32) Interrupt Disable Register */ 612 __I uint32_t IMR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Mask Register */ 613 __I uint32_t RHR; /**< \brief Offset: 0x20 (R/ 32) Receive Holding Register */ 614 __O uint32_t THR; /**< \brief Offset: 0x24 ( /W 32) Transmit Holding Register */ 615 __I uint32_t VERSION; /**< \brief Offset: 0x28 (R/ 32) Version Register */ 616 __I uint32_t PARAMETER; /**< \brief Offset: 0x2C (R/ 32) Parameter Register */ 617 } Iisc; 618 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 619 620 /*@}*/ 621 622 #endif /* _SAM4L_IISC_COMPONENT_ */ 623
