1 /** 2 * \file 3 * 4 * \brief Component description for GPIO 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_GPIO_COMPONENT_ 30 #define _SAM4L_GPIO_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR GPIO */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_GPIO General-Purpose Input/Output Controller */ 36 /*@{*/ 37 38 #define GPIO_I7512 39 #define REV_GPIO 0x215 40 41 /* -------- GPIO_GPER : (GPIO Offset: 0x000) (R/W 32) port GPIO Enable Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t P0:1; /*!< bit: 0 GPIO Enable */ 46 uint32_t P1:1; /*!< bit: 1 GPIO Enable */ 47 uint32_t P2:1; /*!< bit: 2 GPIO Enable */ 48 uint32_t P3:1; /*!< bit: 3 GPIO Enable */ 49 uint32_t P4:1; /*!< bit: 4 GPIO Enable */ 50 uint32_t P5:1; /*!< bit: 5 GPIO Enable */ 51 uint32_t P6:1; /*!< bit: 6 GPIO Enable */ 52 uint32_t P7:1; /*!< bit: 7 GPIO Enable */ 53 uint32_t P8:1; /*!< bit: 8 GPIO Enable */ 54 uint32_t P9:1; /*!< bit: 9 GPIO Enable */ 55 uint32_t P10:1; /*!< bit: 10 GPIO Enable */ 56 uint32_t P11:1; /*!< bit: 11 GPIO Enable */ 57 uint32_t P12:1; /*!< bit: 12 GPIO Enable */ 58 uint32_t P13:1; /*!< bit: 13 GPIO Enable */ 59 uint32_t P14:1; /*!< bit: 14 GPIO Enable */ 60 uint32_t P15:1; /*!< bit: 15 GPIO Enable */ 61 uint32_t P16:1; /*!< bit: 16 GPIO Enable */ 62 uint32_t P17:1; /*!< bit: 17 GPIO Enable */ 63 uint32_t P18:1; /*!< bit: 18 GPIO Enable */ 64 uint32_t P19:1; /*!< bit: 19 GPIO Enable */ 65 uint32_t P20:1; /*!< bit: 20 GPIO Enable */ 66 uint32_t P21:1; /*!< bit: 21 GPIO Enable */ 67 uint32_t P22:1; /*!< bit: 22 GPIO Enable */ 68 uint32_t P23:1; /*!< bit: 23 GPIO Enable */ 69 uint32_t P24:1; /*!< bit: 24 GPIO Enable */ 70 uint32_t P25:1; /*!< bit: 25 GPIO Enable */ 71 uint32_t P26:1; /*!< bit: 26 GPIO Enable */ 72 uint32_t P27:1; /*!< bit: 27 GPIO Enable */ 73 uint32_t P28:1; /*!< bit: 28 GPIO Enable */ 74 uint32_t P29:1; /*!< bit: 29 GPIO Enable */ 75 uint32_t P30:1; /*!< bit: 30 GPIO Enable */ 76 uint32_t P31:1; /*!< bit: 31 GPIO Enable */ 77 } bit; /*!< Structure used for bit access */ 78 uint32_t reg; /*!< Type used for register access */ 79 } GPIO_GPER_Type; 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define GPIO_GPER_OFFSET 0x000 /**< \brief (GPIO_GPER offset) GPIO Enable Register */ 83 84 #define GPIO_GPER_P0_Pos 0 /**< \brief (GPIO_GPER) GPIO Enable */ 85 #define GPIO_GPER_P0 (_U_(0x1) << GPIO_GPER_P0_Pos) 86 #define GPIO_GPER_P1_Pos 1 /**< \brief (GPIO_GPER) GPIO Enable */ 87 #define GPIO_GPER_P1 (_U_(0x1) << GPIO_GPER_P1_Pos) 88 #define GPIO_GPER_P2_Pos 2 /**< \brief (GPIO_GPER) GPIO Enable */ 89 #define GPIO_GPER_P2 (_U_(0x1) << GPIO_GPER_P2_Pos) 90 #define GPIO_GPER_P3_Pos 3 /**< \brief (GPIO_GPER) GPIO Enable */ 91 #define GPIO_GPER_P3 (_U_(0x1) << GPIO_GPER_P3_Pos) 92 #define GPIO_GPER_P4_Pos 4 /**< \brief (GPIO_GPER) GPIO Enable */ 93 #define GPIO_GPER_P4 (_U_(0x1) << GPIO_GPER_P4_Pos) 94 #define GPIO_GPER_P5_Pos 5 /**< \brief (GPIO_GPER) GPIO Enable */ 95 #define GPIO_GPER_P5 (_U_(0x1) << GPIO_GPER_P5_Pos) 96 #define GPIO_GPER_P6_Pos 6 /**< \brief (GPIO_GPER) GPIO Enable */ 97 #define GPIO_GPER_P6 (_U_(0x1) << GPIO_GPER_P6_Pos) 98 #define GPIO_GPER_P7_Pos 7 /**< \brief (GPIO_GPER) GPIO Enable */ 99 #define GPIO_GPER_P7 (_U_(0x1) << GPIO_GPER_P7_Pos) 100 #define GPIO_GPER_P8_Pos 8 /**< \brief (GPIO_GPER) GPIO Enable */ 101 #define GPIO_GPER_P8 (_U_(0x1) << GPIO_GPER_P8_Pos) 102 #define GPIO_GPER_P9_Pos 9 /**< \brief (GPIO_GPER) GPIO Enable */ 103 #define GPIO_GPER_P9 (_U_(0x1) << GPIO_GPER_P9_Pos) 104 #define GPIO_GPER_P10_Pos 10 /**< \brief (GPIO_GPER) GPIO Enable */ 105 #define GPIO_GPER_P10 (_U_(0x1) << GPIO_GPER_P10_Pos) 106 #define GPIO_GPER_P11_Pos 11 /**< \brief (GPIO_GPER) GPIO Enable */ 107 #define GPIO_GPER_P11 (_U_(0x1) << GPIO_GPER_P11_Pos) 108 #define GPIO_GPER_P12_Pos 12 /**< \brief (GPIO_GPER) GPIO Enable */ 109 #define GPIO_GPER_P12 (_U_(0x1) << GPIO_GPER_P12_Pos) 110 #define GPIO_GPER_P13_Pos 13 /**< \brief (GPIO_GPER) GPIO Enable */ 111 #define GPIO_GPER_P13 (_U_(0x1) << GPIO_GPER_P13_Pos) 112 #define GPIO_GPER_P14_Pos 14 /**< \brief (GPIO_GPER) GPIO Enable */ 113 #define GPIO_GPER_P14 (_U_(0x1) << GPIO_GPER_P14_Pos) 114 #define GPIO_GPER_P15_Pos 15 /**< \brief (GPIO_GPER) GPIO Enable */ 115 #define GPIO_GPER_P15 (_U_(0x1) << GPIO_GPER_P15_Pos) 116 #define GPIO_GPER_P16_Pos 16 /**< \brief (GPIO_GPER) GPIO Enable */ 117 #define GPIO_GPER_P16 (_U_(0x1) << GPIO_GPER_P16_Pos) 118 #define GPIO_GPER_P17_Pos 17 /**< \brief (GPIO_GPER) GPIO Enable */ 119 #define GPIO_GPER_P17 (_U_(0x1) << GPIO_GPER_P17_Pos) 120 #define GPIO_GPER_P18_Pos 18 /**< \brief (GPIO_GPER) GPIO Enable */ 121 #define GPIO_GPER_P18 (_U_(0x1) << GPIO_GPER_P18_Pos) 122 #define GPIO_GPER_P19_Pos 19 /**< \brief (GPIO_GPER) GPIO Enable */ 123 #define GPIO_GPER_P19 (_U_(0x1) << GPIO_GPER_P19_Pos) 124 #define GPIO_GPER_P20_Pos 20 /**< \brief (GPIO_GPER) GPIO Enable */ 125 #define GPIO_GPER_P20 (_U_(0x1) << GPIO_GPER_P20_Pos) 126 #define GPIO_GPER_P21_Pos 21 /**< \brief (GPIO_GPER) GPIO Enable */ 127 #define GPIO_GPER_P21 (_U_(0x1) << GPIO_GPER_P21_Pos) 128 #define GPIO_GPER_P22_Pos 22 /**< \brief (GPIO_GPER) GPIO Enable */ 129 #define GPIO_GPER_P22 (_U_(0x1) << GPIO_GPER_P22_Pos) 130 #define GPIO_GPER_P23_Pos 23 /**< \brief (GPIO_GPER) GPIO Enable */ 131 #define GPIO_GPER_P23 (_U_(0x1) << GPIO_GPER_P23_Pos) 132 #define GPIO_GPER_P24_Pos 24 /**< \brief (GPIO_GPER) GPIO Enable */ 133 #define GPIO_GPER_P24 (_U_(0x1) << GPIO_GPER_P24_Pos) 134 #define GPIO_GPER_P25_Pos 25 /**< \brief (GPIO_GPER) GPIO Enable */ 135 #define GPIO_GPER_P25 (_U_(0x1) << GPIO_GPER_P25_Pos) 136 #define GPIO_GPER_P26_Pos 26 /**< \brief (GPIO_GPER) GPIO Enable */ 137 #define GPIO_GPER_P26 (_U_(0x1) << GPIO_GPER_P26_Pos) 138 #define GPIO_GPER_P27_Pos 27 /**< \brief (GPIO_GPER) GPIO Enable */ 139 #define GPIO_GPER_P27 (_U_(0x1) << GPIO_GPER_P27_Pos) 140 #define GPIO_GPER_P28_Pos 28 /**< \brief (GPIO_GPER) GPIO Enable */ 141 #define GPIO_GPER_P28 (_U_(0x1) << GPIO_GPER_P28_Pos) 142 #define GPIO_GPER_P29_Pos 29 /**< \brief (GPIO_GPER) GPIO Enable */ 143 #define GPIO_GPER_P29 (_U_(0x1) << GPIO_GPER_P29_Pos) 144 #define GPIO_GPER_P30_Pos 30 /**< \brief (GPIO_GPER) GPIO Enable */ 145 #define GPIO_GPER_P30 (_U_(0x1) << GPIO_GPER_P30_Pos) 146 #define GPIO_GPER_P31_Pos 31 /**< \brief (GPIO_GPER) GPIO Enable */ 147 #define GPIO_GPER_P31 (_U_(0x1) << GPIO_GPER_P31_Pos) 148 #define GPIO_GPER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GPER) MASK Register */ 149 150 /* -------- GPIO_GPERS : (GPIO Offset: 0x004) ( /W 32) port GPIO Enable Register - Set -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t P0:1; /*!< bit: 0 GPIO Enable */ 155 uint32_t P1:1; /*!< bit: 1 GPIO Enable */ 156 uint32_t P2:1; /*!< bit: 2 GPIO Enable */ 157 uint32_t P3:1; /*!< bit: 3 GPIO Enable */ 158 uint32_t P4:1; /*!< bit: 4 GPIO Enable */ 159 uint32_t P5:1; /*!< bit: 5 GPIO Enable */ 160 uint32_t P6:1; /*!< bit: 6 GPIO Enable */ 161 uint32_t P7:1; /*!< bit: 7 GPIO Enable */ 162 uint32_t P8:1; /*!< bit: 8 GPIO Enable */ 163 uint32_t P9:1; /*!< bit: 9 GPIO Enable */ 164 uint32_t P10:1; /*!< bit: 10 GPIO Enable */ 165 uint32_t P11:1; /*!< bit: 11 GPIO Enable */ 166 uint32_t P12:1; /*!< bit: 12 GPIO Enable */ 167 uint32_t P13:1; /*!< bit: 13 GPIO Enable */ 168 uint32_t P14:1; /*!< bit: 14 GPIO Enable */ 169 uint32_t P15:1; /*!< bit: 15 GPIO Enable */ 170 uint32_t P16:1; /*!< bit: 16 GPIO Enable */ 171 uint32_t P17:1; /*!< bit: 17 GPIO Enable */ 172 uint32_t P18:1; /*!< bit: 18 GPIO Enable */ 173 uint32_t P19:1; /*!< bit: 19 GPIO Enable */ 174 uint32_t P20:1; /*!< bit: 20 GPIO Enable */ 175 uint32_t P21:1; /*!< bit: 21 GPIO Enable */ 176 uint32_t P22:1; /*!< bit: 22 GPIO Enable */ 177 uint32_t P23:1; /*!< bit: 23 GPIO Enable */ 178 uint32_t P24:1; /*!< bit: 24 GPIO Enable */ 179 uint32_t P25:1; /*!< bit: 25 GPIO Enable */ 180 uint32_t P26:1; /*!< bit: 26 GPIO Enable */ 181 uint32_t P27:1; /*!< bit: 27 GPIO Enable */ 182 uint32_t P28:1; /*!< bit: 28 GPIO Enable */ 183 uint32_t P29:1; /*!< bit: 29 GPIO Enable */ 184 uint32_t P30:1; /*!< bit: 30 GPIO Enable */ 185 uint32_t P31:1; /*!< bit: 31 GPIO Enable */ 186 } bit; /*!< Structure used for bit access */ 187 uint32_t reg; /*!< Type used for register access */ 188 } GPIO_GPERS_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define GPIO_GPERS_OFFSET 0x004 /**< \brief (GPIO_GPERS offset) GPIO Enable Register - Set */ 192 193 #define GPIO_GPERS_P0_Pos 0 /**< \brief (GPIO_GPERS) GPIO Enable */ 194 #define GPIO_GPERS_P0 (_U_(0x1) << GPIO_GPERS_P0_Pos) 195 #define GPIO_GPERS_P1_Pos 1 /**< \brief (GPIO_GPERS) GPIO Enable */ 196 #define GPIO_GPERS_P1 (_U_(0x1) << GPIO_GPERS_P1_Pos) 197 #define GPIO_GPERS_P2_Pos 2 /**< \brief (GPIO_GPERS) GPIO Enable */ 198 #define GPIO_GPERS_P2 (_U_(0x1) << GPIO_GPERS_P2_Pos) 199 #define GPIO_GPERS_P3_Pos 3 /**< \brief (GPIO_GPERS) GPIO Enable */ 200 #define GPIO_GPERS_P3 (_U_(0x1) << GPIO_GPERS_P3_Pos) 201 #define GPIO_GPERS_P4_Pos 4 /**< \brief (GPIO_GPERS) GPIO Enable */ 202 #define GPIO_GPERS_P4 (_U_(0x1) << GPIO_GPERS_P4_Pos) 203 #define GPIO_GPERS_P5_Pos 5 /**< \brief (GPIO_GPERS) GPIO Enable */ 204 #define GPIO_GPERS_P5 (_U_(0x1) << GPIO_GPERS_P5_Pos) 205 #define GPIO_GPERS_P6_Pos 6 /**< \brief (GPIO_GPERS) GPIO Enable */ 206 #define GPIO_GPERS_P6 (_U_(0x1) << GPIO_GPERS_P6_Pos) 207 #define GPIO_GPERS_P7_Pos 7 /**< \brief (GPIO_GPERS) GPIO Enable */ 208 #define GPIO_GPERS_P7 (_U_(0x1) << GPIO_GPERS_P7_Pos) 209 #define GPIO_GPERS_P8_Pos 8 /**< \brief (GPIO_GPERS) GPIO Enable */ 210 #define GPIO_GPERS_P8 (_U_(0x1) << GPIO_GPERS_P8_Pos) 211 #define GPIO_GPERS_P9_Pos 9 /**< \brief (GPIO_GPERS) GPIO Enable */ 212 #define GPIO_GPERS_P9 (_U_(0x1) << GPIO_GPERS_P9_Pos) 213 #define GPIO_GPERS_P10_Pos 10 /**< \brief (GPIO_GPERS) GPIO Enable */ 214 #define GPIO_GPERS_P10 (_U_(0x1) << GPIO_GPERS_P10_Pos) 215 #define GPIO_GPERS_P11_Pos 11 /**< \brief (GPIO_GPERS) GPIO Enable */ 216 #define GPIO_GPERS_P11 (_U_(0x1) << GPIO_GPERS_P11_Pos) 217 #define GPIO_GPERS_P12_Pos 12 /**< \brief (GPIO_GPERS) GPIO Enable */ 218 #define GPIO_GPERS_P12 (_U_(0x1) << GPIO_GPERS_P12_Pos) 219 #define GPIO_GPERS_P13_Pos 13 /**< \brief (GPIO_GPERS) GPIO Enable */ 220 #define GPIO_GPERS_P13 (_U_(0x1) << GPIO_GPERS_P13_Pos) 221 #define GPIO_GPERS_P14_Pos 14 /**< \brief (GPIO_GPERS) GPIO Enable */ 222 #define GPIO_GPERS_P14 (_U_(0x1) << GPIO_GPERS_P14_Pos) 223 #define GPIO_GPERS_P15_Pos 15 /**< \brief (GPIO_GPERS) GPIO Enable */ 224 #define GPIO_GPERS_P15 (_U_(0x1) << GPIO_GPERS_P15_Pos) 225 #define GPIO_GPERS_P16_Pos 16 /**< \brief (GPIO_GPERS) GPIO Enable */ 226 #define GPIO_GPERS_P16 (_U_(0x1) << GPIO_GPERS_P16_Pos) 227 #define GPIO_GPERS_P17_Pos 17 /**< \brief (GPIO_GPERS) GPIO Enable */ 228 #define GPIO_GPERS_P17 (_U_(0x1) << GPIO_GPERS_P17_Pos) 229 #define GPIO_GPERS_P18_Pos 18 /**< \brief (GPIO_GPERS) GPIO Enable */ 230 #define GPIO_GPERS_P18 (_U_(0x1) << GPIO_GPERS_P18_Pos) 231 #define GPIO_GPERS_P19_Pos 19 /**< \brief (GPIO_GPERS) GPIO Enable */ 232 #define GPIO_GPERS_P19 (_U_(0x1) << GPIO_GPERS_P19_Pos) 233 #define GPIO_GPERS_P20_Pos 20 /**< \brief (GPIO_GPERS) GPIO Enable */ 234 #define GPIO_GPERS_P20 (_U_(0x1) << GPIO_GPERS_P20_Pos) 235 #define GPIO_GPERS_P21_Pos 21 /**< \brief (GPIO_GPERS) GPIO Enable */ 236 #define GPIO_GPERS_P21 (_U_(0x1) << GPIO_GPERS_P21_Pos) 237 #define GPIO_GPERS_P22_Pos 22 /**< \brief (GPIO_GPERS) GPIO Enable */ 238 #define GPIO_GPERS_P22 (_U_(0x1) << GPIO_GPERS_P22_Pos) 239 #define GPIO_GPERS_P23_Pos 23 /**< \brief (GPIO_GPERS) GPIO Enable */ 240 #define GPIO_GPERS_P23 (_U_(0x1) << GPIO_GPERS_P23_Pos) 241 #define GPIO_GPERS_P24_Pos 24 /**< \brief (GPIO_GPERS) GPIO Enable */ 242 #define GPIO_GPERS_P24 (_U_(0x1) << GPIO_GPERS_P24_Pos) 243 #define GPIO_GPERS_P25_Pos 25 /**< \brief (GPIO_GPERS) GPIO Enable */ 244 #define GPIO_GPERS_P25 (_U_(0x1) << GPIO_GPERS_P25_Pos) 245 #define GPIO_GPERS_P26_Pos 26 /**< \brief (GPIO_GPERS) GPIO Enable */ 246 #define GPIO_GPERS_P26 (_U_(0x1) << GPIO_GPERS_P26_Pos) 247 #define GPIO_GPERS_P27_Pos 27 /**< \brief (GPIO_GPERS) GPIO Enable */ 248 #define GPIO_GPERS_P27 (_U_(0x1) << GPIO_GPERS_P27_Pos) 249 #define GPIO_GPERS_P28_Pos 28 /**< \brief (GPIO_GPERS) GPIO Enable */ 250 #define GPIO_GPERS_P28 (_U_(0x1) << GPIO_GPERS_P28_Pos) 251 #define GPIO_GPERS_P29_Pos 29 /**< \brief (GPIO_GPERS) GPIO Enable */ 252 #define GPIO_GPERS_P29 (_U_(0x1) << GPIO_GPERS_P29_Pos) 253 #define GPIO_GPERS_P30_Pos 30 /**< \brief (GPIO_GPERS) GPIO Enable */ 254 #define GPIO_GPERS_P30 (_U_(0x1) << GPIO_GPERS_P30_Pos) 255 #define GPIO_GPERS_P31_Pos 31 /**< \brief (GPIO_GPERS) GPIO Enable */ 256 #define GPIO_GPERS_P31 (_U_(0x1) << GPIO_GPERS_P31_Pos) 257 #define GPIO_GPERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GPERS) MASK Register */ 258 259 /* -------- GPIO_GPERC : (GPIO Offset: 0x008) ( /W 32) port GPIO Enable Register - Clear -------- */ 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 261 typedef union { 262 struct { 263 uint32_t P0:1; /*!< bit: 0 GPIO Enable */ 264 uint32_t P1:1; /*!< bit: 1 GPIO Enable */ 265 uint32_t P2:1; /*!< bit: 2 GPIO Enable */ 266 uint32_t P3:1; /*!< bit: 3 GPIO Enable */ 267 uint32_t P4:1; /*!< bit: 4 GPIO Enable */ 268 uint32_t P5:1; /*!< bit: 5 GPIO Enable */ 269 uint32_t P6:1; /*!< bit: 6 GPIO Enable */ 270 uint32_t P7:1; /*!< bit: 7 GPIO Enable */ 271 uint32_t P8:1; /*!< bit: 8 GPIO Enable */ 272 uint32_t P9:1; /*!< bit: 9 GPIO Enable */ 273 uint32_t P10:1; /*!< bit: 10 GPIO Enable */ 274 uint32_t P11:1; /*!< bit: 11 GPIO Enable */ 275 uint32_t P12:1; /*!< bit: 12 GPIO Enable */ 276 uint32_t P13:1; /*!< bit: 13 GPIO Enable */ 277 uint32_t P14:1; /*!< bit: 14 GPIO Enable */ 278 uint32_t P15:1; /*!< bit: 15 GPIO Enable */ 279 uint32_t P16:1; /*!< bit: 16 GPIO Enable */ 280 uint32_t P17:1; /*!< bit: 17 GPIO Enable */ 281 uint32_t P18:1; /*!< bit: 18 GPIO Enable */ 282 uint32_t P19:1; /*!< bit: 19 GPIO Enable */ 283 uint32_t P20:1; /*!< bit: 20 GPIO Enable */ 284 uint32_t P21:1; /*!< bit: 21 GPIO Enable */ 285 uint32_t P22:1; /*!< bit: 22 GPIO Enable */ 286 uint32_t P23:1; /*!< bit: 23 GPIO Enable */ 287 uint32_t P24:1; /*!< bit: 24 GPIO Enable */ 288 uint32_t P25:1; /*!< bit: 25 GPIO Enable */ 289 uint32_t P26:1; /*!< bit: 26 GPIO Enable */ 290 uint32_t P27:1; /*!< bit: 27 GPIO Enable */ 291 uint32_t P28:1; /*!< bit: 28 GPIO Enable */ 292 uint32_t P29:1; /*!< bit: 29 GPIO Enable */ 293 uint32_t P30:1; /*!< bit: 30 GPIO Enable */ 294 uint32_t P31:1; /*!< bit: 31 GPIO Enable */ 295 } bit; /*!< Structure used for bit access */ 296 uint32_t reg; /*!< Type used for register access */ 297 } GPIO_GPERC_Type; 298 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 299 300 #define GPIO_GPERC_OFFSET 0x008 /**< \brief (GPIO_GPERC offset) GPIO Enable Register - Clear */ 301 302 #define GPIO_GPERC_P0_Pos 0 /**< \brief (GPIO_GPERC) GPIO Enable */ 303 #define GPIO_GPERC_P0 (_U_(0x1) << GPIO_GPERC_P0_Pos) 304 #define GPIO_GPERC_P1_Pos 1 /**< \brief (GPIO_GPERC) GPIO Enable */ 305 #define GPIO_GPERC_P1 (_U_(0x1) << GPIO_GPERC_P1_Pos) 306 #define GPIO_GPERC_P2_Pos 2 /**< \brief (GPIO_GPERC) GPIO Enable */ 307 #define GPIO_GPERC_P2 (_U_(0x1) << GPIO_GPERC_P2_Pos) 308 #define GPIO_GPERC_P3_Pos 3 /**< \brief (GPIO_GPERC) GPIO Enable */ 309 #define GPIO_GPERC_P3 (_U_(0x1) << GPIO_GPERC_P3_Pos) 310 #define GPIO_GPERC_P4_Pos 4 /**< \brief (GPIO_GPERC) GPIO Enable */ 311 #define GPIO_GPERC_P4 (_U_(0x1) << GPIO_GPERC_P4_Pos) 312 #define GPIO_GPERC_P5_Pos 5 /**< \brief (GPIO_GPERC) GPIO Enable */ 313 #define GPIO_GPERC_P5 (_U_(0x1) << GPIO_GPERC_P5_Pos) 314 #define GPIO_GPERC_P6_Pos 6 /**< \brief (GPIO_GPERC) GPIO Enable */ 315 #define GPIO_GPERC_P6 (_U_(0x1) << GPIO_GPERC_P6_Pos) 316 #define GPIO_GPERC_P7_Pos 7 /**< \brief (GPIO_GPERC) GPIO Enable */ 317 #define GPIO_GPERC_P7 (_U_(0x1) << GPIO_GPERC_P7_Pos) 318 #define GPIO_GPERC_P8_Pos 8 /**< \brief (GPIO_GPERC) GPIO Enable */ 319 #define GPIO_GPERC_P8 (_U_(0x1) << GPIO_GPERC_P8_Pos) 320 #define GPIO_GPERC_P9_Pos 9 /**< \brief (GPIO_GPERC) GPIO Enable */ 321 #define GPIO_GPERC_P9 (_U_(0x1) << GPIO_GPERC_P9_Pos) 322 #define GPIO_GPERC_P10_Pos 10 /**< \brief (GPIO_GPERC) GPIO Enable */ 323 #define GPIO_GPERC_P10 (_U_(0x1) << GPIO_GPERC_P10_Pos) 324 #define GPIO_GPERC_P11_Pos 11 /**< \brief (GPIO_GPERC) GPIO Enable */ 325 #define GPIO_GPERC_P11 (_U_(0x1) << GPIO_GPERC_P11_Pos) 326 #define GPIO_GPERC_P12_Pos 12 /**< \brief (GPIO_GPERC) GPIO Enable */ 327 #define GPIO_GPERC_P12 (_U_(0x1) << GPIO_GPERC_P12_Pos) 328 #define GPIO_GPERC_P13_Pos 13 /**< \brief (GPIO_GPERC) GPIO Enable */ 329 #define GPIO_GPERC_P13 (_U_(0x1) << GPIO_GPERC_P13_Pos) 330 #define GPIO_GPERC_P14_Pos 14 /**< \brief (GPIO_GPERC) GPIO Enable */ 331 #define GPIO_GPERC_P14 (_U_(0x1) << GPIO_GPERC_P14_Pos) 332 #define GPIO_GPERC_P15_Pos 15 /**< \brief (GPIO_GPERC) GPIO Enable */ 333 #define GPIO_GPERC_P15 (_U_(0x1) << GPIO_GPERC_P15_Pos) 334 #define GPIO_GPERC_P16_Pos 16 /**< \brief (GPIO_GPERC) GPIO Enable */ 335 #define GPIO_GPERC_P16 (_U_(0x1) << GPIO_GPERC_P16_Pos) 336 #define GPIO_GPERC_P17_Pos 17 /**< \brief (GPIO_GPERC) GPIO Enable */ 337 #define GPIO_GPERC_P17 (_U_(0x1) << GPIO_GPERC_P17_Pos) 338 #define GPIO_GPERC_P18_Pos 18 /**< \brief (GPIO_GPERC) GPIO Enable */ 339 #define GPIO_GPERC_P18 (_U_(0x1) << GPIO_GPERC_P18_Pos) 340 #define GPIO_GPERC_P19_Pos 19 /**< \brief (GPIO_GPERC) GPIO Enable */ 341 #define GPIO_GPERC_P19 (_U_(0x1) << GPIO_GPERC_P19_Pos) 342 #define GPIO_GPERC_P20_Pos 20 /**< \brief (GPIO_GPERC) GPIO Enable */ 343 #define GPIO_GPERC_P20 (_U_(0x1) << GPIO_GPERC_P20_Pos) 344 #define GPIO_GPERC_P21_Pos 21 /**< \brief (GPIO_GPERC) GPIO Enable */ 345 #define GPIO_GPERC_P21 (_U_(0x1) << GPIO_GPERC_P21_Pos) 346 #define GPIO_GPERC_P22_Pos 22 /**< \brief (GPIO_GPERC) GPIO Enable */ 347 #define GPIO_GPERC_P22 (_U_(0x1) << GPIO_GPERC_P22_Pos) 348 #define GPIO_GPERC_P23_Pos 23 /**< \brief (GPIO_GPERC) GPIO Enable */ 349 #define GPIO_GPERC_P23 (_U_(0x1) << GPIO_GPERC_P23_Pos) 350 #define GPIO_GPERC_P24_Pos 24 /**< \brief (GPIO_GPERC) GPIO Enable */ 351 #define GPIO_GPERC_P24 (_U_(0x1) << GPIO_GPERC_P24_Pos) 352 #define GPIO_GPERC_P25_Pos 25 /**< \brief (GPIO_GPERC) GPIO Enable */ 353 #define GPIO_GPERC_P25 (_U_(0x1) << GPIO_GPERC_P25_Pos) 354 #define GPIO_GPERC_P26_Pos 26 /**< \brief (GPIO_GPERC) GPIO Enable */ 355 #define GPIO_GPERC_P26 (_U_(0x1) << GPIO_GPERC_P26_Pos) 356 #define GPIO_GPERC_P27_Pos 27 /**< \brief (GPIO_GPERC) GPIO Enable */ 357 #define GPIO_GPERC_P27 (_U_(0x1) << GPIO_GPERC_P27_Pos) 358 #define GPIO_GPERC_P28_Pos 28 /**< \brief (GPIO_GPERC) GPIO Enable */ 359 #define GPIO_GPERC_P28 (_U_(0x1) << GPIO_GPERC_P28_Pos) 360 #define GPIO_GPERC_P29_Pos 29 /**< \brief (GPIO_GPERC) GPIO Enable */ 361 #define GPIO_GPERC_P29 (_U_(0x1) << GPIO_GPERC_P29_Pos) 362 #define GPIO_GPERC_P30_Pos 30 /**< \brief (GPIO_GPERC) GPIO Enable */ 363 #define GPIO_GPERC_P30 (_U_(0x1) << GPIO_GPERC_P30_Pos) 364 #define GPIO_GPERC_P31_Pos 31 /**< \brief (GPIO_GPERC) GPIO Enable */ 365 #define GPIO_GPERC_P31 (_U_(0x1) << GPIO_GPERC_P31_Pos) 366 #define GPIO_GPERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GPERC) MASK Register */ 367 368 /* -------- GPIO_GPERT : (GPIO Offset: 0x00C) ( /W 32) port GPIO Enable Register - Toggle -------- */ 369 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 370 typedef union { 371 struct { 372 uint32_t P0:1; /*!< bit: 0 GPIO Enable */ 373 uint32_t P1:1; /*!< bit: 1 GPIO Enable */ 374 uint32_t P2:1; /*!< bit: 2 GPIO Enable */ 375 uint32_t P3:1; /*!< bit: 3 GPIO Enable */ 376 uint32_t P4:1; /*!< bit: 4 GPIO Enable */ 377 uint32_t P5:1; /*!< bit: 5 GPIO Enable */ 378 uint32_t P6:1; /*!< bit: 6 GPIO Enable */ 379 uint32_t P7:1; /*!< bit: 7 GPIO Enable */ 380 uint32_t P8:1; /*!< bit: 8 GPIO Enable */ 381 uint32_t P9:1; /*!< bit: 9 GPIO Enable */ 382 uint32_t P10:1; /*!< bit: 10 GPIO Enable */ 383 uint32_t P11:1; /*!< bit: 11 GPIO Enable */ 384 uint32_t P12:1; /*!< bit: 12 GPIO Enable */ 385 uint32_t P13:1; /*!< bit: 13 GPIO Enable */ 386 uint32_t P14:1; /*!< bit: 14 GPIO Enable */ 387 uint32_t P15:1; /*!< bit: 15 GPIO Enable */ 388 uint32_t P16:1; /*!< bit: 16 GPIO Enable */ 389 uint32_t P17:1; /*!< bit: 17 GPIO Enable */ 390 uint32_t P18:1; /*!< bit: 18 GPIO Enable */ 391 uint32_t P19:1; /*!< bit: 19 GPIO Enable */ 392 uint32_t P20:1; /*!< bit: 20 GPIO Enable */ 393 uint32_t P21:1; /*!< bit: 21 GPIO Enable */ 394 uint32_t P22:1; /*!< bit: 22 GPIO Enable */ 395 uint32_t P23:1; /*!< bit: 23 GPIO Enable */ 396 uint32_t P24:1; /*!< bit: 24 GPIO Enable */ 397 uint32_t P25:1; /*!< bit: 25 GPIO Enable */ 398 uint32_t P26:1; /*!< bit: 26 GPIO Enable */ 399 uint32_t P27:1; /*!< bit: 27 GPIO Enable */ 400 uint32_t P28:1; /*!< bit: 28 GPIO Enable */ 401 uint32_t P29:1; /*!< bit: 29 GPIO Enable */ 402 uint32_t P30:1; /*!< bit: 30 GPIO Enable */ 403 uint32_t P31:1; /*!< bit: 31 GPIO Enable */ 404 } bit; /*!< Structure used for bit access */ 405 uint32_t reg; /*!< Type used for register access */ 406 } GPIO_GPERT_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define GPIO_GPERT_OFFSET 0x00C /**< \brief (GPIO_GPERT offset) GPIO Enable Register - Toggle */ 410 411 #define GPIO_GPERT_P0_Pos 0 /**< \brief (GPIO_GPERT) GPIO Enable */ 412 #define GPIO_GPERT_P0 (_U_(0x1) << GPIO_GPERT_P0_Pos) 413 #define GPIO_GPERT_P1_Pos 1 /**< \brief (GPIO_GPERT) GPIO Enable */ 414 #define GPIO_GPERT_P1 (_U_(0x1) << GPIO_GPERT_P1_Pos) 415 #define GPIO_GPERT_P2_Pos 2 /**< \brief (GPIO_GPERT) GPIO Enable */ 416 #define GPIO_GPERT_P2 (_U_(0x1) << GPIO_GPERT_P2_Pos) 417 #define GPIO_GPERT_P3_Pos 3 /**< \brief (GPIO_GPERT) GPIO Enable */ 418 #define GPIO_GPERT_P3 (_U_(0x1) << GPIO_GPERT_P3_Pos) 419 #define GPIO_GPERT_P4_Pos 4 /**< \brief (GPIO_GPERT) GPIO Enable */ 420 #define GPIO_GPERT_P4 (_U_(0x1) << GPIO_GPERT_P4_Pos) 421 #define GPIO_GPERT_P5_Pos 5 /**< \brief (GPIO_GPERT) GPIO Enable */ 422 #define GPIO_GPERT_P5 (_U_(0x1) << GPIO_GPERT_P5_Pos) 423 #define GPIO_GPERT_P6_Pos 6 /**< \brief (GPIO_GPERT) GPIO Enable */ 424 #define GPIO_GPERT_P6 (_U_(0x1) << GPIO_GPERT_P6_Pos) 425 #define GPIO_GPERT_P7_Pos 7 /**< \brief (GPIO_GPERT) GPIO Enable */ 426 #define GPIO_GPERT_P7 (_U_(0x1) << GPIO_GPERT_P7_Pos) 427 #define GPIO_GPERT_P8_Pos 8 /**< \brief (GPIO_GPERT) GPIO Enable */ 428 #define GPIO_GPERT_P8 (_U_(0x1) << GPIO_GPERT_P8_Pos) 429 #define GPIO_GPERT_P9_Pos 9 /**< \brief (GPIO_GPERT) GPIO Enable */ 430 #define GPIO_GPERT_P9 (_U_(0x1) << GPIO_GPERT_P9_Pos) 431 #define GPIO_GPERT_P10_Pos 10 /**< \brief (GPIO_GPERT) GPIO Enable */ 432 #define GPIO_GPERT_P10 (_U_(0x1) << GPIO_GPERT_P10_Pos) 433 #define GPIO_GPERT_P11_Pos 11 /**< \brief (GPIO_GPERT) GPIO Enable */ 434 #define GPIO_GPERT_P11 (_U_(0x1) << GPIO_GPERT_P11_Pos) 435 #define GPIO_GPERT_P12_Pos 12 /**< \brief (GPIO_GPERT) GPIO Enable */ 436 #define GPIO_GPERT_P12 (_U_(0x1) << GPIO_GPERT_P12_Pos) 437 #define GPIO_GPERT_P13_Pos 13 /**< \brief (GPIO_GPERT) GPIO Enable */ 438 #define GPIO_GPERT_P13 (_U_(0x1) << GPIO_GPERT_P13_Pos) 439 #define GPIO_GPERT_P14_Pos 14 /**< \brief (GPIO_GPERT) GPIO Enable */ 440 #define GPIO_GPERT_P14 (_U_(0x1) << GPIO_GPERT_P14_Pos) 441 #define GPIO_GPERT_P15_Pos 15 /**< \brief (GPIO_GPERT) GPIO Enable */ 442 #define GPIO_GPERT_P15 (_U_(0x1) << GPIO_GPERT_P15_Pos) 443 #define GPIO_GPERT_P16_Pos 16 /**< \brief (GPIO_GPERT) GPIO Enable */ 444 #define GPIO_GPERT_P16 (_U_(0x1) << GPIO_GPERT_P16_Pos) 445 #define GPIO_GPERT_P17_Pos 17 /**< \brief (GPIO_GPERT) GPIO Enable */ 446 #define GPIO_GPERT_P17 (_U_(0x1) << GPIO_GPERT_P17_Pos) 447 #define GPIO_GPERT_P18_Pos 18 /**< \brief (GPIO_GPERT) GPIO Enable */ 448 #define GPIO_GPERT_P18 (_U_(0x1) << GPIO_GPERT_P18_Pos) 449 #define GPIO_GPERT_P19_Pos 19 /**< \brief (GPIO_GPERT) GPIO Enable */ 450 #define GPIO_GPERT_P19 (_U_(0x1) << GPIO_GPERT_P19_Pos) 451 #define GPIO_GPERT_P20_Pos 20 /**< \brief (GPIO_GPERT) GPIO Enable */ 452 #define GPIO_GPERT_P20 (_U_(0x1) << GPIO_GPERT_P20_Pos) 453 #define GPIO_GPERT_P21_Pos 21 /**< \brief (GPIO_GPERT) GPIO Enable */ 454 #define GPIO_GPERT_P21 (_U_(0x1) << GPIO_GPERT_P21_Pos) 455 #define GPIO_GPERT_P22_Pos 22 /**< \brief (GPIO_GPERT) GPIO Enable */ 456 #define GPIO_GPERT_P22 (_U_(0x1) << GPIO_GPERT_P22_Pos) 457 #define GPIO_GPERT_P23_Pos 23 /**< \brief (GPIO_GPERT) GPIO Enable */ 458 #define GPIO_GPERT_P23 (_U_(0x1) << GPIO_GPERT_P23_Pos) 459 #define GPIO_GPERT_P24_Pos 24 /**< \brief (GPIO_GPERT) GPIO Enable */ 460 #define GPIO_GPERT_P24 (_U_(0x1) << GPIO_GPERT_P24_Pos) 461 #define GPIO_GPERT_P25_Pos 25 /**< \brief (GPIO_GPERT) GPIO Enable */ 462 #define GPIO_GPERT_P25 (_U_(0x1) << GPIO_GPERT_P25_Pos) 463 #define GPIO_GPERT_P26_Pos 26 /**< \brief (GPIO_GPERT) GPIO Enable */ 464 #define GPIO_GPERT_P26 (_U_(0x1) << GPIO_GPERT_P26_Pos) 465 #define GPIO_GPERT_P27_Pos 27 /**< \brief (GPIO_GPERT) GPIO Enable */ 466 #define GPIO_GPERT_P27 (_U_(0x1) << GPIO_GPERT_P27_Pos) 467 #define GPIO_GPERT_P28_Pos 28 /**< \brief (GPIO_GPERT) GPIO Enable */ 468 #define GPIO_GPERT_P28 (_U_(0x1) << GPIO_GPERT_P28_Pos) 469 #define GPIO_GPERT_P29_Pos 29 /**< \brief (GPIO_GPERT) GPIO Enable */ 470 #define GPIO_GPERT_P29 (_U_(0x1) << GPIO_GPERT_P29_Pos) 471 #define GPIO_GPERT_P30_Pos 30 /**< \brief (GPIO_GPERT) GPIO Enable */ 472 #define GPIO_GPERT_P30 (_U_(0x1) << GPIO_GPERT_P30_Pos) 473 #define GPIO_GPERT_P31_Pos 31 /**< \brief (GPIO_GPERT) GPIO Enable */ 474 #define GPIO_GPERT_P31 (_U_(0x1) << GPIO_GPERT_P31_Pos) 475 #define GPIO_GPERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GPERT) MASK Register */ 476 477 /* -------- GPIO_PMR0 : (GPIO Offset: 0x010) (R/W 32) port Peripheral Mux Register 0 -------- */ 478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 479 typedef union { 480 struct { 481 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 0 */ 482 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 0 */ 483 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 0 */ 484 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 0 */ 485 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 0 */ 486 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 0 */ 487 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 0 */ 488 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 0 */ 489 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 0 */ 490 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 0 */ 491 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 0 */ 492 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 0 */ 493 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 0 */ 494 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 0 */ 495 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 0 */ 496 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 0 */ 497 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 0 */ 498 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 0 */ 499 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 0 */ 500 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 0 */ 501 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 0 */ 502 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 0 */ 503 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 0 */ 504 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 0 */ 505 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 0 */ 506 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 0 */ 507 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 0 */ 508 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 0 */ 509 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 0 */ 510 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 0 */ 511 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 0 */ 512 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 0 */ 513 } bit; /*!< Structure used for bit access */ 514 uint32_t reg; /*!< Type used for register access */ 515 } GPIO_PMR0_Type; 516 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 517 518 #define GPIO_PMR0_OFFSET 0x010 /**< \brief (GPIO_PMR0 offset) Peripheral Mux Register 0 */ 519 520 #define GPIO_PMR0_P0_Pos 0 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 521 #define GPIO_PMR0_P0 (_U_(0x1) << GPIO_PMR0_P0_Pos) 522 #define GPIO_PMR0_P1_Pos 1 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 523 #define GPIO_PMR0_P1 (_U_(0x1) << GPIO_PMR0_P1_Pos) 524 #define GPIO_PMR0_P2_Pos 2 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 525 #define GPIO_PMR0_P2 (_U_(0x1) << GPIO_PMR0_P2_Pos) 526 #define GPIO_PMR0_P3_Pos 3 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 527 #define GPIO_PMR0_P3 (_U_(0x1) << GPIO_PMR0_P3_Pos) 528 #define GPIO_PMR0_P4_Pos 4 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 529 #define GPIO_PMR0_P4 (_U_(0x1) << GPIO_PMR0_P4_Pos) 530 #define GPIO_PMR0_P5_Pos 5 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 531 #define GPIO_PMR0_P5 (_U_(0x1) << GPIO_PMR0_P5_Pos) 532 #define GPIO_PMR0_P6_Pos 6 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 533 #define GPIO_PMR0_P6 (_U_(0x1) << GPIO_PMR0_P6_Pos) 534 #define GPIO_PMR0_P7_Pos 7 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 535 #define GPIO_PMR0_P7 (_U_(0x1) << GPIO_PMR0_P7_Pos) 536 #define GPIO_PMR0_P8_Pos 8 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 537 #define GPIO_PMR0_P8 (_U_(0x1) << GPIO_PMR0_P8_Pos) 538 #define GPIO_PMR0_P9_Pos 9 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 539 #define GPIO_PMR0_P9 (_U_(0x1) << GPIO_PMR0_P9_Pos) 540 #define GPIO_PMR0_P10_Pos 10 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 541 #define GPIO_PMR0_P10 (_U_(0x1) << GPIO_PMR0_P10_Pos) 542 #define GPIO_PMR0_P11_Pos 11 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 543 #define GPIO_PMR0_P11 (_U_(0x1) << GPIO_PMR0_P11_Pos) 544 #define GPIO_PMR0_P12_Pos 12 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 545 #define GPIO_PMR0_P12 (_U_(0x1) << GPIO_PMR0_P12_Pos) 546 #define GPIO_PMR0_P13_Pos 13 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 547 #define GPIO_PMR0_P13 (_U_(0x1) << GPIO_PMR0_P13_Pos) 548 #define GPIO_PMR0_P14_Pos 14 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 549 #define GPIO_PMR0_P14 (_U_(0x1) << GPIO_PMR0_P14_Pos) 550 #define GPIO_PMR0_P15_Pos 15 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 551 #define GPIO_PMR0_P15 (_U_(0x1) << GPIO_PMR0_P15_Pos) 552 #define GPIO_PMR0_P16_Pos 16 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 553 #define GPIO_PMR0_P16 (_U_(0x1) << GPIO_PMR0_P16_Pos) 554 #define GPIO_PMR0_P17_Pos 17 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 555 #define GPIO_PMR0_P17 (_U_(0x1) << GPIO_PMR0_P17_Pos) 556 #define GPIO_PMR0_P18_Pos 18 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 557 #define GPIO_PMR0_P18 (_U_(0x1) << GPIO_PMR0_P18_Pos) 558 #define GPIO_PMR0_P19_Pos 19 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 559 #define GPIO_PMR0_P19 (_U_(0x1) << GPIO_PMR0_P19_Pos) 560 #define GPIO_PMR0_P20_Pos 20 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 561 #define GPIO_PMR0_P20 (_U_(0x1) << GPIO_PMR0_P20_Pos) 562 #define GPIO_PMR0_P21_Pos 21 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 563 #define GPIO_PMR0_P21 (_U_(0x1) << GPIO_PMR0_P21_Pos) 564 #define GPIO_PMR0_P22_Pos 22 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 565 #define GPIO_PMR0_P22 (_U_(0x1) << GPIO_PMR0_P22_Pos) 566 #define GPIO_PMR0_P23_Pos 23 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 567 #define GPIO_PMR0_P23 (_U_(0x1) << GPIO_PMR0_P23_Pos) 568 #define GPIO_PMR0_P24_Pos 24 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 569 #define GPIO_PMR0_P24 (_U_(0x1) << GPIO_PMR0_P24_Pos) 570 #define GPIO_PMR0_P25_Pos 25 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 571 #define GPIO_PMR0_P25 (_U_(0x1) << GPIO_PMR0_P25_Pos) 572 #define GPIO_PMR0_P26_Pos 26 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 573 #define GPIO_PMR0_P26 (_U_(0x1) << GPIO_PMR0_P26_Pos) 574 #define GPIO_PMR0_P27_Pos 27 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 575 #define GPIO_PMR0_P27 (_U_(0x1) << GPIO_PMR0_P27_Pos) 576 #define GPIO_PMR0_P28_Pos 28 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 577 #define GPIO_PMR0_P28 (_U_(0x1) << GPIO_PMR0_P28_Pos) 578 #define GPIO_PMR0_P29_Pos 29 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 579 #define GPIO_PMR0_P29 (_U_(0x1) << GPIO_PMR0_P29_Pos) 580 #define GPIO_PMR0_P30_Pos 30 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 581 #define GPIO_PMR0_P30 (_U_(0x1) << GPIO_PMR0_P30_Pos) 582 #define GPIO_PMR0_P31_Pos 31 /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */ 583 #define GPIO_PMR0_P31 (_U_(0x1) << GPIO_PMR0_P31_Pos) 584 #define GPIO_PMR0_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR0) MASK Register */ 585 586 /* -------- GPIO_PMR0S : (GPIO Offset: 0x014) ( /W 32) port Peripheral Mux Register 0 - Set -------- */ 587 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 588 typedef union { 589 struct { 590 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 0 */ 591 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 0 */ 592 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 0 */ 593 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 0 */ 594 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 0 */ 595 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 0 */ 596 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 0 */ 597 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 0 */ 598 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 0 */ 599 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 0 */ 600 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 0 */ 601 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 0 */ 602 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 0 */ 603 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 0 */ 604 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 0 */ 605 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 0 */ 606 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 0 */ 607 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 0 */ 608 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 0 */ 609 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 0 */ 610 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 0 */ 611 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 0 */ 612 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 0 */ 613 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 0 */ 614 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 0 */ 615 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 0 */ 616 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 0 */ 617 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 0 */ 618 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 0 */ 619 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 0 */ 620 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 0 */ 621 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 0 */ 622 } bit; /*!< Structure used for bit access */ 623 uint32_t reg; /*!< Type used for register access */ 624 } GPIO_PMR0S_Type; 625 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 626 627 #define GPIO_PMR0S_OFFSET 0x014 /**< \brief (GPIO_PMR0S offset) Peripheral Mux Register 0 - Set */ 628 629 #define GPIO_PMR0S_P0_Pos 0 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 630 #define GPIO_PMR0S_P0 (_U_(0x1) << GPIO_PMR0S_P0_Pos) 631 #define GPIO_PMR0S_P1_Pos 1 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 632 #define GPIO_PMR0S_P1 (_U_(0x1) << GPIO_PMR0S_P1_Pos) 633 #define GPIO_PMR0S_P2_Pos 2 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 634 #define GPIO_PMR0S_P2 (_U_(0x1) << GPIO_PMR0S_P2_Pos) 635 #define GPIO_PMR0S_P3_Pos 3 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 636 #define GPIO_PMR0S_P3 (_U_(0x1) << GPIO_PMR0S_P3_Pos) 637 #define GPIO_PMR0S_P4_Pos 4 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 638 #define GPIO_PMR0S_P4 (_U_(0x1) << GPIO_PMR0S_P4_Pos) 639 #define GPIO_PMR0S_P5_Pos 5 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 640 #define GPIO_PMR0S_P5 (_U_(0x1) << GPIO_PMR0S_P5_Pos) 641 #define GPIO_PMR0S_P6_Pos 6 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 642 #define GPIO_PMR0S_P6 (_U_(0x1) << GPIO_PMR0S_P6_Pos) 643 #define GPIO_PMR0S_P7_Pos 7 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 644 #define GPIO_PMR0S_P7 (_U_(0x1) << GPIO_PMR0S_P7_Pos) 645 #define GPIO_PMR0S_P8_Pos 8 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 646 #define GPIO_PMR0S_P8 (_U_(0x1) << GPIO_PMR0S_P8_Pos) 647 #define GPIO_PMR0S_P9_Pos 9 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 648 #define GPIO_PMR0S_P9 (_U_(0x1) << GPIO_PMR0S_P9_Pos) 649 #define GPIO_PMR0S_P10_Pos 10 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 650 #define GPIO_PMR0S_P10 (_U_(0x1) << GPIO_PMR0S_P10_Pos) 651 #define GPIO_PMR0S_P11_Pos 11 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 652 #define GPIO_PMR0S_P11 (_U_(0x1) << GPIO_PMR0S_P11_Pos) 653 #define GPIO_PMR0S_P12_Pos 12 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 654 #define GPIO_PMR0S_P12 (_U_(0x1) << GPIO_PMR0S_P12_Pos) 655 #define GPIO_PMR0S_P13_Pos 13 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 656 #define GPIO_PMR0S_P13 (_U_(0x1) << GPIO_PMR0S_P13_Pos) 657 #define GPIO_PMR0S_P14_Pos 14 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 658 #define GPIO_PMR0S_P14 (_U_(0x1) << GPIO_PMR0S_P14_Pos) 659 #define GPIO_PMR0S_P15_Pos 15 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 660 #define GPIO_PMR0S_P15 (_U_(0x1) << GPIO_PMR0S_P15_Pos) 661 #define GPIO_PMR0S_P16_Pos 16 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 662 #define GPIO_PMR0S_P16 (_U_(0x1) << GPIO_PMR0S_P16_Pos) 663 #define GPIO_PMR0S_P17_Pos 17 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 664 #define GPIO_PMR0S_P17 (_U_(0x1) << GPIO_PMR0S_P17_Pos) 665 #define GPIO_PMR0S_P18_Pos 18 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 666 #define GPIO_PMR0S_P18 (_U_(0x1) << GPIO_PMR0S_P18_Pos) 667 #define GPIO_PMR0S_P19_Pos 19 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 668 #define GPIO_PMR0S_P19 (_U_(0x1) << GPIO_PMR0S_P19_Pos) 669 #define GPIO_PMR0S_P20_Pos 20 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 670 #define GPIO_PMR0S_P20 (_U_(0x1) << GPIO_PMR0S_P20_Pos) 671 #define GPIO_PMR0S_P21_Pos 21 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 672 #define GPIO_PMR0S_P21 (_U_(0x1) << GPIO_PMR0S_P21_Pos) 673 #define GPIO_PMR0S_P22_Pos 22 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 674 #define GPIO_PMR0S_P22 (_U_(0x1) << GPIO_PMR0S_P22_Pos) 675 #define GPIO_PMR0S_P23_Pos 23 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 676 #define GPIO_PMR0S_P23 (_U_(0x1) << GPIO_PMR0S_P23_Pos) 677 #define GPIO_PMR0S_P24_Pos 24 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 678 #define GPIO_PMR0S_P24 (_U_(0x1) << GPIO_PMR0S_P24_Pos) 679 #define GPIO_PMR0S_P25_Pos 25 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 680 #define GPIO_PMR0S_P25 (_U_(0x1) << GPIO_PMR0S_P25_Pos) 681 #define GPIO_PMR0S_P26_Pos 26 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 682 #define GPIO_PMR0S_P26 (_U_(0x1) << GPIO_PMR0S_P26_Pos) 683 #define GPIO_PMR0S_P27_Pos 27 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 684 #define GPIO_PMR0S_P27 (_U_(0x1) << GPIO_PMR0S_P27_Pos) 685 #define GPIO_PMR0S_P28_Pos 28 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 686 #define GPIO_PMR0S_P28 (_U_(0x1) << GPIO_PMR0S_P28_Pos) 687 #define GPIO_PMR0S_P29_Pos 29 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 688 #define GPIO_PMR0S_P29 (_U_(0x1) << GPIO_PMR0S_P29_Pos) 689 #define GPIO_PMR0S_P30_Pos 30 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 690 #define GPIO_PMR0S_P30 (_U_(0x1) << GPIO_PMR0S_P30_Pos) 691 #define GPIO_PMR0S_P31_Pos 31 /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */ 692 #define GPIO_PMR0S_P31 (_U_(0x1) << GPIO_PMR0S_P31_Pos) 693 #define GPIO_PMR0S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR0S) MASK Register */ 694 695 /* -------- GPIO_PMR0C : (GPIO Offset: 0x018) ( /W 32) port Peripheral Mux Register 0 - Clear -------- */ 696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 697 typedef union { 698 struct { 699 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 0 */ 700 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 0 */ 701 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 0 */ 702 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 0 */ 703 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 0 */ 704 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 0 */ 705 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 0 */ 706 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 0 */ 707 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 0 */ 708 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 0 */ 709 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 0 */ 710 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 0 */ 711 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 0 */ 712 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 0 */ 713 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 0 */ 714 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 0 */ 715 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 0 */ 716 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 0 */ 717 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 0 */ 718 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 0 */ 719 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 0 */ 720 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 0 */ 721 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 0 */ 722 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 0 */ 723 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 0 */ 724 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 0 */ 725 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 0 */ 726 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 0 */ 727 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 0 */ 728 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 0 */ 729 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 0 */ 730 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 0 */ 731 } bit; /*!< Structure used for bit access */ 732 uint32_t reg; /*!< Type used for register access */ 733 } GPIO_PMR0C_Type; 734 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 735 736 #define GPIO_PMR0C_OFFSET 0x018 /**< \brief (GPIO_PMR0C offset) Peripheral Mux Register 0 - Clear */ 737 738 #define GPIO_PMR0C_P0_Pos 0 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 739 #define GPIO_PMR0C_P0 (_U_(0x1) << GPIO_PMR0C_P0_Pos) 740 #define GPIO_PMR0C_P1_Pos 1 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 741 #define GPIO_PMR0C_P1 (_U_(0x1) << GPIO_PMR0C_P1_Pos) 742 #define GPIO_PMR0C_P2_Pos 2 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 743 #define GPIO_PMR0C_P2 (_U_(0x1) << GPIO_PMR0C_P2_Pos) 744 #define GPIO_PMR0C_P3_Pos 3 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 745 #define GPIO_PMR0C_P3 (_U_(0x1) << GPIO_PMR0C_P3_Pos) 746 #define GPIO_PMR0C_P4_Pos 4 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 747 #define GPIO_PMR0C_P4 (_U_(0x1) << GPIO_PMR0C_P4_Pos) 748 #define GPIO_PMR0C_P5_Pos 5 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 749 #define GPIO_PMR0C_P5 (_U_(0x1) << GPIO_PMR0C_P5_Pos) 750 #define GPIO_PMR0C_P6_Pos 6 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 751 #define GPIO_PMR0C_P6 (_U_(0x1) << GPIO_PMR0C_P6_Pos) 752 #define GPIO_PMR0C_P7_Pos 7 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 753 #define GPIO_PMR0C_P7 (_U_(0x1) << GPIO_PMR0C_P7_Pos) 754 #define GPIO_PMR0C_P8_Pos 8 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 755 #define GPIO_PMR0C_P8 (_U_(0x1) << GPIO_PMR0C_P8_Pos) 756 #define GPIO_PMR0C_P9_Pos 9 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 757 #define GPIO_PMR0C_P9 (_U_(0x1) << GPIO_PMR0C_P9_Pos) 758 #define GPIO_PMR0C_P10_Pos 10 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 759 #define GPIO_PMR0C_P10 (_U_(0x1) << GPIO_PMR0C_P10_Pos) 760 #define GPIO_PMR0C_P11_Pos 11 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 761 #define GPIO_PMR0C_P11 (_U_(0x1) << GPIO_PMR0C_P11_Pos) 762 #define GPIO_PMR0C_P12_Pos 12 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 763 #define GPIO_PMR0C_P12 (_U_(0x1) << GPIO_PMR0C_P12_Pos) 764 #define GPIO_PMR0C_P13_Pos 13 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 765 #define GPIO_PMR0C_P13 (_U_(0x1) << GPIO_PMR0C_P13_Pos) 766 #define GPIO_PMR0C_P14_Pos 14 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 767 #define GPIO_PMR0C_P14 (_U_(0x1) << GPIO_PMR0C_P14_Pos) 768 #define GPIO_PMR0C_P15_Pos 15 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 769 #define GPIO_PMR0C_P15 (_U_(0x1) << GPIO_PMR0C_P15_Pos) 770 #define GPIO_PMR0C_P16_Pos 16 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 771 #define GPIO_PMR0C_P16 (_U_(0x1) << GPIO_PMR0C_P16_Pos) 772 #define GPIO_PMR0C_P17_Pos 17 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 773 #define GPIO_PMR0C_P17 (_U_(0x1) << GPIO_PMR0C_P17_Pos) 774 #define GPIO_PMR0C_P18_Pos 18 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 775 #define GPIO_PMR0C_P18 (_U_(0x1) << GPIO_PMR0C_P18_Pos) 776 #define GPIO_PMR0C_P19_Pos 19 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 777 #define GPIO_PMR0C_P19 (_U_(0x1) << GPIO_PMR0C_P19_Pos) 778 #define GPIO_PMR0C_P20_Pos 20 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 779 #define GPIO_PMR0C_P20 (_U_(0x1) << GPIO_PMR0C_P20_Pos) 780 #define GPIO_PMR0C_P21_Pos 21 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 781 #define GPIO_PMR0C_P21 (_U_(0x1) << GPIO_PMR0C_P21_Pos) 782 #define GPIO_PMR0C_P22_Pos 22 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 783 #define GPIO_PMR0C_P22 (_U_(0x1) << GPIO_PMR0C_P22_Pos) 784 #define GPIO_PMR0C_P23_Pos 23 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 785 #define GPIO_PMR0C_P23 (_U_(0x1) << GPIO_PMR0C_P23_Pos) 786 #define GPIO_PMR0C_P24_Pos 24 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 787 #define GPIO_PMR0C_P24 (_U_(0x1) << GPIO_PMR0C_P24_Pos) 788 #define GPIO_PMR0C_P25_Pos 25 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 789 #define GPIO_PMR0C_P25 (_U_(0x1) << GPIO_PMR0C_P25_Pos) 790 #define GPIO_PMR0C_P26_Pos 26 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 791 #define GPIO_PMR0C_P26 (_U_(0x1) << GPIO_PMR0C_P26_Pos) 792 #define GPIO_PMR0C_P27_Pos 27 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 793 #define GPIO_PMR0C_P27 (_U_(0x1) << GPIO_PMR0C_P27_Pos) 794 #define GPIO_PMR0C_P28_Pos 28 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 795 #define GPIO_PMR0C_P28 (_U_(0x1) << GPIO_PMR0C_P28_Pos) 796 #define GPIO_PMR0C_P29_Pos 29 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 797 #define GPIO_PMR0C_P29 (_U_(0x1) << GPIO_PMR0C_P29_Pos) 798 #define GPIO_PMR0C_P30_Pos 30 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 799 #define GPIO_PMR0C_P30 (_U_(0x1) << GPIO_PMR0C_P30_Pos) 800 #define GPIO_PMR0C_P31_Pos 31 /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */ 801 #define GPIO_PMR0C_P31 (_U_(0x1) << GPIO_PMR0C_P31_Pos) 802 #define GPIO_PMR0C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR0C) MASK Register */ 803 804 /* -------- GPIO_PMR0T : (GPIO Offset: 0x01C) ( /W 32) port Peripheral Mux Register 0 - Toggle -------- */ 805 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 806 typedef union { 807 struct { 808 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 0 */ 809 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 0 */ 810 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 0 */ 811 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 0 */ 812 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 0 */ 813 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 0 */ 814 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 0 */ 815 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 0 */ 816 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 0 */ 817 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 0 */ 818 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 0 */ 819 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 0 */ 820 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 0 */ 821 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 0 */ 822 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 0 */ 823 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 0 */ 824 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 0 */ 825 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 0 */ 826 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 0 */ 827 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 0 */ 828 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 0 */ 829 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 0 */ 830 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 0 */ 831 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 0 */ 832 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 0 */ 833 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 0 */ 834 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 0 */ 835 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 0 */ 836 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 0 */ 837 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 0 */ 838 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 0 */ 839 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 0 */ 840 } bit; /*!< Structure used for bit access */ 841 uint32_t reg; /*!< Type used for register access */ 842 } GPIO_PMR0T_Type; 843 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 844 845 #define GPIO_PMR0T_OFFSET 0x01C /**< \brief (GPIO_PMR0T offset) Peripheral Mux Register 0 - Toggle */ 846 847 #define GPIO_PMR0T_P0_Pos 0 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 848 #define GPIO_PMR0T_P0 (_U_(0x1) << GPIO_PMR0T_P0_Pos) 849 #define GPIO_PMR0T_P1_Pos 1 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 850 #define GPIO_PMR0T_P1 (_U_(0x1) << GPIO_PMR0T_P1_Pos) 851 #define GPIO_PMR0T_P2_Pos 2 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 852 #define GPIO_PMR0T_P2 (_U_(0x1) << GPIO_PMR0T_P2_Pos) 853 #define GPIO_PMR0T_P3_Pos 3 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 854 #define GPIO_PMR0T_P3 (_U_(0x1) << GPIO_PMR0T_P3_Pos) 855 #define GPIO_PMR0T_P4_Pos 4 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 856 #define GPIO_PMR0T_P4 (_U_(0x1) << GPIO_PMR0T_P4_Pos) 857 #define GPIO_PMR0T_P5_Pos 5 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 858 #define GPIO_PMR0T_P5 (_U_(0x1) << GPIO_PMR0T_P5_Pos) 859 #define GPIO_PMR0T_P6_Pos 6 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 860 #define GPIO_PMR0T_P6 (_U_(0x1) << GPIO_PMR0T_P6_Pos) 861 #define GPIO_PMR0T_P7_Pos 7 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 862 #define GPIO_PMR0T_P7 (_U_(0x1) << GPIO_PMR0T_P7_Pos) 863 #define GPIO_PMR0T_P8_Pos 8 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 864 #define GPIO_PMR0T_P8 (_U_(0x1) << GPIO_PMR0T_P8_Pos) 865 #define GPIO_PMR0T_P9_Pos 9 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 866 #define GPIO_PMR0T_P9 (_U_(0x1) << GPIO_PMR0T_P9_Pos) 867 #define GPIO_PMR0T_P10_Pos 10 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 868 #define GPIO_PMR0T_P10 (_U_(0x1) << GPIO_PMR0T_P10_Pos) 869 #define GPIO_PMR0T_P11_Pos 11 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 870 #define GPIO_PMR0T_P11 (_U_(0x1) << GPIO_PMR0T_P11_Pos) 871 #define GPIO_PMR0T_P12_Pos 12 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 872 #define GPIO_PMR0T_P12 (_U_(0x1) << GPIO_PMR0T_P12_Pos) 873 #define GPIO_PMR0T_P13_Pos 13 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 874 #define GPIO_PMR0T_P13 (_U_(0x1) << GPIO_PMR0T_P13_Pos) 875 #define GPIO_PMR0T_P14_Pos 14 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 876 #define GPIO_PMR0T_P14 (_U_(0x1) << GPIO_PMR0T_P14_Pos) 877 #define GPIO_PMR0T_P15_Pos 15 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 878 #define GPIO_PMR0T_P15 (_U_(0x1) << GPIO_PMR0T_P15_Pos) 879 #define GPIO_PMR0T_P16_Pos 16 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 880 #define GPIO_PMR0T_P16 (_U_(0x1) << GPIO_PMR0T_P16_Pos) 881 #define GPIO_PMR0T_P17_Pos 17 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 882 #define GPIO_PMR0T_P17 (_U_(0x1) << GPIO_PMR0T_P17_Pos) 883 #define GPIO_PMR0T_P18_Pos 18 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 884 #define GPIO_PMR0T_P18 (_U_(0x1) << GPIO_PMR0T_P18_Pos) 885 #define GPIO_PMR0T_P19_Pos 19 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 886 #define GPIO_PMR0T_P19 (_U_(0x1) << GPIO_PMR0T_P19_Pos) 887 #define GPIO_PMR0T_P20_Pos 20 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 888 #define GPIO_PMR0T_P20 (_U_(0x1) << GPIO_PMR0T_P20_Pos) 889 #define GPIO_PMR0T_P21_Pos 21 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 890 #define GPIO_PMR0T_P21 (_U_(0x1) << GPIO_PMR0T_P21_Pos) 891 #define GPIO_PMR0T_P22_Pos 22 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 892 #define GPIO_PMR0T_P22 (_U_(0x1) << GPIO_PMR0T_P22_Pos) 893 #define GPIO_PMR0T_P23_Pos 23 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 894 #define GPIO_PMR0T_P23 (_U_(0x1) << GPIO_PMR0T_P23_Pos) 895 #define GPIO_PMR0T_P24_Pos 24 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 896 #define GPIO_PMR0T_P24 (_U_(0x1) << GPIO_PMR0T_P24_Pos) 897 #define GPIO_PMR0T_P25_Pos 25 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 898 #define GPIO_PMR0T_P25 (_U_(0x1) << GPIO_PMR0T_P25_Pos) 899 #define GPIO_PMR0T_P26_Pos 26 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 900 #define GPIO_PMR0T_P26 (_U_(0x1) << GPIO_PMR0T_P26_Pos) 901 #define GPIO_PMR0T_P27_Pos 27 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 902 #define GPIO_PMR0T_P27 (_U_(0x1) << GPIO_PMR0T_P27_Pos) 903 #define GPIO_PMR0T_P28_Pos 28 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 904 #define GPIO_PMR0T_P28 (_U_(0x1) << GPIO_PMR0T_P28_Pos) 905 #define GPIO_PMR0T_P29_Pos 29 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 906 #define GPIO_PMR0T_P29 (_U_(0x1) << GPIO_PMR0T_P29_Pos) 907 #define GPIO_PMR0T_P30_Pos 30 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 908 #define GPIO_PMR0T_P30 (_U_(0x1) << GPIO_PMR0T_P30_Pos) 909 #define GPIO_PMR0T_P31_Pos 31 /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */ 910 #define GPIO_PMR0T_P31 (_U_(0x1) << GPIO_PMR0T_P31_Pos) 911 #define GPIO_PMR0T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR0T) MASK Register */ 912 913 /* -------- GPIO_PMR1 : (GPIO Offset: 0x020) (R/W 32) port Peripheral Mux Register 1 -------- */ 914 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 915 typedef union { 916 struct { 917 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 1 */ 918 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 1 */ 919 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 1 */ 920 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 1 */ 921 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 1 */ 922 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 1 */ 923 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 1 */ 924 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 1 */ 925 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 1 */ 926 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 1 */ 927 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 1 */ 928 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 1 */ 929 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 1 */ 930 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 1 */ 931 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 1 */ 932 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 1 */ 933 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 1 */ 934 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 1 */ 935 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 1 */ 936 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 1 */ 937 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 1 */ 938 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 1 */ 939 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 1 */ 940 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 1 */ 941 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 1 */ 942 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 1 */ 943 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 1 */ 944 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 1 */ 945 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 1 */ 946 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 1 */ 947 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 1 */ 948 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 1 */ 949 } bit; /*!< Structure used for bit access */ 950 uint32_t reg; /*!< Type used for register access */ 951 } GPIO_PMR1_Type; 952 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 953 954 #define GPIO_PMR1_OFFSET 0x020 /**< \brief (GPIO_PMR1 offset) Peripheral Mux Register 1 */ 955 956 #define GPIO_PMR1_P0_Pos 0 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 957 #define GPIO_PMR1_P0 (_U_(0x1) << GPIO_PMR1_P0_Pos) 958 #define GPIO_PMR1_P1_Pos 1 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 959 #define GPIO_PMR1_P1 (_U_(0x1) << GPIO_PMR1_P1_Pos) 960 #define GPIO_PMR1_P2_Pos 2 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 961 #define GPIO_PMR1_P2 (_U_(0x1) << GPIO_PMR1_P2_Pos) 962 #define GPIO_PMR1_P3_Pos 3 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 963 #define GPIO_PMR1_P3 (_U_(0x1) << GPIO_PMR1_P3_Pos) 964 #define GPIO_PMR1_P4_Pos 4 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 965 #define GPIO_PMR1_P4 (_U_(0x1) << GPIO_PMR1_P4_Pos) 966 #define GPIO_PMR1_P5_Pos 5 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 967 #define GPIO_PMR1_P5 (_U_(0x1) << GPIO_PMR1_P5_Pos) 968 #define GPIO_PMR1_P6_Pos 6 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 969 #define GPIO_PMR1_P6 (_U_(0x1) << GPIO_PMR1_P6_Pos) 970 #define GPIO_PMR1_P7_Pos 7 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 971 #define GPIO_PMR1_P7 (_U_(0x1) << GPIO_PMR1_P7_Pos) 972 #define GPIO_PMR1_P8_Pos 8 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 973 #define GPIO_PMR1_P8 (_U_(0x1) << GPIO_PMR1_P8_Pos) 974 #define GPIO_PMR1_P9_Pos 9 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 975 #define GPIO_PMR1_P9 (_U_(0x1) << GPIO_PMR1_P9_Pos) 976 #define GPIO_PMR1_P10_Pos 10 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 977 #define GPIO_PMR1_P10 (_U_(0x1) << GPIO_PMR1_P10_Pos) 978 #define GPIO_PMR1_P11_Pos 11 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 979 #define GPIO_PMR1_P11 (_U_(0x1) << GPIO_PMR1_P11_Pos) 980 #define GPIO_PMR1_P12_Pos 12 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 981 #define GPIO_PMR1_P12 (_U_(0x1) << GPIO_PMR1_P12_Pos) 982 #define GPIO_PMR1_P13_Pos 13 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 983 #define GPIO_PMR1_P13 (_U_(0x1) << GPIO_PMR1_P13_Pos) 984 #define GPIO_PMR1_P14_Pos 14 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 985 #define GPIO_PMR1_P14 (_U_(0x1) << GPIO_PMR1_P14_Pos) 986 #define GPIO_PMR1_P15_Pos 15 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 987 #define GPIO_PMR1_P15 (_U_(0x1) << GPIO_PMR1_P15_Pos) 988 #define GPIO_PMR1_P16_Pos 16 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 989 #define GPIO_PMR1_P16 (_U_(0x1) << GPIO_PMR1_P16_Pos) 990 #define GPIO_PMR1_P17_Pos 17 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 991 #define GPIO_PMR1_P17 (_U_(0x1) << GPIO_PMR1_P17_Pos) 992 #define GPIO_PMR1_P18_Pos 18 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 993 #define GPIO_PMR1_P18 (_U_(0x1) << GPIO_PMR1_P18_Pos) 994 #define GPIO_PMR1_P19_Pos 19 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 995 #define GPIO_PMR1_P19 (_U_(0x1) << GPIO_PMR1_P19_Pos) 996 #define GPIO_PMR1_P20_Pos 20 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 997 #define GPIO_PMR1_P20 (_U_(0x1) << GPIO_PMR1_P20_Pos) 998 #define GPIO_PMR1_P21_Pos 21 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 999 #define GPIO_PMR1_P21 (_U_(0x1) << GPIO_PMR1_P21_Pos) 1000 #define GPIO_PMR1_P22_Pos 22 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1001 #define GPIO_PMR1_P22 (_U_(0x1) << GPIO_PMR1_P22_Pos) 1002 #define GPIO_PMR1_P23_Pos 23 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1003 #define GPIO_PMR1_P23 (_U_(0x1) << GPIO_PMR1_P23_Pos) 1004 #define GPIO_PMR1_P24_Pos 24 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1005 #define GPIO_PMR1_P24 (_U_(0x1) << GPIO_PMR1_P24_Pos) 1006 #define GPIO_PMR1_P25_Pos 25 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1007 #define GPIO_PMR1_P25 (_U_(0x1) << GPIO_PMR1_P25_Pos) 1008 #define GPIO_PMR1_P26_Pos 26 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1009 #define GPIO_PMR1_P26 (_U_(0x1) << GPIO_PMR1_P26_Pos) 1010 #define GPIO_PMR1_P27_Pos 27 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1011 #define GPIO_PMR1_P27 (_U_(0x1) << GPIO_PMR1_P27_Pos) 1012 #define GPIO_PMR1_P28_Pos 28 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1013 #define GPIO_PMR1_P28 (_U_(0x1) << GPIO_PMR1_P28_Pos) 1014 #define GPIO_PMR1_P29_Pos 29 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1015 #define GPIO_PMR1_P29 (_U_(0x1) << GPIO_PMR1_P29_Pos) 1016 #define GPIO_PMR1_P30_Pos 30 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1017 #define GPIO_PMR1_P30 (_U_(0x1) << GPIO_PMR1_P30_Pos) 1018 #define GPIO_PMR1_P31_Pos 31 /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */ 1019 #define GPIO_PMR1_P31 (_U_(0x1) << GPIO_PMR1_P31_Pos) 1020 #define GPIO_PMR1_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR1) MASK Register */ 1021 1022 /* -------- GPIO_PMR1S : (GPIO Offset: 0x024) ( /W 32) port Peripheral Mux Register 1 - Set -------- */ 1023 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1024 typedef union { 1025 struct { 1026 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 1 */ 1027 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 1 */ 1028 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 1 */ 1029 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 1 */ 1030 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 1 */ 1031 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 1 */ 1032 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 1 */ 1033 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 1 */ 1034 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 1 */ 1035 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 1 */ 1036 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 1 */ 1037 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 1 */ 1038 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 1 */ 1039 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 1 */ 1040 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 1 */ 1041 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 1 */ 1042 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 1 */ 1043 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 1 */ 1044 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 1 */ 1045 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 1 */ 1046 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 1 */ 1047 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 1 */ 1048 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 1 */ 1049 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 1 */ 1050 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 1 */ 1051 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 1 */ 1052 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 1 */ 1053 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 1 */ 1054 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 1 */ 1055 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 1 */ 1056 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 1 */ 1057 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 1 */ 1058 } bit; /*!< Structure used for bit access */ 1059 uint32_t reg; /*!< Type used for register access */ 1060 } GPIO_PMR1S_Type; 1061 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1062 1063 #define GPIO_PMR1S_OFFSET 0x024 /**< \brief (GPIO_PMR1S offset) Peripheral Mux Register 1 - Set */ 1064 1065 #define GPIO_PMR1S_P0_Pos 0 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1066 #define GPIO_PMR1S_P0 (_U_(0x1) << GPIO_PMR1S_P0_Pos) 1067 #define GPIO_PMR1S_P1_Pos 1 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1068 #define GPIO_PMR1S_P1 (_U_(0x1) << GPIO_PMR1S_P1_Pos) 1069 #define GPIO_PMR1S_P2_Pos 2 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1070 #define GPIO_PMR1S_P2 (_U_(0x1) << GPIO_PMR1S_P2_Pos) 1071 #define GPIO_PMR1S_P3_Pos 3 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1072 #define GPIO_PMR1S_P3 (_U_(0x1) << GPIO_PMR1S_P3_Pos) 1073 #define GPIO_PMR1S_P4_Pos 4 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1074 #define GPIO_PMR1S_P4 (_U_(0x1) << GPIO_PMR1S_P4_Pos) 1075 #define GPIO_PMR1S_P5_Pos 5 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1076 #define GPIO_PMR1S_P5 (_U_(0x1) << GPIO_PMR1S_P5_Pos) 1077 #define GPIO_PMR1S_P6_Pos 6 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1078 #define GPIO_PMR1S_P6 (_U_(0x1) << GPIO_PMR1S_P6_Pos) 1079 #define GPIO_PMR1S_P7_Pos 7 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1080 #define GPIO_PMR1S_P7 (_U_(0x1) << GPIO_PMR1S_P7_Pos) 1081 #define GPIO_PMR1S_P8_Pos 8 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1082 #define GPIO_PMR1S_P8 (_U_(0x1) << GPIO_PMR1S_P8_Pos) 1083 #define GPIO_PMR1S_P9_Pos 9 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1084 #define GPIO_PMR1S_P9 (_U_(0x1) << GPIO_PMR1S_P9_Pos) 1085 #define GPIO_PMR1S_P10_Pos 10 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1086 #define GPIO_PMR1S_P10 (_U_(0x1) << GPIO_PMR1S_P10_Pos) 1087 #define GPIO_PMR1S_P11_Pos 11 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1088 #define GPIO_PMR1S_P11 (_U_(0x1) << GPIO_PMR1S_P11_Pos) 1089 #define GPIO_PMR1S_P12_Pos 12 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1090 #define GPIO_PMR1S_P12 (_U_(0x1) << GPIO_PMR1S_P12_Pos) 1091 #define GPIO_PMR1S_P13_Pos 13 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1092 #define GPIO_PMR1S_P13 (_U_(0x1) << GPIO_PMR1S_P13_Pos) 1093 #define GPIO_PMR1S_P14_Pos 14 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1094 #define GPIO_PMR1S_P14 (_U_(0x1) << GPIO_PMR1S_P14_Pos) 1095 #define GPIO_PMR1S_P15_Pos 15 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1096 #define GPIO_PMR1S_P15 (_U_(0x1) << GPIO_PMR1S_P15_Pos) 1097 #define GPIO_PMR1S_P16_Pos 16 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1098 #define GPIO_PMR1S_P16 (_U_(0x1) << GPIO_PMR1S_P16_Pos) 1099 #define GPIO_PMR1S_P17_Pos 17 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1100 #define GPIO_PMR1S_P17 (_U_(0x1) << GPIO_PMR1S_P17_Pos) 1101 #define GPIO_PMR1S_P18_Pos 18 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1102 #define GPIO_PMR1S_P18 (_U_(0x1) << GPIO_PMR1S_P18_Pos) 1103 #define GPIO_PMR1S_P19_Pos 19 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1104 #define GPIO_PMR1S_P19 (_U_(0x1) << GPIO_PMR1S_P19_Pos) 1105 #define GPIO_PMR1S_P20_Pos 20 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1106 #define GPIO_PMR1S_P20 (_U_(0x1) << GPIO_PMR1S_P20_Pos) 1107 #define GPIO_PMR1S_P21_Pos 21 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1108 #define GPIO_PMR1S_P21 (_U_(0x1) << GPIO_PMR1S_P21_Pos) 1109 #define GPIO_PMR1S_P22_Pos 22 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1110 #define GPIO_PMR1S_P22 (_U_(0x1) << GPIO_PMR1S_P22_Pos) 1111 #define GPIO_PMR1S_P23_Pos 23 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1112 #define GPIO_PMR1S_P23 (_U_(0x1) << GPIO_PMR1S_P23_Pos) 1113 #define GPIO_PMR1S_P24_Pos 24 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1114 #define GPIO_PMR1S_P24 (_U_(0x1) << GPIO_PMR1S_P24_Pos) 1115 #define GPIO_PMR1S_P25_Pos 25 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1116 #define GPIO_PMR1S_P25 (_U_(0x1) << GPIO_PMR1S_P25_Pos) 1117 #define GPIO_PMR1S_P26_Pos 26 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1118 #define GPIO_PMR1S_P26 (_U_(0x1) << GPIO_PMR1S_P26_Pos) 1119 #define GPIO_PMR1S_P27_Pos 27 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1120 #define GPIO_PMR1S_P27 (_U_(0x1) << GPIO_PMR1S_P27_Pos) 1121 #define GPIO_PMR1S_P28_Pos 28 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1122 #define GPIO_PMR1S_P28 (_U_(0x1) << GPIO_PMR1S_P28_Pos) 1123 #define GPIO_PMR1S_P29_Pos 29 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1124 #define GPIO_PMR1S_P29 (_U_(0x1) << GPIO_PMR1S_P29_Pos) 1125 #define GPIO_PMR1S_P30_Pos 30 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1126 #define GPIO_PMR1S_P30 (_U_(0x1) << GPIO_PMR1S_P30_Pos) 1127 #define GPIO_PMR1S_P31_Pos 31 /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */ 1128 #define GPIO_PMR1S_P31 (_U_(0x1) << GPIO_PMR1S_P31_Pos) 1129 #define GPIO_PMR1S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR1S) MASK Register */ 1130 1131 /* -------- GPIO_PMR1C : (GPIO Offset: 0x028) ( /W 32) port Peripheral Mux Register 1 - Clear -------- */ 1132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1133 typedef union { 1134 struct { 1135 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 1 */ 1136 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 1 */ 1137 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 1 */ 1138 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 1 */ 1139 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 1 */ 1140 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 1 */ 1141 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 1 */ 1142 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 1 */ 1143 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 1 */ 1144 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 1 */ 1145 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 1 */ 1146 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 1 */ 1147 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 1 */ 1148 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 1 */ 1149 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 1 */ 1150 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 1 */ 1151 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 1 */ 1152 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 1 */ 1153 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 1 */ 1154 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 1 */ 1155 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 1 */ 1156 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 1 */ 1157 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 1 */ 1158 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 1 */ 1159 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 1 */ 1160 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 1 */ 1161 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 1 */ 1162 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 1 */ 1163 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 1 */ 1164 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 1 */ 1165 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 1 */ 1166 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 1 */ 1167 } bit; /*!< Structure used for bit access */ 1168 uint32_t reg; /*!< Type used for register access */ 1169 } GPIO_PMR1C_Type; 1170 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1171 1172 #define GPIO_PMR1C_OFFSET 0x028 /**< \brief (GPIO_PMR1C offset) Peripheral Mux Register 1 - Clear */ 1173 1174 #define GPIO_PMR1C_P0_Pos 0 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1175 #define GPIO_PMR1C_P0 (_U_(0x1) << GPIO_PMR1C_P0_Pos) 1176 #define GPIO_PMR1C_P1_Pos 1 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1177 #define GPIO_PMR1C_P1 (_U_(0x1) << GPIO_PMR1C_P1_Pos) 1178 #define GPIO_PMR1C_P2_Pos 2 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1179 #define GPIO_PMR1C_P2 (_U_(0x1) << GPIO_PMR1C_P2_Pos) 1180 #define GPIO_PMR1C_P3_Pos 3 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1181 #define GPIO_PMR1C_P3 (_U_(0x1) << GPIO_PMR1C_P3_Pos) 1182 #define GPIO_PMR1C_P4_Pos 4 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1183 #define GPIO_PMR1C_P4 (_U_(0x1) << GPIO_PMR1C_P4_Pos) 1184 #define GPIO_PMR1C_P5_Pos 5 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1185 #define GPIO_PMR1C_P5 (_U_(0x1) << GPIO_PMR1C_P5_Pos) 1186 #define GPIO_PMR1C_P6_Pos 6 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1187 #define GPIO_PMR1C_P6 (_U_(0x1) << GPIO_PMR1C_P6_Pos) 1188 #define GPIO_PMR1C_P7_Pos 7 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1189 #define GPIO_PMR1C_P7 (_U_(0x1) << GPIO_PMR1C_P7_Pos) 1190 #define GPIO_PMR1C_P8_Pos 8 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1191 #define GPIO_PMR1C_P8 (_U_(0x1) << GPIO_PMR1C_P8_Pos) 1192 #define GPIO_PMR1C_P9_Pos 9 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1193 #define GPIO_PMR1C_P9 (_U_(0x1) << GPIO_PMR1C_P9_Pos) 1194 #define GPIO_PMR1C_P10_Pos 10 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1195 #define GPIO_PMR1C_P10 (_U_(0x1) << GPIO_PMR1C_P10_Pos) 1196 #define GPIO_PMR1C_P11_Pos 11 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1197 #define GPIO_PMR1C_P11 (_U_(0x1) << GPIO_PMR1C_P11_Pos) 1198 #define GPIO_PMR1C_P12_Pos 12 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1199 #define GPIO_PMR1C_P12 (_U_(0x1) << GPIO_PMR1C_P12_Pos) 1200 #define GPIO_PMR1C_P13_Pos 13 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1201 #define GPIO_PMR1C_P13 (_U_(0x1) << GPIO_PMR1C_P13_Pos) 1202 #define GPIO_PMR1C_P14_Pos 14 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1203 #define GPIO_PMR1C_P14 (_U_(0x1) << GPIO_PMR1C_P14_Pos) 1204 #define GPIO_PMR1C_P15_Pos 15 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1205 #define GPIO_PMR1C_P15 (_U_(0x1) << GPIO_PMR1C_P15_Pos) 1206 #define GPIO_PMR1C_P16_Pos 16 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1207 #define GPIO_PMR1C_P16 (_U_(0x1) << GPIO_PMR1C_P16_Pos) 1208 #define GPIO_PMR1C_P17_Pos 17 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1209 #define GPIO_PMR1C_P17 (_U_(0x1) << GPIO_PMR1C_P17_Pos) 1210 #define GPIO_PMR1C_P18_Pos 18 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1211 #define GPIO_PMR1C_P18 (_U_(0x1) << GPIO_PMR1C_P18_Pos) 1212 #define GPIO_PMR1C_P19_Pos 19 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1213 #define GPIO_PMR1C_P19 (_U_(0x1) << GPIO_PMR1C_P19_Pos) 1214 #define GPIO_PMR1C_P20_Pos 20 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1215 #define GPIO_PMR1C_P20 (_U_(0x1) << GPIO_PMR1C_P20_Pos) 1216 #define GPIO_PMR1C_P21_Pos 21 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1217 #define GPIO_PMR1C_P21 (_U_(0x1) << GPIO_PMR1C_P21_Pos) 1218 #define GPIO_PMR1C_P22_Pos 22 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1219 #define GPIO_PMR1C_P22 (_U_(0x1) << GPIO_PMR1C_P22_Pos) 1220 #define GPIO_PMR1C_P23_Pos 23 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1221 #define GPIO_PMR1C_P23 (_U_(0x1) << GPIO_PMR1C_P23_Pos) 1222 #define GPIO_PMR1C_P24_Pos 24 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1223 #define GPIO_PMR1C_P24 (_U_(0x1) << GPIO_PMR1C_P24_Pos) 1224 #define GPIO_PMR1C_P25_Pos 25 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1225 #define GPIO_PMR1C_P25 (_U_(0x1) << GPIO_PMR1C_P25_Pos) 1226 #define GPIO_PMR1C_P26_Pos 26 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1227 #define GPIO_PMR1C_P26 (_U_(0x1) << GPIO_PMR1C_P26_Pos) 1228 #define GPIO_PMR1C_P27_Pos 27 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1229 #define GPIO_PMR1C_P27 (_U_(0x1) << GPIO_PMR1C_P27_Pos) 1230 #define GPIO_PMR1C_P28_Pos 28 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1231 #define GPIO_PMR1C_P28 (_U_(0x1) << GPIO_PMR1C_P28_Pos) 1232 #define GPIO_PMR1C_P29_Pos 29 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1233 #define GPIO_PMR1C_P29 (_U_(0x1) << GPIO_PMR1C_P29_Pos) 1234 #define GPIO_PMR1C_P30_Pos 30 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1235 #define GPIO_PMR1C_P30 (_U_(0x1) << GPIO_PMR1C_P30_Pos) 1236 #define GPIO_PMR1C_P31_Pos 31 /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */ 1237 #define GPIO_PMR1C_P31 (_U_(0x1) << GPIO_PMR1C_P31_Pos) 1238 #define GPIO_PMR1C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR1C) MASK Register */ 1239 1240 /* -------- GPIO_PMR1T : (GPIO Offset: 0x02C) ( /W 32) port Peripheral Mux Register 1 - Toggle -------- */ 1241 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1242 typedef union { 1243 struct { 1244 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 1 */ 1245 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 1 */ 1246 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 1 */ 1247 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 1 */ 1248 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 1 */ 1249 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 1 */ 1250 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 1 */ 1251 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 1 */ 1252 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 1 */ 1253 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 1 */ 1254 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 1 */ 1255 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 1 */ 1256 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 1 */ 1257 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 1 */ 1258 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 1 */ 1259 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 1 */ 1260 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 1 */ 1261 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 1 */ 1262 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 1 */ 1263 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 1 */ 1264 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 1 */ 1265 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 1 */ 1266 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 1 */ 1267 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 1 */ 1268 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 1 */ 1269 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 1 */ 1270 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 1 */ 1271 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 1 */ 1272 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 1 */ 1273 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 1 */ 1274 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 1 */ 1275 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 1 */ 1276 } bit; /*!< Structure used for bit access */ 1277 uint32_t reg; /*!< Type used for register access */ 1278 } GPIO_PMR1T_Type; 1279 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1280 1281 #define GPIO_PMR1T_OFFSET 0x02C /**< \brief (GPIO_PMR1T offset) Peripheral Mux Register 1 - Toggle */ 1282 1283 #define GPIO_PMR1T_P0_Pos 0 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1284 #define GPIO_PMR1T_P0 (_U_(0x1) << GPIO_PMR1T_P0_Pos) 1285 #define GPIO_PMR1T_P1_Pos 1 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1286 #define GPIO_PMR1T_P1 (_U_(0x1) << GPIO_PMR1T_P1_Pos) 1287 #define GPIO_PMR1T_P2_Pos 2 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1288 #define GPIO_PMR1T_P2 (_U_(0x1) << GPIO_PMR1T_P2_Pos) 1289 #define GPIO_PMR1T_P3_Pos 3 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1290 #define GPIO_PMR1T_P3 (_U_(0x1) << GPIO_PMR1T_P3_Pos) 1291 #define GPIO_PMR1T_P4_Pos 4 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1292 #define GPIO_PMR1T_P4 (_U_(0x1) << GPIO_PMR1T_P4_Pos) 1293 #define GPIO_PMR1T_P5_Pos 5 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1294 #define GPIO_PMR1T_P5 (_U_(0x1) << GPIO_PMR1T_P5_Pos) 1295 #define GPIO_PMR1T_P6_Pos 6 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1296 #define GPIO_PMR1T_P6 (_U_(0x1) << GPIO_PMR1T_P6_Pos) 1297 #define GPIO_PMR1T_P7_Pos 7 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1298 #define GPIO_PMR1T_P7 (_U_(0x1) << GPIO_PMR1T_P7_Pos) 1299 #define GPIO_PMR1T_P8_Pos 8 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1300 #define GPIO_PMR1T_P8 (_U_(0x1) << GPIO_PMR1T_P8_Pos) 1301 #define GPIO_PMR1T_P9_Pos 9 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1302 #define GPIO_PMR1T_P9 (_U_(0x1) << GPIO_PMR1T_P9_Pos) 1303 #define GPIO_PMR1T_P10_Pos 10 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1304 #define GPIO_PMR1T_P10 (_U_(0x1) << GPIO_PMR1T_P10_Pos) 1305 #define GPIO_PMR1T_P11_Pos 11 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1306 #define GPIO_PMR1T_P11 (_U_(0x1) << GPIO_PMR1T_P11_Pos) 1307 #define GPIO_PMR1T_P12_Pos 12 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1308 #define GPIO_PMR1T_P12 (_U_(0x1) << GPIO_PMR1T_P12_Pos) 1309 #define GPIO_PMR1T_P13_Pos 13 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1310 #define GPIO_PMR1T_P13 (_U_(0x1) << GPIO_PMR1T_P13_Pos) 1311 #define GPIO_PMR1T_P14_Pos 14 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1312 #define GPIO_PMR1T_P14 (_U_(0x1) << GPIO_PMR1T_P14_Pos) 1313 #define GPIO_PMR1T_P15_Pos 15 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1314 #define GPIO_PMR1T_P15 (_U_(0x1) << GPIO_PMR1T_P15_Pos) 1315 #define GPIO_PMR1T_P16_Pos 16 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1316 #define GPIO_PMR1T_P16 (_U_(0x1) << GPIO_PMR1T_P16_Pos) 1317 #define GPIO_PMR1T_P17_Pos 17 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1318 #define GPIO_PMR1T_P17 (_U_(0x1) << GPIO_PMR1T_P17_Pos) 1319 #define GPIO_PMR1T_P18_Pos 18 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1320 #define GPIO_PMR1T_P18 (_U_(0x1) << GPIO_PMR1T_P18_Pos) 1321 #define GPIO_PMR1T_P19_Pos 19 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1322 #define GPIO_PMR1T_P19 (_U_(0x1) << GPIO_PMR1T_P19_Pos) 1323 #define GPIO_PMR1T_P20_Pos 20 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1324 #define GPIO_PMR1T_P20 (_U_(0x1) << GPIO_PMR1T_P20_Pos) 1325 #define GPIO_PMR1T_P21_Pos 21 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1326 #define GPIO_PMR1T_P21 (_U_(0x1) << GPIO_PMR1T_P21_Pos) 1327 #define GPIO_PMR1T_P22_Pos 22 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1328 #define GPIO_PMR1T_P22 (_U_(0x1) << GPIO_PMR1T_P22_Pos) 1329 #define GPIO_PMR1T_P23_Pos 23 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1330 #define GPIO_PMR1T_P23 (_U_(0x1) << GPIO_PMR1T_P23_Pos) 1331 #define GPIO_PMR1T_P24_Pos 24 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1332 #define GPIO_PMR1T_P24 (_U_(0x1) << GPIO_PMR1T_P24_Pos) 1333 #define GPIO_PMR1T_P25_Pos 25 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1334 #define GPIO_PMR1T_P25 (_U_(0x1) << GPIO_PMR1T_P25_Pos) 1335 #define GPIO_PMR1T_P26_Pos 26 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1336 #define GPIO_PMR1T_P26 (_U_(0x1) << GPIO_PMR1T_P26_Pos) 1337 #define GPIO_PMR1T_P27_Pos 27 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1338 #define GPIO_PMR1T_P27 (_U_(0x1) << GPIO_PMR1T_P27_Pos) 1339 #define GPIO_PMR1T_P28_Pos 28 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1340 #define GPIO_PMR1T_P28 (_U_(0x1) << GPIO_PMR1T_P28_Pos) 1341 #define GPIO_PMR1T_P29_Pos 29 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1342 #define GPIO_PMR1T_P29 (_U_(0x1) << GPIO_PMR1T_P29_Pos) 1343 #define GPIO_PMR1T_P30_Pos 30 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1344 #define GPIO_PMR1T_P30 (_U_(0x1) << GPIO_PMR1T_P30_Pos) 1345 #define GPIO_PMR1T_P31_Pos 31 /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */ 1346 #define GPIO_PMR1T_P31 (_U_(0x1) << GPIO_PMR1T_P31_Pos) 1347 #define GPIO_PMR1T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR1T) MASK Register */ 1348 1349 /* -------- GPIO_PMR2 : (GPIO Offset: 0x030) (R/W 32) port Peripheral Mux Register 2 -------- */ 1350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1351 typedef union { 1352 struct { 1353 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 2 */ 1354 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 2 */ 1355 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 2 */ 1356 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 2 */ 1357 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 2 */ 1358 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 2 */ 1359 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 2 */ 1360 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 2 */ 1361 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 2 */ 1362 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 2 */ 1363 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 2 */ 1364 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 2 */ 1365 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 2 */ 1366 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 2 */ 1367 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 2 */ 1368 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 2 */ 1369 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 2 */ 1370 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 2 */ 1371 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 2 */ 1372 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 2 */ 1373 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 2 */ 1374 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 2 */ 1375 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 2 */ 1376 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 2 */ 1377 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 2 */ 1378 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 2 */ 1379 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 2 */ 1380 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 2 */ 1381 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 2 */ 1382 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 2 */ 1383 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 2 */ 1384 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 2 */ 1385 } bit; /*!< Structure used for bit access */ 1386 uint32_t reg; /*!< Type used for register access */ 1387 } GPIO_PMR2_Type; 1388 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1389 1390 #define GPIO_PMR2_OFFSET 0x030 /**< \brief (GPIO_PMR2 offset) Peripheral Mux Register 2 */ 1391 1392 #define GPIO_PMR2_P0_Pos 0 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1393 #define GPIO_PMR2_P0 (_U_(0x1) << GPIO_PMR2_P0_Pos) 1394 #define GPIO_PMR2_P1_Pos 1 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1395 #define GPIO_PMR2_P1 (_U_(0x1) << GPIO_PMR2_P1_Pos) 1396 #define GPIO_PMR2_P2_Pos 2 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1397 #define GPIO_PMR2_P2 (_U_(0x1) << GPIO_PMR2_P2_Pos) 1398 #define GPIO_PMR2_P3_Pos 3 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1399 #define GPIO_PMR2_P3 (_U_(0x1) << GPIO_PMR2_P3_Pos) 1400 #define GPIO_PMR2_P4_Pos 4 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1401 #define GPIO_PMR2_P4 (_U_(0x1) << GPIO_PMR2_P4_Pos) 1402 #define GPIO_PMR2_P5_Pos 5 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1403 #define GPIO_PMR2_P5 (_U_(0x1) << GPIO_PMR2_P5_Pos) 1404 #define GPIO_PMR2_P6_Pos 6 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1405 #define GPIO_PMR2_P6 (_U_(0x1) << GPIO_PMR2_P6_Pos) 1406 #define GPIO_PMR2_P7_Pos 7 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1407 #define GPIO_PMR2_P7 (_U_(0x1) << GPIO_PMR2_P7_Pos) 1408 #define GPIO_PMR2_P8_Pos 8 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1409 #define GPIO_PMR2_P8 (_U_(0x1) << GPIO_PMR2_P8_Pos) 1410 #define GPIO_PMR2_P9_Pos 9 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1411 #define GPIO_PMR2_P9 (_U_(0x1) << GPIO_PMR2_P9_Pos) 1412 #define GPIO_PMR2_P10_Pos 10 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1413 #define GPIO_PMR2_P10 (_U_(0x1) << GPIO_PMR2_P10_Pos) 1414 #define GPIO_PMR2_P11_Pos 11 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1415 #define GPIO_PMR2_P11 (_U_(0x1) << GPIO_PMR2_P11_Pos) 1416 #define GPIO_PMR2_P12_Pos 12 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1417 #define GPIO_PMR2_P12 (_U_(0x1) << GPIO_PMR2_P12_Pos) 1418 #define GPIO_PMR2_P13_Pos 13 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1419 #define GPIO_PMR2_P13 (_U_(0x1) << GPIO_PMR2_P13_Pos) 1420 #define GPIO_PMR2_P14_Pos 14 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1421 #define GPIO_PMR2_P14 (_U_(0x1) << GPIO_PMR2_P14_Pos) 1422 #define GPIO_PMR2_P15_Pos 15 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1423 #define GPIO_PMR2_P15 (_U_(0x1) << GPIO_PMR2_P15_Pos) 1424 #define GPIO_PMR2_P16_Pos 16 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1425 #define GPIO_PMR2_P16 (_U_(0x1) << GPIO_PMR2_P16_Pos) 1426 #define GPIO_PMR2_P17_Pos 17 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1427 #define GPIO_PMR2_P17 (_U_(0x1) << GPIO_PMR2_P17_Pos) 1428 #define GPIO_PMR2_P18_Pos 18 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1429 #define GPIO_PMR2_P18 (_U_(0x1) << GPIO_PMR2_P18_Pos) 1430 #define GPIO_PMR2_P19_Pos 19 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1431 #define GPIO_PMR2_P19 (_U_(0x1) << GPIO_PMR2_P19_Pos) 1432 #define GPIO_PMR2_P20_Pos 20 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1433 #define GPIO_PMR2_P20 (_U_(0x1) << GPIO_PMR2_P20_Pos) 1434 #define GPIO_PMR2_P21_Pos 21 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1435 #define GPIO_PMR2_P21 (_U_(0x1) << GPIO_PMR2_P21_Pos) 1436 #define GPIO_PMR2_P22_Pos 22 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1437 #define GPIO_PMR2_P22 (_U_(0x1) << GPIO_PMR2_P22_Pos) 1438 #define GPIO_PMR2_P23_Pos 23 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1439 #define GPIO_PMR2_P23 (_U_(0x1) << GPIO_PMR2_P23_Pos) 1440 #define GPIO_PMR2_P24_Pos 24 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1441 #define GPIO_PMR2_P24 (_U_(0x1) << GPIO_PMR2_P24_Pos) 1442 #define GPIO_PMR2_P25_Pos 25 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1443 #define GPIO_PMR2_P25 (_U_(0x1) << GPIO_PMR2_P25_Pos) 1444 #define GPIO_PMR2_P26_Pos 26 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1445 #define GPIO_PMR2_P26 (_U_(0x1) << GPIO_PMR2_P26_Pos) 1446 #define GPIO_PMR2_P27_Pos 27 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1447 #define GPIO_PMR2_P27 (_U_(0x1) << GPIO_PMR2_P27_Pos) 1448 #define GPIO_PMR2_P28_Pos 28 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1449 #define GPIO_PMR2_P28 (_U_(0x1) << GPIO_PMR2_P28_Pos) 1450 #define GPIO_PMR2_P29_Pos 29 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1451 #define GPIO_PMR2_P29 (_U_(0x1) << GPIO_PMR2_P29_Pos) 1452 #define GPIO_PMR2_P30_Pos 30 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1453 #define GPIO_PMR2_P30 (_U_(0x1) << GPIO_PMR2_P30_Pos) 1454 #define GPIO_PMR2_P31_Pos 31 /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */ 1455 #define GPIO_PMR2_P31 (_U_(0x1) << GPIO_PMR2_P31_Pos) 1456 #define GPIO_PMR2_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR2) MASK Register */ 1457 1458 /* -------- GPIO_PMR2S : (GPIO Offset: 0x034) ( /W 32) port Peripheral Mux Register 2 - Set -------- */ 1459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1460 typedef union { 1461 struct { 1462 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 2 */ 1463 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 2 */ 1464 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 2 */ 1465 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 2 */ 1466 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 2 */ 1467 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 2 */ 1468 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 2 */ 1469 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 2 */ 1470 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 2 */ 1471 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 2 */ 1472 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 2 */ 1473 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 2 */ 1474 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 2 */ 1475 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 2 */ 1476 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 2 */ 1477 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 2 */ 1478 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 2 */ 1479 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 2 */ 1480 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 2 */ 1481 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 2 */ 1482 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 2 */ 1483 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 2 */ 1484 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 2 */ 1485 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 2 */ 1486 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 2 */ 1487 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 2 */ 1488 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 2 */ 1489 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 2 */ 1490 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 2 */ 1491 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 2 */ 1492 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 2 */ 1493 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 2 */ 1494 } bit; /*!< Structure used for bit access */ 1495 uint32_t reg; /*!< Type used for register access */ 1496 } GPIO_PMR2S_Type; 1497 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1498 1499 #define GPIO_PMR2S_OFFSET 0x034 /**< \brief (GPIO_PMR2S offset) Peripheral Mux Register 2 - Set */ 1500 1501 #define GPIO_PMR2S_P0_Pos 0 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1502 #define GPIO_PMR2S_P0 (_U_(0x1) << GPIO_PMR2S_P0_Pos) 1503 #define GPIO_PMR2S_P1_Pos 1 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1504 #define GPIO_PMR2S_P1 (_U_(0x1) << GPIO_PMR2S_P1_Pos) 1505 #define GPIO_PMR2S_P2_Pos 2 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1506 #define GPIO_PMR2S_P2 (_U_(0x1) << GPIO_PMR2S_P2_Pos) 1507 #define GPIO_PMR2S_P3_Pos 3 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1508 #define GPIO_PMR2S_P3 (_U_(0x1) << GPIO_PMR2S_P3_Pos) 1509 #define GPIO_PMR2S_P4_Pos 4 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1510 #define GPIO_PMR2S_P4 (_U_(0x1) << GPIO_PMR2S_P4_Pos) 1511 #define GPIO_PMR2S_P5_Pos 5 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1512 #define GPIO_PMR2S_P5 (_U_(0x1) << GPIO_PMR2S_P5_Pos) 1513 #define GPIO_PMR2S_P6_Pos 6 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1514 #define GPIO_PMR2S_P6 (_U_(0x1) << GPIO_PMR2S_P6_Pos) 1515 #define GPIO_PMR2S_P7_Pos 7 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1516 #define GPIO_PMR2S_P7 (_U_(0x1) << GPIO_PMR2S_P7_Pos) 1517 #define GPIO_PMR2S_P8_Pos 8 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1518 #define GPIO_PMR2S_P8 (_U_(0x1) << GPIO_PMR2S_P8_Pos) 1519 #define GPIO_PMR2S_P9_Pos 9 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1520 #define GPIO_PMR2S_P9 (_U_(0x1) << GPIO_PMR2S_P9_Pos) 1521 #define GPIO_PMR2S_P10_Pos 10 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1522 #define GPIO_PMR2S_P10 (_U_(0x1) << GPIO_PMR2S_P10_Pos) 1523 #define GPIO_PMR2S_P11_Pos 11 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1524 #define GPIO_PMR2S_P11 (_U_(0x1) << GPIO_PMR2S_P11_Pos) 1525 #define GPIO_PMR2S_P12_Pos 12 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1526 #define GPIO_PMR2S_P12 (_U_(0x1) << GPIO_PMR2S_P12_Pos) 1527 #define GPIO_PMR2S_P13_Pos 13 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1528 #define GPIO_PMR2S_P13 (_U_(0x1) << GPIO_PMR2S_P13_Pos) 1529 #define GPIO_PMR2S_P14_Pos 14 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1530 #define GPIO_PMR2S_P14 (_U_(0x1) << GPIO_PMR2S_P14_Pos) 1531 #define GPIO_PMR2S_P15_Pos 15 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1532 #define GPIO_PMR2S_P15 (_U_(0x1) << GPIO_PMR2S_P15_Pos) 1533 #define GPIO_PMR2S_P16_Pos 16 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1534 #define GPIO_PMR2S_P16 (_U_(0x1) << GPIO_PMR2S_P16_Pos) 1535 #define GPIO_PMR2S_P17_Pos 17 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1536 #define GPIO_PMR2S_P17 (_U_(0x1) << GPIO_PMR2S_P17_Pos) 1537 #define GPIO_PMR2S_P18_Pos 18 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1538 #define GPIO_PMR2S_P18 (_U_(0x1) << GPIO_PMR2S_P18_Pos) 1539 #define GPIO_PMR2S_P19_Pos 19 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1540 #define GPIO_PMR2S_P19 (_U_(0x1) << GPIO_PMR2S_P19_Pos) 1541 #define GPIO_PMR2S_P20_Pos 20 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1542 #define GPIO_PMR2S_P20 (_U_(0x1) << GPIO_PMR2S_P20_Pos) 1543 #define GPIO_PMR2S_P21_Pos 21 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1544 #define GPIO_PMR2S_P21 (_U_(0x1) << GPIO_PMR2S_P21_Pos) 1545 #define GPIO_PMR2S_P22_Pos 22 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1546 #define GPIO_PMR2S_P22 (_U_(0x1) << GPIO_PMR2S_P22_Pos) 1547 #define GPIO_PMR2S_P23_Pos 23 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1548 #define GPIO_PMR2S_P23 (_U_(0x1) << GPIO_PMR2S_P23_Pos) 1549 #define GPIO_PMR2S_P24_Pos 24 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1550 #define GPIO_PMR2S_P24 (_U_(0x1) << GPIO_PMR2S_P24_Pos) 1551 #define GPIO_PMR2S_P25_Pos 25 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1552 #define GPIO_PMR2S_P25 (_U_(0x1) << GPIO_PMR2S_P25_Pos) 1553 #define GPIO_PMR2S_P26_Pos 26 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1554 #define GPIO_PMR2S_P26 (_U_(0x1) << GPIO_PMR2S_P26_Pos) 1555 #define GPIO_PMR2S_P27_Pos 27 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1556 #define GPIO_PMR2S_P27 (_U_(0x1) << GPIO_PMR2S_P27_Pos) 1557 #define GPIO_PMR2S_P28_Pos 28 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1558 #define GPIO_PMR2S_P28 (_U_(0x1) << GPIO_PMR2S_P28_Pos) 1559 #define GPIO_PMR2S_P29_Pos 29 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1560 #define GPIO_PMR2S_P29 (_U_(0x1) << GPIO_PMR2S_P29_Pos) 1561 #define GPIO_PMR2S_P30_Pos 30 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1562 #define GPIO_PMR2S_P30 (_U_(0x1) << GPIO_PMR2S_P30_Pos) 1563 #define GPIO_PMR2S_P31_Pos 31 /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */ 1564 #define GPIO_PMR2S_P31 (_U_(0x1) << GPIO_PMR2S_P31_Pos) 1565 #define GPIO_PMR2S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR2S) MASK Register */ 1566 1567 /* -------- GPIO_PMR2C : (GPIO Offset: 0x038) ( /W 32) port Peripheral Mux Register 2 - Clear -------- */ 1568 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1569 typedef union { 1570 struct { 1571 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 2 */ 1572 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 2 */ 1573 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 2 */ 1574 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 2 */ 1575 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 2 */ 1576 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 2 */ 1577 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 2 */ 1578 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 2 */ 1579 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 2 */ 1580 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 2 */ 1581 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 2 */ 1582 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 2 */ 1583 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 2 */ 1584 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 2 */ 1585 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 2 */ 1586 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 2 */ 1587 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 2 */ 1588 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 2 */ 1589 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 2 */ 1590 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 2 */ 1591 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 2 */ 1592 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 2 */ 1593 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 2 */ 1594 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 2 */ 1595 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 2 */ 1596 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 2 */ 1597 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 2 */ 1598 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 2 */ 1599 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 2 */ 1600 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 2 */ 1601 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 2 */ 1602 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 2 */ 1603 } bit; /*!< Structure used for bit access */ 1604 uint32_t reg; /*!< Type used for register access */ 1605 } GPIO_PMR2C_Type; 1606 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1607 1608 #define GPIO_PMR2C_OFFSET 0x038 /**< \brief (GPIO_PMR2C offset) Peripheral Mux Register 2 - Clear */ 1609 1610 #define GPIO_PMR2C_P0_Pos 0 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1611 #define GPIO_PMR2C_P0 (_U_(0x1) << GPIO_PMR2C_P0_Pos) 1612 #define GPIO_PMR2C_P1_Pos 1 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1613 #define GPIO_PMR2C_P1 (_U_(0x1) << GPIO_PMR2C_P1_Pos) 1614 #define GPIO_PMR2C_P2_Pos 2 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1615 #define GPIO_PMR2C_P2 (_U_(0x1) << GPIO_PMR2C_P2_Pos) 1616 #define GPIO_PMR2C_P3_Pos 3 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1617 #define GPIO_PMR2C_P3 (_U_(0x1) << GPIO_PMR2C_P3_Pos) 1618 #define GPIO_PMR2C_P4_Pos 4 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1619 #define GPIO_PMR2C_P4 (_U_(0x1) << GPIO_PMR2C_P4_Pos) 1620 #define GPIO_PMR2C_P5_Pos 5 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1621 #define GPIO_PMR2C_P5 (_U_(0x1) << GPIO_PMR2C_P5_Pos) 1622 #define GPIO_PMR2C_P6_Pos 6 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1623 #define GPIO_PMR2C_P6 (_U_(0x1) << GPIO_PMR2C_P6_Pos) 1624 #define GPIO_PMR2C_P7_Pos 7 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1625 #define GPIO_PMR2C_P7 (_U_(0x1) << GPIO_PMR2C_P7_Pos) 1626 #define GPIO_PMR2C_P8_Pos 8 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1627 #define GPIO_PMR2C_P8 (_U_(0x1) << GPIO_PMR2C_P8_Pos) 1628 #define GPIO_PMR2C_P9_Pos 9 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1629 #define GPIO_PMR2C_P9 (_U_(0x1) << GPIO_PMR2C_P9_Pos) 1630 #define GPIO_PMR2C_P10_Pos 10 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1631 #define GPIO_PMR2C_P10 (_U_(0x1) << GPIO_PMR2C_P10_Pos) 1632 #define GPIO_PMR2C_P11_Pos 11 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1633 #define GPIO_PMR2C_P11 (_U_(0x1) << GPIO_PMR2C_P11_Pos) 1634 #define GPIO_PMR2C_P12_Pos 12 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1635 #define GPIO_PMR2C_P12 (_U_(0x1) << GPIO_PMR2C_P12_Pos) 1636 #define GPIO_PMR2C_P13_Pos 13 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1637 #define GPIO_PMR2C_P13 (_U_(0x1) << GPIO_PMR2C_P13_Pos) 1638 #define GPIO_PMR2C_P14_Pos 14 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1639 #define GPIO_PMR2C_P14 (_U_(0x1) << GPIO_PMR2C_P14_Pos) 1640 #define GPIO_PMR2C_P15_Pos 15 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1641 #define GPIO_PMR2C_P15 (_U_(0x1) << GPIO_PMR2C_P15_Pos) 1642 #define GPIO_PMR2C_P16_Pos 16 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1643 #define GPIO_PMR2C_P16 (_U_(0x1) << GPIO_PMR2C_P16_Pos) 1644 #define GPIO_PMR2C_P17_Pos 17 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1645 #define GPIO_PMR2C_P17 (_U_(0x1) << GPIO_PMR2C_P17_Pos) 1646 #define GPIO_PMR2C_P18_Pos 18 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1647 #define GPIO_PMR2C_P18 (_U_(0x1) << GPIO_PMR2C_P18_Pos) 1648 #define GPIO_PMR2C_P19_Pos 19 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1649 #define GPIO_PMR2C_P19 (_U_(0x1) << GPIO_PMR2C_P19_Pos) 1650 #define GPIO_PMR2C_P20_Pos 20 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1651 #define GPIO_PMR2C_P20 (_U_(0x1) << GPIO_PMR2C_P20_Pos) 1652 #define GPIO_PMR2C_P21_Pos 21 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1653 #define GPIO_PMR2C_P21 (_U_(0x1) << GPIO_PMR2C_P21_Pos) 1654 #define GPIO_PMR2C_P22_Pos 22 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1655 #define GPIO_PMR2C_P22 (_U_(0x1) << GPIO_PMR2C_P22_Pos) 1656 #define GPIO_PMR2C_P23_Pos 23 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1657 #define GPIO_PMR2C_P23 (_U_(0x1) << GPIO_PMR2C_P23_Pos) 1658 #define GPIO_PMR2C_P24_Pos 24 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1659 #define GPIO_PMR2C_P24 (_U_(0x1) << GPIO_PMR2C_P24_Pos) 1660 #define GPIO_PMR2C_P25_Pos 25 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1661 #define GPIO_PMR2C_P25 (_U_(0x1) << GPIO_PMR2C_P25_Pos) 1662 #define GPIO_PMR2C_P26_Pos 26 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1663 #define GPIO_PMR2C_P26 (_U_(0x1) << GPIO_PMR2C_P26_Pos) 1664 #define GPIO_PMR2C_P27_Pos 27 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1665 #define GPIO_PMR2C_P27 (_U_(0x1) << GPIO_PMR2C_P27_Pos) 1666 #define GPIO_PMR2C_P28_Pos 28 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1667 #define GPIO_PMR2C_P28 (_U_(0x1) << GPIO_PMR2C_P28_Pos) 1668 #define GPIO_PMR2C_P29_Pos 29 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1669 #define GPIO_PMR2C_P29 (_U_(0x1) << GPIO_PMR2C_P29_Pos) 1670 #define GPIO_PMR2C_P30_Pos 30 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1671 #define GPIO_PMR2C_P30 (_U_(0x1) << GPIO_PMR2C_P30_Pos) 1672 #define GPIO_PMR2C_P31_Pos 31 /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */ 1673 #define GPIO_PMR2C_P31 (_U_(0x1) << GPIO_PMR2C_P31_Pos) 1674 #define GPIO_PMR2C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR2C) MASK Register */ 1675 1676 /* -------- GPIO_PMR2T : (GPIO Offset: 0x03C) ( /W 32) port Peripheral Mux Register 2 - Toggle -------- */ 1677 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1678 typedef union { 1679 struct { 1680 uint32_t P0:1; /*!< bit: 0 Peripheral Multiplexer Select bit 2 */ 1681 uint32_t P1:1; /*!< bit: 1 Peripheral Multiplexer Select bit 2 */ 1682 uint32_t P2:1; /*!< bit: 2 Peripheral Multiplexer Select bit 2 */ 1683 uint32_t P3:1; /*!< bit: 3 Peripheral Multiplexer Select bit 2 */ 1684 uint32_t P4:1; /*!< bit: 4 Peripheral Multiplexer Select bit 2 */ 1685 uint32_t P5:1; /*!< bit: 5 Peripheral Multiplexer Select bit 2 */ 1686 uint32_t P6:1; /*!< bit: 6 Peripheral Multiplexer Select bit 2 */ 1687 uint32_t P7:1; /*!< bit: 7 Peripheral Multiplexer Select bit 2 */ 1688 uint32_t P8:1; /*!< bit: 8 Peripheral Multiplexer Select bit 2 */ 1689 uint32_t P9:1; /*!< bit: 9 Peripheral Multiplexer Select bit 2 */ 1690 uint32_t P10:1; /*!< bit: 10 Peripheral Multiplexer Select bit 2 */ 1691 uint32_t P11:1; /*!< bit: 11 Peripheral Multiplexer Select bit 2 */ 1692 uint32_t P12:1; /*!< bit: 12 Peripheral Multiplexer Select bit 2 */ 1693 uint32_t P13:1; /*!< bit: 13 Peripheral Multiplexer Select bit 2 */ 1694 uint32_t P14:1; /*!< bit: 14 Peripheral Multiplexer Select bit 2 */ 1695 uint32_t P15:1; /*!< bit: 15 Peripheral Multiplexer Select bit 2 */ 1696 uint32_t P16:1; /*!< bit: 16 Peripheral Multiplexer Select bit 2 */ 1697 uint32_t P17:1; /*!< bit: 17 Peripheral Multiplexer Select bit 2 */ 1698 uint32_t P18:1; /*!< bit: 18 Peripheral Multiplexer Select bit 2 */ 1699 uint32_t P19:1; /*!< bit: 19 Peripheral Multiplexer Select bit 2 */ 1700 uint32_t P20:1; /*!< bit: 20 Peripheral Multiplexer Select bit 2 */ 1701 uint32_t P21:1; /*!< bit: 21 Peripheral Multiplexer Select bit 2 */ 1702 uint32_t P22:1; /*!< bit: 22 Peripheral Multiplexer Select bit 2 */ 1703 uint32_t P23:1; /*!< bit: 23 Peripheral Multiplexer Select bit 2 */ 1704 uint32_t P24:1; /*!< bit: 24 Peripheral Multiplexer Select bit 2 */ 1705 uint32_t P25:1; /*!< bit: 25 Peripheral Multiplexer Select bit 2 */ 1706 uint32_t P26:1; /*!< bit: 26 Peripheral Multiplexer Select bit 2 */ 1707 uint32_t P27:1; /*!< bit: 27 Peripheral Multiplexer Select bit 2 */ 1708 uint32_t P28:1; /*!< bit: 28 Peripheral Multiplexer Select bit 2 */ 1709 uint32_t P29:1; /*!< bit: 29 Peripheral Multiplexer Select bit 2 */ 1710 uint32_t P30:1; /*!< bit: 30 Peripheral Multiplexer Select bit 2 */ 1711 uint32_t P31:1; /*!< bit: 31 Peripheral Multiplexer Select bit 2 */ 1712 } bit; /*!< Structure used for bit access */ 1713 uint32_t reg; /*!< Type used for register access */ 1714 } GPIO_PMR2T_Type; 1715 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1716 1717 #define GPIO_PMR2T_OFFSET 0x03C /**< \brief (GPIO_PMR2T offset) Peripheral Mux Register 2 - Toggle */ 1718 1719 #define GPIO_PMR2T_P0_Pos 0 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1720 #define GPIO_PMR2T_P0 (_U_(0x1) << GPIO_PMR2T_P0_Pos) 1721 #define GPIO_PMR2T_P1_Pos 1 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1722 #define GPIO_PMR2T_P1 (_U_(0x1) << GPIO_PMR2T_P1_Pos) 1723 #define GPIO_PMR2T_P2_Pos 2 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1724 #define GPIO_PMR2T_P2 (_U_(0x1) << GPIO_PMR2T_P2_Pos) 1725 #define GPIO_PMR2T_P3_Pos 3 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1726 #define GPIO_PMR2T_P3 (_U_(0x1) << GPIO_PMR2T_P3_Pos) 1727 #define GPIO_PMR2T_P4_Pos 4 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1728 #define GPIO_PMR2T_P4 (_U_(0x1) << GPIO_PMR2T_P4_Pos) 1729 #define GPIO_PMR2T_P5_Pos 5 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1730 #define GPIO_PMR2T_P5 (_U_(0x1) << GPIO_PMR2T_P5_Pos) 1731 #define GPIO_PMR2T_P6_Pos 6 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1732 #define GPIO_PMR2T_P6 (_U_(0x1) << GPIO_PMR2T_P6_Pos) 1733 #define GPIO_PMR2T_P7_Pos 7 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1734 #define GPIO_PMR2T_P7 (_U_(0x1) << GPIO_PMR2T_P7_Pos) 1735 #define GPIO_PMR2T_P8_Pos 8 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1736 #define GPIO_PMR2T_P8 (_U_(0x1) << GPIO_PMR2T_P8_Pos) 1737 #define GPIO_PMR2T_P9_Pos 9 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1738 #define GPIO_PMR2T_P9 (_U_(0x1) << GPIO_PMR2T_P9_Pos) 1739 #define GPIO_PMR2T_P10_Pos 10 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1740 #define GPIO_PMR2T_P10 (_U_(0x1) << GPIO_PMR2T_P10_Pos) 1741 #define GPIO_PMR2T_P11_Pos 11 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1742 #define GPIO_PMR2T_P11 (_U_(0x1) << GPIO_PMR2T_P11_Pos) 1743 #define GPIO_PMR2T_P12_Pos 12 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1744 #define GPIO_PMR2T_P12 (_U_(0x1) << GPIO_PMR2T_P12_Pos) 1745 #define GPIO_PMR2T_P13_Pos 13 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1746 #define GPIO_PMR2T_P13 (_U_(0x1) << GPIO_PMR2T_P13_Pos) 1747 #define GPIO_PMR2T_P14_Pos 14 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1748 #define GPIO_PMR2T_P14 (_U_(0x1) << GPIO_PMR2T_P14_Pos) 1749 #define GPIO_PMR2T_P15_Pos 15 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1750 #define GPIO_PMR2T_P15 (_U_(0x1) << GPIO_PMR2T_P15_Pos) 1751 #define GPIO_PMR2T_P16_Pos 16 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1752 #define GPIO_PMR2T_P16 (_U_(0x1) << GPIO_PMR2T_P16_Pos) 1753 #define GPIO_PMR2T_P17_Pos 17 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1754 #define GPIO_PMR2T_P17 (_U_(0x1) << GPIO_PMR2T_P17_Pos) 1755 #define GPIO_PMR2T_P18_Pos 18 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1756 #define GPIO_PMR2T_P18 (_U_(0x1) << GPIO_PMR2T_P18_Pos) 1757 #define GPIO_PMR2T_P19_Pos 19 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1758 #define GPIO_PMR2T_P19 (_U_(0x1) << GPIO_PMR2T_P19_Pos) 1759 #define GPIO_PMR2T_P20_Pos 20 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1760 #define GPIO_PMR2T_P20 (_U_(0x1) << GPIO_PMR2T_P20_Pos) 1761 #define GPIO_PMR2T_P21_Pos 21 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1762 #define GPIO_PMR2T_P21 (_U_(0x1) << GPIO_PMR2T_P21_Pos) 1763 #define GPIO_PMR2T_P22_Pos 22 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1764 #define GPIO_PMR2T_P22 (_U_(0x1) << GPIO_PMR2T_P22_Pos) 1765 #define GPIO_PMR2T_P23_Pos 23 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1766 #define GPIO_PMR2T_P23 (_U_(0x1) << GPIO_PMR2T_P23_Pos) 1767 #define GPIO_PMR2T_P24_Pos 24 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1768 #define GPIO_PMR2T_P24 (_U_(0x1) << GPIO_PMR2T_P24_Pos) 1769 #define GPIO_PMR2T_P25_Pos 25 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1770 #define GPIO_PMR2T_P25 (_U_(0x1) << GPIO_PMR2T_P25_Pos) 1771 #define GPIO_PMR2T_P26_Pos 26 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1772 #define GPIO_PMR2T_P26 (_U_(0x1) << GPIO_PMR2T_P26_Pos) 1773 #define GPIO_PMR2T_P27_Pos 27 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1774 #define GPIO_PMR2T_P27 (_U_(0x1) << GPIO_PMR2T_P27_Pos) 1775 #define GPIO_PMR2T_P28_Pos 28 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1776 #define GPIO_PMR2T_P28 (_U_(0x1) << GPIO_PMR2T_P28_Pos) 1777 #define GPIO_PMR2T_P29_Pos 29 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1778 #define GPIO_PMR2T_P29 (_U_(0x1) << GPIO_PMR2T_P29_Pos) 1779 #define GPIO_PMR2T_P30_Pos 30 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1780 #define GPIO_PMR2T_P30 (_U_(0x1) << GPIO_PMR2T_P30_Pos) 1781 #define GPIO_PMR2T_P31_Pos 31 /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */ 1782 #define GPIO_PMR2T_P31 (_U_(0x1) << GPIO_PMR2T_P31_Pos) 1783 #define GPIO_PMR2T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PMR2T) MASK Register */ 1784 1785 /* -------- GPIO_ODER : (GPIO Offset: 0x040) (R/W 32) port Output Driver Enable Register -------- */ 1786 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1787 typedef union { 1788 struct { 1789 uint32_t P0:1; /*!< bit: 0 Output Driver Enable */ 1790 uint32_t P1:1; /*!< bit: 1 Output Driver Enable */ 1791 uint32_t P2:1; /*!< bit: 2 Output Driver Enable */ 1792 uint32_t P3:1; /*!< bit: 3 Output Driver Enable */ 1793 uint32_t P4:1; /*!< bit: 4 Output Driver Enable */ 1794 uint32_t P5:1; /*!< bit: 5 Output Driver Enable */ 1795 uint32_t P6:1; /*!< bit: 6 Output Driver Enable */ 1796 uint32_t P7:1; /*!< bit: 7 Output Driver Enable */ 1797 uint32_t P8:1; /*!< bit: 8 Output Driver Enable */ 1798 uint32_t P9:1; /*!< bit: 9 Output Driver Enable */ 1799 uint32_t P10:1; /*!< bit: 10 Output Driver Enable */ 1800 uint32_t P11:1; /*!< bit: 11 Output Driver Enable */ 1801 uint32_t P12:1; /*!< bit: 12 Output Driver Enable */ 1802 uint32_t P13:1; /*!< bit: 13 Output Driver Enable */ 1803 uint32_t P14:1; /*!< bit: 14 Output Driver Enable */ 1804 uint32_t P15:1; /*!< bit: 15 Output Driver Enable */ 1805 uint32_t P16:1; /*!< bit: 16 Output Driver Enable */ 1806 uint32_t P17:1; /*!< bit: 17 Output Driver Enable */ 1807 uint32_t P18:1; /*!< bit: 18 Output Driver Enable */ 1808 uint32_t P19:1; /*!< bit: 19 Output Driver Enable */ 1809 uint32_t P20:1; /*!< bit: 20 Output Driver Enable */ 1810 uint32_t P21:1; /*!< bit: 21 Output Driver Enable */ 1811 uint32_t P22:1; /*!< bit: 22 Output Driver Enable */ 1812 uint32_t P23:1; /*!< bit: 23 Output Driver Enable */ 1813 uint32_t P24:1; /*!< bit: 24 Output Driver Enable */ 1814 uint32_t P25:1; /*!< bit: 25 Output Driver Enable */ 1815 uint32_t P26:1; /*!< bit: 26 Output Driver Enable */ 1816 uint32_t P27:1; /*!< bit: 27 Output Driver Enable */ 1817 uint32_t P28:1; /*!< bit: 28 Output Driver Enable */ 1818 uint32_t P29:1; /*!< bit: 29 Output Driver Enable */ 1819 uint32_t P30:1; /*!< bit: 30 Output Driver Enable */ 1820 uint32_t P31:1; /*!< bit: 31 Output Driver Enable */ 1821 } bit; /*!< Structure used for bit access */ 1822 uint32_t reg; /*!< Type used for register access */ 1823 } GPIO_ODER_Type; 1824 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1825 1826 #define GPIO_ODER_OFFSET 0x040 /**< \brief (GPIO_ODER offset) Output Driver Enable Register */ 1827 1828 #define GPIO_ODER_P0_Pos 0 /**< \brief (GPIO_ODER) Output Driver Enable */ 1829 #define GPIO_ODER_P0 (_U_(0x1) << GPIO_ODER_P0_Pos) 1830 #define GPIO_ODER_P1_Pos 1 /**< \brief (GPIO_ODER) Output Driver Enable */ 1831 #define GPIO_ODER_P1 (_U_(0x1) << GPIO_ODER_P1_Pos) 1832 #define GPIO_ODER_P2_Pos 2 /**< \brief (GPIO_ODER) Output Driver Enable */ 1833 #define GPIO_ODER_P2 (_U_(0x1) << GPIO_ODER_P2_Pos) 1834 #define GPIO_ODER_P3_Pos 3 /**< \brief (GPIO_ODER) Output Driver Enable */ 1835 #define GPIO_ODER_P3 (_U_(0x1) << GPIO_ODER_P3_Pos) 1836 #define GPIO_ODER_P4_Pos 4 /**< \brief (GPIO_ODER) Output Driver Enable */ 1837 #define GPIO_ODER_P4 (_U_(0x1) << GPIO_ODER_P4_Pos) 1838 #define GPIO_ODER_P5_Pos 5 /**< \brief (GPIO_ODER) Output Driver Enable */ 1839 #define GPIO_ODER_P5 (_U_(0x1) << GPIO_ODER_P5_Pos) 1840 #define GPIO_ODER_P6_Pos 6 /**< \brief (GPIO_ODER) Output Driver Enable */ 1841 #define GPIO_ODER_P6 (_U_(0x1) << GPIO_ODER_P6_Pos) 1842 #define GPIO_ODER_P7_Pos 7 /**< \brief (GPIO_ODER) Output Driver Enable */ 1843 #define GPIO_ODER_P7 (_U_(0x1) << GPIO_ODER_P7_Pos) 1844 #define GPIO_ODER_P8_Pos 8 /**< \brief (GPIO_ODER) Output Driver Enable */ 1845 #define GPIO_ODER_P8 (_U_(0x1) << GPIO_ODER_P8_Pos) 1846 #define GPIO_ODER_P9_Pos 9 /**< \brief (GPIO_ODER) Output Driver Enable */ 1847 #define GPIO_ODER_P9 (_U_(0x1) << GPIO_ODER_P9_Pos) 1848 #define GPIO_ODER_P10_Pos 10 /**< \brief (GPIO_ODER) Output Driver Enable */ 1849 #define GPIO_ODER_P10 (_U_(0x1) << GPIO_ODER_P10_Pos) 1850 #define GPIO_ODER_P11_Pos 11 /**< \brief (GPIO_ODER) Output Driver Enable */ 1851 #define GPIO_ODER_P11 (_U_(0x1) << GPIO_ODER_P11_Pos) 1852 #define GPIO_ODER_P12_Pos 12 /**< \brief (GPIO_ODER) Output Driver Enable */ 1853 #define GPIO_ODER_P12 (_U_(0x1) << GPIO_ODER_P12_Pos) 1854 #define GPIO_ODER_P13_Pos 13 /**< \brief (GPIO_ODER) Output Driver Enable */ 1855 #define GPIO_ODER_P13 (_U_(0x1) << GPIO_ODER_P13_Pos) 1856 #define GPIO_ODER_P14_Pos 14 /**< \brief (GPIO_ODER) Output Driver Enable */ 1857 #define GPIO_ODER_P14 (_U_(0x1) << GPIO_ODER_P14_Pos) 1858 #define GPIO_ODER_P15_Pos 15 /**< \brief (GPIO_ODER) Output Driver Enable */ 1859 #define GPIO_ODER_P15 (_U_(0x1) << GPIO_ODER_P15_Pos) 1860 #define GPIO_ODER_P16_Pos 16 /**< \brief (GPIO_ODER) Output Driver Enable */ 1861 #define GPIO_ODER_P16 (_U_(0x1) << GPIO_ODER_P16_Pos) 1862 #define GPIO_ODER_P17_Pos 17 /**< \brief (GPIO_ODER) Output Driver Enable */ 1863 #define GPIO_ODER_P17 (_U_(0x1) << GPIO_ODER_P17_Pos) 1864 #define GPIO_ODER_P18_Pos 18 /**< \brief (GPIO_ODER) Output Driver Enable */ 1865 #define GPIO_ODER_P18 (_U_(0x1) << GPIO_ODER_P18_Pos) 1866 #define GPIO_ODER_P19_Pos 19 /**< \brief (GPIO_ODER) Output Driver Enable */ 1867 #define GPIO_ODER_P19 (_U_(0x1) << GPIO_ODER_P19_Pos) 1868 #define GPIO_ODER_P20_Pos 20 /**< \brief (GPIO_ODER) Output Driver Enable */ 1869 #define GPIO_ODER_P20 (_U_(0x1) << GPIO_ODER_P20_Pos) 1870 #define GPIO_ODER_P21_Pos 21 /**< \brief (GPIO_ODER) Output Driver Enable */ 1871 #define GPIO_ODER_P21 (_U_(0x1) << GPIO_ODER_P21_Pos) 1872 #define GPIO_ODER_P22_Pos 22 /**< \brief (GPIO_ODER) Output Driver Enable */ 1873 #define GPIO_ODER_P22 (_U_(0x1) << GPIO_ODER_P22_Pos) 1874 #define GPIO_ODER_P23_Pos 23 /**< \brief (GPIO_ODER) Output Driver Enable */ 1875 #define GPIO_ODER_P23 (_U_(0x1) << GPIO_ODER_P23_Pos) 1876 #define GPIO_ODER_P24_Pos 24 /**< \brief (GPIO_ODER) Output Driver Enable */ 1877 #define GPIO_ODER_P24 (_U_(0x1) << GPIO_ODER_P24_Pos) 1878 #define GPIO_ODER_P25_Pos 25 /**< \brief (GPIO_ODER) Output Driver Enable */ 1879 #define GPIO_ODER_P25 (_U_(0x1) << GPIO_ODER_P25_Pos) 1880 #define GPIO_ODER_P26_Pos 26 /**< \brief (GPIO_ODER) Output Driver Enable */ 1881 #define GPIO_ODER_P26 (_U_(0x1) << GPIO_ODER_P26_Pos) 1882 #define GPIO_ODER_P27_Pos 27 /**< \brief (GPIO_ODER) Output Driver Enable */ 1883 #define GPIO_ODER_P27 (_U_(0x1) << GPIO_ODER_P27_Pos) 1884 #define GPIO_ODER_P28_Pos 28 /**< \brief (GPIO_ODER) Output Driver Enable */ 1885 #define GPIO_ODER_P28 (_U_(0x1) << GPIO_ODER_P28_Pos) 1886 #define GPIO_ODER_P29_Pos 29 /**< \brief (GPIO_ODER) Output Driver Enable */ 1887 #define GPIO_ODER_P29 (_U_(0x1) << GPIO_ODER_P29_Pos) 1888 #define GPIO_ODER_P30_Pos 30 /**< \brief (GPIO_ODER) Output Driver Enable */ 1889 #define GPIO_ODER_P30 (_U_(0x1) << GPIO_ODER_P30_Pos) 1890 #define GPIO_ODER_P31_Pos 31 /**< \brief (GPIO_ODER) Output Driver Enable */ 1891 #define GPIO_ODER_P31 (_U_(0x1) << GPIO_ODER_P31_Pos) 1892 #define GPIO_ODER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODER) MASK Register */ 1893 1894 /* -------- GPIO_ODERS : (GPIO Offset: 0x044) ( /W 32) port Output Driver Enable Register - Set -------- */ 1895 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1896 typedef union { 1897 struct { 1898 uint32_t P0:1; /*!< bit: 0 Output Driver Enable */ 1899 uint32_t P1:1; /*!< bit: 1 Output Driver Enable */ 1900 uint32_t P2:1; /*!< bit: 2 Output Driver Enable */ 1901 uint32_t P3:1; /*!< bit: 3 Output Driver Enable */ 1902 uint32_t P4:1; /*!< bit: 4 Output Driver Enable */ 1903 uint32_t P5:1; /*!< bit: 5 Output Driver Enable */ 1904 uint32_t P6:1; /*!< bit: 6 Output Driver Enable */ 1905 uint32_t P7:1; /*!< bit: 7 Output Driver Enable */ 1906 uint32_t P8:1; /*!< bit: 8 Output Driver Enable */ 1907 uint32_t P9:1; /*!< bit: 9 Output Driver Enable */ 1908 uint32_t P10:1; /*!< bit: 10 Output Driver Enable */ 1909 uint32_t P11:1; /*!< bit: 11 Output Driver Enable */ 1910 uint32_t P12:1; /*!< bit: 12 Output Driver Enable */ 1911 uint32_t P13:1; /*!< bit: 13 Output Driver Enable */ 1912 uint32_t P14:1; /*!< bit: 14 Output Driver Enable */ 1913 uint32_t P15:1; /*!< bit: 15 Output Driver Enable */ 1914 uint32_t P16:1; /*!< bit: 16 Output Driver Enable */ 1915 uint32_t P17:1; /*!< bit: 17 Output Driver Enable */ 1916 uint32_t P18:1; /*!< bit: 18 Output Driver Enable */ 1917 uint32_t P19:1; /*!< bit: 19 Output Driver Enable */ 1918 uint32_t P20:1; /*!< bit: 20 Output Driver Enable */ 1919 uint32_t P21:1; /*!< bit: 21 Output Driver Enable */ 1920 uint32_t P22:1; /*!< bit: 22 Output Driver Enable */ 1921 uint32_t P23:1; /*!< bit: 23 Output Driver Enable */ 1922 uint32_t P24:1; /*!< bit: 24 Output Driver Enable */ 1923 uint32_t P25:1; /*!< bit: 25 Output Driver Enable */ 1924 uint32_t P26:1; /*!< bit: 26 Output Driver Enable */ 1925 uint32_t P27:1; /*!< bit: 27 Output Driver Enable */ 1926 uint32_t P28:1; /*!< bit: 28 Output Driver Enable */ 1927 uint32_t P29:1; /*!< bit: 29 Output Driver Enable */ 1928 uint32_t P30:1; /*!< bit: 30 Output Driver Enable */ 1929 uint32_t P31:1; /*!< bit: 31 Output Driver Enable */ 1930 } bit; /*!< Structure used for bit access */ 1931 uint32_t reg; /*!< Type used for register access */ 1932 } GPIO_ODERS_Type; 1933 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1934 1935 #define GPIO_ODERS_OFFSET 0x044 /**< \brief (GPIO_ODERS offset) Output Driver Enable Register - Set */ 1936 1937 #define GPIO_ODERS_P0_Pos 0 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1938 #define GPIO_ODERS_P0 (_U_(0x1) << GPIO_ODERS_P0_Pos) 1939 #define GPIO_ODERS_P1_Pos 1 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1940 #define GPIO_ODERS_P1 (_U_(0x1) << GPIO_ODERS_P1_Pos) 1941 #define GPIO_ODERS_P2_Pos 2 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1942 #define GPIO_ODERS_P2 (_U_(0x1) << GPIO_ODERS_P2_Pos) 1943 #define GPIO_ODERS_P3_Pos 3 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1944 #define GPIO_ODERS_P3 (_U_(0x1) << GPIO_ODERS_P3_Pos) 1945 #define GPIO_ODERS_P4_Pos 4 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1946 #define GPIO_ODERS_P4 (_U_(0x1) << GPIO_ODERS_P4_Pos) 1947 #define GPIO_ODERS_P5_Pos 5 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1948 #define GPIO_ODERS_P5 (_U_(0x1) << GPIO_ODERS_P5_Pos) 1949 #define GPIO_ODERS_P6_Pos 6 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1950 #define GPIO_ODERS_P6 (_U_(0x1) << GPIO_ODERS_P6_Pos) 1951 #define GPIO_ODERS_P7_Pos 7 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1952 #define GPIO_ODERS_P7 (_U_(0x1) << GPIO_ODERS_P7_Pos) 1953 #define GPIO_ODERS_P8_Pos 8 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1954 #define GPIO_ODERS_P8 (_U_(0x1) << GPIO_ODERS_P8_Pos) 1955 #define GPIO_ODERS_P9_Pos 9 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1956 #define GPIO_ODERS_P9 (_U_(0x1) << GPIO_ODERS_P9_Pos) 1957 #define GPIO_ODERS_P10_Pos 10 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1958 #define GPIO_ODERS_P10 (_U_(0x1) << GPIO_ODERS_P10_Pos) 1959 #define GPIO_ODERS_P11_Pos 11 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1960 #define GPIO_ODERS_P11 (_U_(0x1) << GPIO_ODERS_P11_Pos) 1961 #define GPIO_ODERS_P12_Pos 12 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1962 #define GPIO_ODERS_P12 (_U_(0x1) << GPIO_ODERS_P12_Pos) 1963 #define GPIO_ODERS_P13_Pos 13 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1964 #define GPIO_ODERS_P13 (_U_(0x1) << GPIO_ODERS_P13_Pos) 1965 #define GPIO_ODERS_P14_Pos 14 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1966 #define GPIO_ODERS_P14 (_U_(0x1) << GPIO_ODERS_P14_Pos) 1967 #define GPIO_ODERS_P15_Pos 15 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1968 #define GPIO_ODERS_P15 (_U_(0x1) << GPIO_ODERS_P15_Pos) 1969 #define GPIO_ODERS_P16_Pos 16 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1970 #define GPIO_ODERS_P16 (_U_(0x1) << GPIO_ODERS_P16_Pos) 1971 #define GPIO_ODERS_P17_Pos 17 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1972 #define GPIO_ODERS_P17 (_U_(0x1) << GPIO_ODERS_P17_Pos) 1973 #define GPIO_ODERS_P18_Pos 18 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1974 #define GPIO_ODERS_P18 (_U_(0x1) << GPIO_ODERS_P18_Pos) 1975 #define GPIO_ODERS_P19_Pos 19 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1976 #define GPIO_ODERS_P19 (_U_(0x1) << GPIO_ODERS_P19_Pos) 1977 #define GPIO_ODERS_P20_Pos 20 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1978 #define GPIO_ODERS_P20 (_U_(0x1) << GPIO_ODERS_P20_Pos) 1979 #define GPIO_ODERS_P21_Pos 21 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1980 #define GPIO_ODERS_P21 (_U_(0x1) << GPIO_ODERS_P21_Pos) 1981 #define GPIO_ODERS_P22_Pos 22 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1982 #define GPIO_ODERS_P22 (_U_(0x1) << GPIO_ODERS_P22_Pos) 1983 #define GPIO_ODERS_P23_Pos 23 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1984 #define GPIO_ODERS_P23 (_U_(0x1) << GPIO_ODERS_P23_Pos) 1985 #define GPIO_ODERS_P24_Pos 24 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1986 #define GPIO_ODERS_P24 (_U_(0x1) << GPIO_ODERS_P24_Pos) 1987 #define GPIO_ODERS_P25_Pos 25 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1988 #define GPIO_ODERS_P25 (_U_(0x1) << GPIO_ODERS_P25_Pos) 1989 #define GPIO_ODERS_P26_Pos 26 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1990 #define GPIO_ODERS_P26 (_U_(0x1) << GPIO_ODERS_P26_Pos) 1991 #define GPIO_ODERS_P27_Pos 27 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1992 #define GPIO_ODERS_P27 (_U_(0x1) << GPIO_ODERS_P27_Pos) 1993 #define GPIO_ODERS_P28_Pos 28 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1994 #define GPIO_ODERS_P28 (_U_(0x1) << GPIO_ODERS_P28_Pos) 1995 #define GPIO_ODERS_P29_Pos 29 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1996 #define GPIO_ODERS_P29 (_U_(0x1) << GPIO_ODERS_P29_Pos) 1997 #define GPIO_ODERS_P30_Pos 30 /**< \brief (GPIO_ODERS) Output Driver Enable */ 1998 #define GPIO_ODERS_P30 (_U_(0x1) << GPIO_ODERS_P30_Pos) 1999 #define GPIO_ODERS_P31_Pos 31 /**< \brief (GPIO_ODERS) Output Driver Enable */ 2000 #define GPIO_ODERS_P31 (_U_(0x1) << GPIO_ODERS_P31_Pos) 2001 #define GPIO_ODERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODERS) MASK Register */ 2002 2003 /* -------- GPIO_ODERC : (GPIO Offset: 0x048) ( /W 32) port Output Driver Enable Register - Clear -------- */ 2004 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2005 typedef union { 2006 struct { 2007 uint32_t P0:1; /*!< bit: 0 Output Driver Enable */ 2008 uint32_t P1:1; /*!< bit: 1 Output Driver Enable */ 2009 uint32_t P2:1; /*!< bit: 2 Output Driver Enable */ 2010 uint32_t P3:1; /*!< bit: 3 Output Driver Enable */ 2011 uint32_t P4:1; /*!< bit: 4 Output Driver Enable */ 2012 uint32_t P5:1; /*!< bit: 5 Output Driver Enable */ 2013 uint32_t P6:1; /*!< bit: 6 Output Driver Enable */ 2014 uint32_t P7:1; /*!< bit: 7 Output Driver Enable */ 2015 uint32_t P8:1; /*!< bit: 8 Output Driver Enable */ 2016 uint32_t P9:1; /*!< bit: 9 Output Driver Enable */ 2017 uint32_t P10:1; /*!< bit: 10 Output Driver Enable */ 2018 uint32_t P11:1; /*!< bit: 11 Output Driver Enable */ 2019 uint32_t P12:1; /*!< bit: 12 Output Driver Enable */ 2020 uint32_t P13:1; /*!< bit: 13 Output Driver Enable */ 2021 uint32_t P14:1; /*!< bit: 14 Output Driver Enable */ 2022 uint32_t P15:1; /*!< bit: 15 Output Driver Enable */ 2023 uint32_t P16:1; /*!< bit: 16 Output Driver Enable */ 2024 uint32_t P17:1; /*!< bit: 17 Output Driver Enable */ 2025 uint32_t P18:1; /*!< bit: 18 Output Driver Enable */ 2026 uint32_t P19:1; /*!< bit: 19 Output Driver Enable */ 2027 uint32_t P20:1; /*!< bit: 20 Output Driver Enable */ 2028 uint32_t P21:1; /*!< bit: 21 Output Driver Enable */ 2029 uint32_t P22:1; /*!< bit: 22 Output Driver Enable */ 2030 uint32_t P23:1; /*!< bit: 23 Output Driver Enable */ 2031 uint32_t P24:1; /*!< bit: 24 Output Driver Enable */ 2032 uint32_t P25:1; /*!< bit: 25 Output Driver Enable */ 2033 uint32_t P26:1; /*!< bit: 26 Output Driver Enable */ 2034 uint32_t P27:1; /*!< bit: 27 Output Driver Enable */ 2035 uint32_t P28:1; /*!< bit: 28 Output Driver Enable */ 2036 uint32_t P29:1; /*!< bit: 29 Output Driver Enable */ 2037 uint32_t P30:1; /*!< bit: 30 Output Driver Enable */ 2038 uint32_t P31:1; /*!< bit: 31 Output Driver Enable */ 2039 } bit; /*!< Structure used for bit access */ 2040 uint32_t reg; /*!< Type used for register access */ 2041 } GPIO_ODERC_Type; 2042 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2043 2044 #define GPIO_ODERC_OFFSET 0x048 /**< \brief (GPIO_ODERC offset) Output Driver Enable Register - Clear */ 2045 2046 #define GPIO_ODERC_P0_Pos 0 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2047 #define GPIO_ODERC_P0 (_U_(0x1) << GPIO_ODERC_P0_Pos) 2048 #define GPIO_ODERC_P1_Pos 1 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2049 #define GPIO_ODERC_P1 (_U_(0x1) << GPIO_ODERC_P1_Pos) 2050 #define GPIO_ODERC_P2_Pos 2 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2051 #define GPIO_ODERC_P2 (_U_(0x1) << GPIO_ODERC_P2_Pos) 2052 #define GPIO_ODERC_P3_Pos 3 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2053 #define GPIO_ODERC_P3 (_U_(0x1) << GPIO_ODERC_P3_Pos) 2054 #define GPIO_ODERC_P4_Pos 4 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2055 #define GPIO_ODERC_P4 (_U_(0x1) << GPIO_ODERC_P4_Pos) 2056 #define GPIO_ODERC_P5_Pos 5 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2057 #define GPIO_ODERC_P5 (_U_(0x1) << GPIO_ODERC_P5_Pos) 2058 #define GPIO_ODERC_P6_Pos 6 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2059 #define GPIO_ODERC_P6 (_U_(0x1) << GPIO_ODERC_P6_Pos) 2060 #define GPIO_ODERC_P7_Pos 7 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2061 #define GPIO_ODERC_P7 (_U_(0x1) << GPIO_ODERC_P7_Pos) 2062 #define GPIO_ODERC_P8_Pos 8 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2063 #define GPIO_ODERC_P8 (_U_(0x1) << GPIO_ODERC_P8_Pos) 2064 #define GPIO_ODERC_P9_Pos 9 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2065 #define GPIO_ODERC_P9 (_U_(0x1) << GPIO_ODERC_P9_Pos) 2066 #define GPIO_ODERC_P10_Pos 10 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2067 #define GPIO_ODERC_P10 (_U_(0x1) << GPIO_ODERC_P10_Pos) 2068 #define GPIO_ODERC_P11_Pos 11 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2069 #define GPIO_ODERC_P11 (_U_(0x1) << GPIO_ODERC_P11_Pos) 2070 #define GPIO_ODERC_P12_Pos 12 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2071 #define GPIO_ODERC_P12 (_U_(0x1) << GPIO_ODERC_P12_Pos) 2072 #define GPIO_ODERC_P13_Pos 13 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2073 #define GPIO_ODERC_P13 (_U_(0x1) << GPIO_ODERC_P13_Pos) 2074 #define GPIO_ODERC_P14_Pos 14 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2075 #define GPIO_ODERC_P14 (_U_(0x1) << GPIO_ODERC_P14_Pos) 2076 #define GPIO_ODERC_P15_Pos 15 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2077 #define GPIO_ODERC_P15 (_U_(0x1) << GPIO_ODERC_P15_Pos) 2078 #define GPIO_ODERC_P16_Pos 16 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2079 #define GPIO_ODERC_P16 (_U_(0x1) << GPIO_ODERC_P16_Pos) 2080 #define GPIO_ODERC_P17_Pos 17 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2081 #define GPIO_ODERC_P17 (_U_(0x1) << GPIO_ODERC_P17_Pos) 2082 #define GPIO_ODERC_P18_Pos 18 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2083 #define GPIO_ODERC_P18 (_U_(0x1) << GPIO_ODERC_P18_Pos) 2084 #define GPIO_ODERC_P19_Pos 19 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2085 #define GPIO_ODERC_P19 (_U_(0x1) << GPIO_ODERC_P19_Pos) 2086 #define GPIO_ODERC_P20_Pos 20 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2087 #define GPIO_ODERC_P20 (_U_(0x1) << GPIO_ODERC_P20_Pos) 2088 #define GPIO_ODERC_P21_Pos 21 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2089 #define GPIO_ODERC_P21 (_U_(0x1) << GPIO_ODERC_P21_Pos) 2090 #define GPIO_ODERC_P22_Pos 22 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2091 #define GPIO_ODERC_P22 (_U_(0x1) << GPIO_ODERC_P22_Pos) 2092 #define GPIO_ODERC_P23_Pos 23 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2093 #define GPIO_ODERC_P23 (_U_(0x1) << GPIO_ODERC_P23_Pos) 2094 #define GPIO_ODERC_P24_Pos 24 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2095 #define GPIO_ODERC_P24 (_U_(0x1) << GPIO_ODERC_P24_Pos) 2096 #define GPIO_ODERC_P25_Pos 25 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2097 #define GPIO_ODERC_P25 (_U_(0x1) << GPIO_ODERC_P25_Pos) 2098 #define GPIO_ODERC_P26_Pos 26 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2099 #define GPIO_ODERC_P26 (_U_(0x1) << GPIO_ODERC_P26_Pos) 2100 #define GPIO_ODERC_P27_Pos 27 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2101 #define GPIO_ODERC_P27 (_U_(0x1) << GPIO_ODERC_P27_Pos) 2102 #define GPIO_ODERC_P28_Pos 28 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2103 #define GPIO_ODERC_P28 (_U_(0x1) << GPIO_ODERC_P28_Pos) 2104 #define GPIO_ODERC_P29_Pos 29 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2105 #define GPIO_ODERC_P29 (_U_(0x1) << GPIO_ODERC_P29_Pos) 2106 #define GPIO_ODERC_P30_Pos 30 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2107 #define GPIO_ODERC_P30 (_U_(0x1) << GPIO_ODERC_P30_Pos) 2108 #define GPIO_ODERC_P31_Pos 31 /**< \brief (GPIO_ODERC) Output Driver Enable */ 2109 #define GPIO_ODERC_P31 (_U_(0x1) << GPIO_ODERC_P31_Pos) 2110 #define GPIO_ODERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODERC) MASK Register */ 2111 2112 /* -------- GPIO_ODERT : (GPIO Offset: 0x04C) ( /W 32) port Output Driver Enable Register - Toggle -------- */ 2113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2114 typedef union { 2115 struct { 2116 uint32_t P0:1; /*!< bit: 0 Output Driver Enable */ 2117 uint32_t P1:1; /*!< bit: 1 Output Driver Enable */ 2118 uint32_t P2:1; /*!< bit: 2 Output Driver Enable */ 2119 uint32_t P3:1; /*!< bit: 3 Output Driver Enable */ 2120 uint32_t P4:1; /*!< bit: 4 Output Driver Enable */ 2121 uint32_t P5:1; /*!< bit: 5 Output Driver Enable */ 2122 uint32_t P6:1; /*!< bit: 6 Output Driver Enable */ 2123 uint32_t P7:1; /*!< bit: 7 Output Driver Enable */ 2124 uint32_t P8:1; /*!< bit: 8 Output Driver Enable */ 2125 uint32_t P9:1; /*!< bit: 9 Output Driver Enable */ 2126 uint32_t P10:1; /*!< bit: 10 Output Driver Enable */ 2127 uint32_t P11:1; /*!< bit: 11 Output Driver Enable */ 2128 uint32_t P12:1; /*!< bit: 12 Output Driver Enable */ 2129 uint32_t P13:1; /*!< bit: 13 Output Driver Enable */ 2130 uint32_t P14:1; /*!< bit: 14 Output Driver Enable */ 2131 uint32_t P15:1; /*!< bit: 15 Output Driver Enable */ 2132 uint32_t P16:1; /*!< bit: 16 Output Driver Enable */ 2133 uint32_t P17:1; /*!< bit: 17 Output Driver Enable */ 2134 uint32_t P18:1; /*!< bit: 18 Output Driver Enable */ 2135 uint32_t P19:1; /*!< bit: 19 Output Driver Enable */ 2136 uint32_t P20:1; /*!< bit: 20 Output Driver Enable */ 2137 uint32_t P21:1; /*!< bit: 21 Output Driver Enable */ 2138 uint32_t P22:1; /*!< bit: 22 Output Driver Enable */ 2139 uint32_t P23:1; /*!< bit: 23 Output Driver Enable */ 2140 uint32_t P24:1; /*!< bit: 24 Output Driver Enable */ 2141 uint32_t P25:1; /*!< bit: 25 Output Driver Enable */ 2142 uint32_t P26:1; /*!< bit: 26 Output Driver Enable */ 2143 uint32_t P27:1; /*!< bit: 27 Output Driver Enable */ 2144 uint32_t P28:1; /*!< bit: 28 Output Driver Enable */ 2145 uint32_t P29:1; /*!< bit: 29 Output Driver Enable */ 2146 uint32_t P30:1; /*!< bit: 30 Output Driver Enable */ 2147 uint32_t P31:1; /*!< bit: 31 Output Driver Enable */ 2148 } bit; /*!< Structure used for bit access */ 2149 uint32_t reg; /*!< Type used for register access */ 2150 } GPIO_ODERT_Type; 2151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2152 2153 #define GPIO_ODERT_OFFSET 0x04C /**< \brief (GPIO_ODERT offset) Output Driver Enable Register - Toggle */ 2154 2155 #define GPIO_ODERT_P0_Pos 0 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2156 #define GPIO_ODERT_P0 (_U_(0x1) << GPIO_ODERT_P0_Pos) 2157 #define GPIO_ODERT_P1_Pos 1 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2158 #define GPIO_ODERT_P1 (_U_(0x1) << GPIO_ODERT_P1_Pos) 2159 #define GPIO_ODERT_P2_Pos 2 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2160 #define GPIO_ODERT_P2 (_U_(0x1) << GPIO_ODERT_P2_Pos) 2161 #define GPIO_ODERT_P3_Pos 3 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2162 #define GPIO_ODERT_P3 (_U_(0x1) << GPIO_ODERT_P3_Pos) 2163 #define GPIO_ODERT_P4_Pos 4 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2164 #define GPIO_ODERT_P4 (_U_(0x1) << GPIO_ODERT_P4_Pos) 2165 #define GPIO_ODERT_P5_Pos 5 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2166 #define GPIO_ODERT_P5 (_U_(0x1) << GPIO_ODERT_P5_Pos) 2167 #define GPIO_ODERT_P6_Pos 6 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2168 #define GPIO_ODERT_P6 (_U_(0x1) << GPIO_ODERT_P6_Pos) 2169 #define GPIO_ODERT_P7_Pos 7 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2170 #define GPIO_ODERT_P7 (_U_(0x1) << GPIO_ODERT_P7_Pos) 2171 #define GPIO_ODERT_P8_Pos 8 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2172 #define GPIO_ODERT_P8 (_U_(0x1) << GPIO_ODERT_P8_Pos) 2173 #define GPIO_ODERT_P9_Pos 9 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2174 #define GPIO_ODERT_P9 (_U_(0x1) << GPIO_ODERT_P9_Pos) 2175 #define GPIO_ODERT_P10_Pos 10 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2176 #define GPIO_ODERT_P10 (_U_(0x1) << GPIO_ODERT_P10_Pos) 2177 #define GPIO_ODERT_P11_Pos 11 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2178 #define GPIO_ODERT_P11 (_U_(0x1) << GPIO_ODERT_P11_Pos) 2179 #define GPIO_ODERT_P12_Pos 12 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2180 #define GPIO_ODERT_P12 (_U_(0x1) << GPIO_ODERT_P12_Pos) 2181 #define GPIO_ODERT_P13_Pos 13 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2182 #define GPIO_ODERT_P13 (_U_(0x1) << GPIO_ODERT_P13_Pos) 2183 #define GPIO_ODERT_P14_Pos 14 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2184 #define GPIO_ODERT_P14 (_U_(0x1) << GPIO_ODERT_P14_Pos) 2185 #define GPIO_ODERT_P15_Pos 15 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2186 #define GPIO_ODERT_P15 (_U_(0x1) << GPIO_ODERT_P15_Pos) 2187 #define GPIO_ODERT_P16_Pos 16 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2188 #define GPIO_ODERT_P16 (_U_(0x1) << GPIO_ODERT_P16_Pos) 2189 #define GPIO_ODERT_P17_Pos 17 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2190 #define GPIO_ODERT_P17 (_U_(0x1) << GPIO_ODERT_P17_Pos) 2191 #define GPIO_ODERT_P18_Pos 18 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2192 #define GPIO_ODERT_P18 (_U_(0x1) << GPIO_ODERT_P18_Pos) 2193 #define GPIO_ODERT_P19_Pos 19 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2194 #define GPIO_ODERT_P19 (_U_(0x1) << GPIO_ODERT_P19_Pos) 2195 #define GPIO_ODERT_P20_Pos 20 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2196 #define GPIO_ODERT_P20 (_U_(0x1) << GPIO_ODERT_P20_Pos) 2197 #define GPIO_ODERT_P21_Pos 21 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2198 #define GPIO_ODERT_P21 (_U_(0x1) << GPIO_ODERT_P21_Pos) 2199 #define GPIO_ODERT_P22_Pos 22 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2200 #define GPIO_ODERT_P22 (_U_(0x1) << GPIO_ODERT_P22_Pos) 2201 #define GPIO_ODERT_P23_Pos 23 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2202 #define GPIO_ODERT_P23 (_U_(0x1) << GPIO_ODERT_P23_Pos) 2203 #define GPIO_ODERT_P24_Pos 24 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2204 #define GPIO_ODERT_P24 (_U_(0x1) << GPIO_ODERT_P24_Pos) 2205 #define GPIO_ODERT_P25_Pos 25 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2206 #define GPIO_ODERT_P25 (_U_(0x1) << GPIO_ODERT_P25_Pos) 2207 #define GPIO_ODERT_P26_Pos 26 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2208 #define GPIO_ODERT_P26 (_U_(0x1) << GPIO_ODERT_P26_Pos) 2209 #define GPIO_ODERT_P27_Pos 27 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2210 #define GPIO_ODERT_P27 (_U_(0x1) << GPIO_ODERT_P27_Pos) 2211 #define GPIO_ODERT_P28_Pos 28 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2212 #define GPIO_ODERT_P28 (_U_(0x1) << GPIO_ODERT_P28_Pos) 2213 #define GPIO_ODERT_P29_Pos 29 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2214 #define GPIO_ODERT_P29 (_U_(0x1) << GPIO_ODERT_P29_Pos) 2215 #define GPIO_ODERT_P30_Pos 30 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2216 #define GPIO_ODERT_P30 (_U_(0x1) << GPIO_ODERT_P30_Pos) 2217 #define GPIO_ODERT_P31_Pos 31 /**< \brief (GPIO_ODERT) Output Driver Enable */ 2218 #define GPIO_ODERT_P31 (_U_(0x1) << GPIO_ODERT_P31_Pos) 2219 #define GPIO_ODERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODERT) MASK Register */ 2220 2221 /* -------- GPIO_OVR : (GPIO Offset: 0x050) (R/W 32) port Output Value Register -------- */ 2222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2223 typedef union { 2224 struct { 2225 uint32_t P0:1; /*!< bit: 0 Output Value */ 2226 uint32_t P1:1; /*!< bit: 1 Output Value */ 2227 uint32_t P2:1; /*!< bit: 2 Output Value */ 2228 uint32_t P3:1; /*!< bit: 3 Output Value */ 2229 uint32_t P4:1; /*!< bit: 4 Output Value */ 2230 uint32_t P5:1; /*!< bit: 5 Output Value */ 2231 uint32_t P6:1; /*!< bit: 6 Output Value */ 2232 uint32_t P7:1; /*!< bit: 7 Output Value */ 2233 uint32_t P8:1; /*!< bit: 8 Output Value */ 2234 uint32_t P9:1; /*!< bit: 9 Output Value */ 2235 uint32_t P10:1; /*!< bit: 10 Output Value */ 2236 uint32_t P11:1; /*!< bit: 11 Output Value */ 2237 uint32_t P12:1; /*!< bit: 12 Output Value */ 2238 uint32_t P13:1; /*!< bit: 13 Output Value */ 2239 uint32_t P14:1; /*!< bit: 14 Output Value */ 2240 uint32_t P15:1; /*!< bit: 15 Output Value */ 2241 uint32_t P16:1; /*!< bit: 16 Output Value */ 2242 uint32_t P17:1; /*!< bit: 17 Output Value */ 2243 uint32_t P18:1; /*!< bit: 18 Output Value */ 2244 uint32_t P19:1; /*!< bit: 19 Output Value */ 2245 uint32_t P20:1; /*!< bit: 20 Output Value */ 2246 uint32_t P21:1; /*!< bit: 21 Output Value */ 2247 uint32_t P22:1; /*!< bit: 22 Output Value */ 2248 uint32_t P23:1; /*!< bit: 23 Output Value */ 2249 uint32_t P24:1; /*!< bit: 24 Output Value */ 2250 uint32_t P25:1; /*!< bit: 25 Output Value */ 2251 uint32_t P26:1; /*!< bit: 26 Output Value */ 2252 uint32_t P27:1; /*!< bit: 27 Output Value */ 2253 uint32_t P28:1; /*!< bit: 28 Output Value */ 2254 uint32_t P29:1; /*!< bit: 29 Output Value */ 2255 uint32_t P30:1; /*!< bit: 30 Output Value */ 2256 uint32_t P31:1; /*!< bit: 31 Output Value */ 2257 } bit; /*!< Structure used for bit access */ 2258 uint32_t reg; /*!< Type used for register access */ 2259 } GPIO_OVR_Type; 2260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2261 2262 #define GPIO_OVR_OFFSET 0x050 /**< \brief (GPIO_OVR offset) Output Value Register */ 2263 2264 #define GPIO_OVR_P0_Pos 0 /**< \brief (GPIO_OVR) Output Value */ 2265 #define GPIO_OVR_P0 (_U_(0x1) << GPIO_OVR_P0_Pos) 2266 #define GPIO_OVR_P1_Pos 1 /**< \brief (GPIO_OVR) Output Value */ 2267 #define GPIO_OVR_P1 (_U_(0x1) << GPIO_OVR_P1_Pos) 2268 #define GPIO_OVR_P2_Pos 2 /**< \brief (GPIO_OVR) Output Value */ 2269 #define GPIO_OVR_P2 (_U_(0x1) << GPIO_OVR_P2_Pos) 2270 #define GPIO_OVR_P3_Pos 3 /**< \brief (GPIO_OVR) Output Value */ 2271 #define GPIO_OVR_P3 (_U_(0x1) << GPIO_OVR_P3_Pos) 2272 #define GPIO_OVR_P4_Pos 4 /**< \brief (GPIO_OVR) Output Value */ 2273 #define GPIO_OVR_P4 (_U_(0x1) << GPIO_OVR_P4_Pos) 2274 #define GPIO_OVR_P5_Pos 5 /**< \brief (GPIO_OVR) Output Value */ 2275 #define GPIO_OVR_P5 (_U_(0x1) << GPIO_OVR_P5_Pos) 2276 #define GPIO_OVR_P6_Pos 6 /**< \brief (GPIO_OVR) Output Value */ 2277 #define GPIO_OVR_P6 (_U_(0x1) << GPIO_OVR_P6_Pos) 2278 #define GPIO_OVR_P7_Pos 7 /**< \brief (GPIO_OVR) Output Value */ 2279 #define GPIO_OVR_P7 (_U_(0x1) << GPIO_OVR_P7_Pos) 2280 #define GPIO_OVR_P8_Pos 8 /**< \brief (GPIO_OVR) Output Value */ 2281 #define GPIO_OVR_P8 (_U_(0x1) << GPIO_OVR_P8_Pos) 2282 #define GPIO_OVR_P9_Pos 9 /**< \brief (GPIO_OVR) Output Value */ 2283 #define GPIO_OVR_P9 (_U_(0x1) << GPIO_OVR_P9_Pos) 2284 #define GPIO_OVR_P10_Pos 10 /**< \brief (GPIO_OVR) Output Value */ 2285 #define GPIO_OVR_P10 (_U_(0x1) << GPIO_OVR_P10_Pos) 2286 #define GPIO_OVR_P11_Pos 11 /**< \brief (GPIO_OVR) Output Value */ 2287 #define GPIO_OVR_P11 (_U_(0x1) << GPIO_OVR_P11_Pos) 2288 #define GPIO_OVR_P12_Pos 12 /**< \brief (GPIO_OVR) Output Value */ 2289 #define GPIO_OVR_P12 (_U_(0x1) << GPIO_OVR_P12_Pos) 2290 #define GPIO_OVR_P13_Pos 13 /**< \brief (GPIO_OVR) Output Value */ 2291 #define GPIO_OVR_P13 (_U_(0x1) << GPIO_OVR_P13_Pos) 2292 #define GPIO_OVR_P14_Pos 14 /**< \brief (GPIO_OVR) Output Value */ 2293 #define GPIO_OVR_P14 (_U_(0x1) << GPIO_OVR_P14_Pos) 2294 #define GPIO_OVR_P15_Pos 15 /**< \brief (GPIO_OVR) Output Value */ 2295 #define GPIO_OVR_P15 (_U_(0x1) << GPIO_OVR_P15_Pos) 2296 #define GPIO_OVR_P16_Pos 16 /**< \brief (GPIO_OVR) Output Value */ 2297 #define GPIO_OVR_P16 (_U_(0x1) << GPIO_OVR_P16_Pos) 2298 #define GPIO_OVR_P17_Pos 17 /**< \brief (GPIO_OVR) Output Value */ 2299 #define GPIO_OVR_P17 (_U_(0x1) << GPIO_OVR_P17_Pos) 2300 #define GPIO_OVR_P18_Pos 18 /**< \brief (GPIO_OVR) Output Value */ 2301 #define GPIO_OVR_P18 (_U_(0x1) << GPIO_OVR_P18_Pos) 2302 #define GPIO_OVR_P19_Pos 19 /**< \brief (GPIO_OVR) Output Value */ 2303 #define GPIO_OVR_P19 (_U_(0x1) << GPIO_OVR_P19_Pos) 2304 #define GPIO_OVR_P20_Pos 20 /**< \brief (GPIO_OVR) Output Value */ 2305 #define GPIO_OVR_P20 (_U_(0x1) << GPIO_OVR_P20_Pos) 2306 #define GPIO_OVR_P21_Pos 21 /**< \brief (GPIO_OVR) Output Value */ 2307 #define GPIO_OVR_P21 (_U_(0x1) << GPIO_OVR_P21_Pos) 2308 #define GPIO_OVR_P22_Pos 22 /**< \brief (GPIO_OVR) Output Value */ 2309 #define GPIO_OVR_P22 (_U_(0x1) << GPIO_OVR_P22_Pos) 2310 #define GPIO_OVR_P23_Pos 23 /**< \brief (GPIO_OVR) Output Value */ 2311 #define GPIO_OVR_P23 (_U_(0x1) << GPIO_OVR_P23_Pos) 2312 #define GPIO_OVR_P24_Pos 24 /**< \brief (GPIO_OVR) Output Value */ 2313 #define GPIO_OVR_P24 (_U_(0x1) << GPIO_OVR_P24_Pos) 2314 #define GPIO_OVR_P25_Pos 25 /**< \brief (GPIO_OVR) Output Value */ 2315 #define GPIO_OVR_P25 (_U_(0x1) << GPIO_OVR_P25_Pos) 2316 #define GPIO_OVR_P26_Pos 26 /**< \brief (GPIO_OVR) Output Value */ 2317 #define GPIO_OVR_P26 (_U_(0x1) << GPIO_OVR_P26_Pos) 2318 #define GPIO_OVR_P27_Pos 27 /**< \brief (GPIO_OVR) Output Value */ 2319 #define GPIO_OVR_P27 (_U_(0x1) << GPIO_OVR_P27_Pos) 2320 #define GPIO_OVR_P28_Pos 28 /**< \brief (GPIO_OVR) Output Value */ 2321 #define GPIO_OVR_P28 (_U_(0x1) << GPIO_OVR_P28_Pos) 2322 #define GPIO_OVR_P29_Pos 29 /**< \brief (GPIO_OVR) Output Value */ 2323 #define GPIO_OVR_P29 (_U_(0x1) << GPIO_OVR_P29_Pos) 2324 #define GPIO_OVR_P30_Pos 30 /**< \brief (GPIO_OVR) Output Value */ 2325 #define GPIO_OVR_P30 (_U_(0x1) << GPIO_OVR_P30_Pos) 2326 #define GPIO_OVR_P31_Pos 31 /**< \brief (GPIO_OVR) Output Value */ 2327 #define GPIO_OVR_P31 (_U_(0x1) << GPIO_OVR_P31_Pos) 2328 #define GPIO_OVR_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OVR) MASK Register */ 2329 2330 /* -------- GPIO_OVRS : (GPIO Offset: 0x054) ( /W 32) port Output Value Register - Set -------- */ 2331 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2332 typedef union { 2333 struct { 2334 uint32_t P0:1; /*!< bit: 0 Output Value */ 2335 uint32_t P1:1; /*!< bit: 1 Output Value */ 2336 uint32_t P2:1; /*!< bit: 2 Output Value */ 2337 uint32_t P3:1; /*!< bit: 3 Output Value */ 2338 uint32_t P4:1; /*!< bit: 4 Output Value */ 2339 uint32_t P5:1; /*!< bit: 5 Output Value */ 2340 uint32_t P6:1; /*!< bit: 6 Output Value */ 2341 uint32_t P7:1; /*!< bit: 7 Output Value */ 2342 uint32_t P8:1; /*!< bit: 8 Output Value */ 2343 uint32_t P9:1; /*!< bit: 9 Output Value */ 2344 uint32_t P10:1; /*!< bit: 10 Output Value */ 2345 uint32_t P11:1; /*!< bit: 11 Output Value */ 2346 uint32_t P12:1; /*!< bit: 12 Output Value */ 2347 uint32_t P13:1; /*!< bit: 13 Output Value */ 2348 uint32_t P14:1; /*!< bit: 14 Output Value */ 2349 uint32_t P15:1; /*!< bit: 15 Output Value */ 2350 uint32_t P16:1; /*!< bit: 16 Output Value */ 2351 uint32_t P17:1; /*!< bit: 17 Output Value */ 2352 uint32_t P18:1; /*!< bit: 18 Output Value */ 2353 uint32_t P19:1; /*!< bit: 19 Output Value */ 2354 uint32_t P20:1; /*!< bit: 20 Output Value */ 2355 uint32_t P21:1; /*!< bit: 21 Output Value */ 2356 uint32_t P22:1; /*!< bit: 22 Output Value */ 2357 uint32_t P23:1; /*!< bit: 23 Output Value */ 2358 uint32_t P24:1; /*!< bit: 24 Output Value */ 2359 uint32_t P25:1; /*!< bit: 25 Output Value */ 2360 uint32_t P26:1; /*!< bit: 26 Output Value */ 2361 uint32_t P27:1; /*!< bit: 27 Output Value */ 2362 uint32_t P28:1; /*!< bit: 28 Output Value */ 2363 uint32_t P29:1; /*!< bit: 29 Output Value */ 2364 uint32_t P30:1; /*!< bit: 30 Output Value */ 2365 uint32_t P31:1; /*!< bit: 31 Output Value */ 2366 } bit; /*!< Structure used for bit access */ 2367 uint32_t reg; /*!< Type used for register access */ 2368 } GPIO_OVRS_Type; 2369 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2370 2371 #define GPIO_OVRS_OFFSET 0x054 /**< \brief (GPIO_OVRS offset) Output Value Register - Set */ 2372 2373 #define GPIO_OVRS_P0_Pos 0 /**< \brief (GPIO_OVRS) Output Value */ 2374 #define GPIO_OVRS_P0 (_U_(0x1) << GPIO_OVRS_P0_Pos) 2375 #define GPIO_OVRS_P1_Pos 1 /**< \brief (GPIO_OVRS) Output Value */ 2376 #define GPIO_OVRS_P1 (_U_(0x1) << GPIO_OVRS_P1_Pos) 2377 #define GPIO_OVRS_P2_Pos 2 /**< \brief (GPIO_OVRS) Output Value */ 2378 #define GPIO_OVRS_P2 (_U_(0x1) << GPIO_OVRS_P2_Pos) 2379 #define GPIO_OVRS_P3_Pos 3 /**< \brief (GPIO_OVRS) Output Value */ 2380 #define GPIO_OVRS_P3 (_U_(0x1) << GPIO_OVRS_P3_Pos) 2381 #define GPIO_OVRS_P4_Pos 4 /**< \brief (GPIO_OVRS) Output Value */ 2382 #define GPIO_OVRS_P4 (_U_(0x1) << GPIO_OVRS_P4_Pos) 2383 #define GPIO_OVRS_P5_Pos 5 /**< \brief (GPIO_OVRS) Output Value */ 2384 #define GPIO_OVRS_P5 (_U_(0x1) << GPIO_OVRS_P5_Pos) 2385 #define GPIO_OVRS_P6_Pos 6 /**< \brief (GPIO_OVRS) Output Value */ 2386 #define GPIO_OVRS_P6 (_U_(0x1) << GPIO_OVRS_P6_Pos) 2387 #define GPIO_OVRS_P7_Pos 7 /**< \brief (GPIO_OVRS) Output Value */ 2388 #define GPIO_OVRS_P7 (_U_(0x1) << GPIO_OVRS_P7_Pos) 2389 #define GPIO_OVRS_P8_Pos 8 /**< \brief (GPIO_OVRS) Output Value */ 2390 #define GPIO_OVRS_P8 (_U_(0x1) << GPIO_OVRS_P8_Pos) 2391 #define GPIO_OVRS_P9_Pos 9 /**< \brief (GPIO_OVRS) Output Value */ 2392 #define GPIO_OVRS_P9 (_U_(0x1) << GPIO_OVRS_P9_Pos) 2393 #define GPIO_OVRS_P10_Pos 10 /**< \brief (GPIO_OVRS) Output Value */ 2394 #define GPIO_OVRS_P10 (_U_(0x1) << GPIO_OVRS_P10_Pos) 2395 #define GPIO_OVRS_P11_Pos 11 /**< \brief (GPIO_OVRS) Output Value */ 2396 #define GPIO_OVRS_P11 (_U_(0x1) << GPIO_OVRS_P11_Pos) 2397 #define GPIO_OVRS_P12_Pos 12 /**< \brief (GPIO_OVRS) Output Value */ 2398 #define GPIO_OVRS_P12 (_U_(0x1) << GPIO_OVRS_P12_Pos) 2399 #define GPIO_OVRS_P13_Pos 13 /**< \brief (GPIO_OVRS) Output Value */ 2400 #define GPIO_OVRS_P13 (_U_(0x1) << GPIO_OVRS_P13_Pos) 2401 #define GPIO_OVRS_P14_Pos 14 /**< \brief (GPIO_OVRS) Output Value */ 2402 #define GPIO_OVRS_P14 (_U_(0x1) << GPIO_OVRS_P14_Pos) 2403 #define GPIO_OVRS_P15_Pos 15 /**< \brief (GPIO_OVRS) Output Value */ 2404 #define GPIO_OVRS_P15 (_U_(0x1) << GPIO_OVRS_P15_Pos) 2405 #define GPIO_OVRS_P16_Pos 16 /**< \brief (GPIO_OVRS) Output Value */ 2406 #define GPIO_OVRS_P16 (_U_(0x1) << GPIO_OVRS_P16_Pos) 2407 #define GPIO_OVRS_P17_Pos 17 /**< \brief (GPIO_OVRS) Output Value */ 2408 #define GPIO_OVRS_P17 (_U_(0x1) << GPIO_OVRS_P17_Pos) 2409 #define GPIO_OVRS_P18_Pos 18 /**< \brief (GPIO_OVRS) Output Value */ 2410 #define GPIO_OVRS_P18 (_U_(0x1) << GPIO_OVRS_P18_Pos) 2411 #define GPIO_OVRS_P19_Pos 19 /**< \brief (GPIO_OVRS) Output Value */ 2412 #define GPIO_OVRS_P19 (_U_(0x1) << GPIO_OVRS_P19_Pos) 2413 #define GPIO_OVRS_P20_Pos 20 /**< \brief (GPIO_OVRS) Output Value */ 2414 #define GPIO_OVRS_P20 (_U_(0x1) << GPIO_OVRS_P20_Pos) 2415 #define GPIO_OVRS_P21_Pos 21 /**< \brief (GPIO_OVRS) Output Value */ 2416 #define GPIO_OVRS_P21 (_U_(0x1) << GPIO_OVRS_P21_Pos) 2417 #define GPIO_OVRS_P22_Pos 22 /**< \brief (GPIO_OVRS) Output Value */ 2418 #define GPIO_OVRS_P22 (_U_(0x1) << GPIO_OVRS_P22_Pos) 2419 #define GPIO_OVRS_P23_Pos 23 /**< \brief (GPIO_OVRS) Output Value */ 2420 #define GPIO_OVRS_P23 (_U_(0x1) << GPIO_OVRS_P23_Pos) 2421 #define GPIO_OVRS_P24_Pos 24 /**< \brief (GPIO_OVRS) Output Value */ 2422 #define GPIO_OVRS_P24 (_U_(0x1) << GPIO_OVRS_P24_Pos) 2423 #define GPIO_OVRS_P25_Pos 25 /**< \brief (GPIO_OVRS) Output Value */ 2424 #define GPIO_OVRS_P25 (_U_(0x1) << GPIO_OVRS_P25_Pos) 2425 #define GPIO_OVRS_P26_Pos 26 /**< \brief (GPIO_OVRS) Output Value */ 2426 #define GPIO_OVRS_P26 (_U_(0x1) << GPIO_OVRS_P26_Pos) 2427 #define GPIO_OVRS_P27_Pos 27 /**< \brief (GPIO_OVRS) Output Value */ 2428 #define GPIO_OVRS_P27 (_U_(0x1) << GPIO_OVRS_P27_Pos) 2429 #define GPIO_OVRS_P28_Pos 28 /**< \brief (GPIO_OVRS) Output Value */ 2430 #define GPIO_OVRS_P28 (_U_(0x1) << GPIO_OVRS_P28_Pos) 2431 #define GPIO_OVRS_P29_Pos 29 /**< \brief (GPIO_OVRS) Output Value */ 2432 #define GPIO_OVRS_P29 (_U_(0x1) << GPIO_OVRS_P29_Pos) 2433 #define GPIO_OVRS_P30_Pos 30 /**< \brief (GPIO_OVRS) Output Value */ 2434 #define GPIO_OVRS_P30 (_U_(0x1) << GPIO_OVRS_P30_Pos) 2435 #define GPIO_OVRS_P31_Pos 31 /**< \brief (GPIO_OVRS) Output Value */ 2436 #define GPIO_OVRS_P31 (_U_(0x1) << GPIO_OVRS_P31_Pos) 2437 #define GPIO_OVRS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OVRS) MASK Register */ 2438 2439 /* -------- GPIO_OVRC : (GPIO Offset: 0x058) ( /W 32) port Output Value Register - Clear -------- */ 2440 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2441 typedef union { 2442 struct { 2443 uint32_t P0:1; /*!< bit: 0 Output Value */ 2444 uint32_t P1:1; /*!< bit: 1 Output Value */ 2445 uint32_t P2:1; /*!< bit: 2 Output Value */ 2446 uint32_t P3:1; /*!< bit: 3 Output Value */ 2447 uint32_t P4:1; /*!< bit: 4 Output Value */ 2448 uint32_t P5:1; /*!< bit: 5 Output Value */ 2449 uint32_t P6:1; /*!< bit: 6 Output Value */ 2450 uint32_t P7:1; /*!< bit: 7 Output Value */ 2451 uint32_t P8:1; /*!< bit: 8 Output Value */ 2452 uint32_t P9:1; /*!< bit: 9 Output Value */ 2453 uint32_t P10:1; /*!< bit: 10 Output Value */ 2454 uint32_t P11:1; /*!< bit: 11 Output Value */ 2455 uint32_t P12:1; /*!< bit: 12 Output Value */ 2456 uint32_t P13:1; /*!< bit: 13 Output Value */ 2457 uint32_t P14:1; /*!< bit: 14 Output Value */ 2458 uint32_t P15:1; /*!< bit: 15 Output Value */ 2459 uint32_t P16:1; /*!< bit: 16 Output Value */ 2460 uint32_t P17:1; /*!< bit: 17 Output Value */ 2461 uint32_t P18:1; /*!< bit: 18 Output Value */ 2462 uint32_t P19:1; /*!< bit: 19 Output Value */ 2463 uint32_t P20:1; /*!< bit: 20 Output Value */ 2464 uint32_t P21:1; /*!< bit: 21 Output Value */ 2465 uint32_t P22:1; /*!< bit: 22 Output Value */ 2466 uint32_t P23:1; /*!< bit: 23 Output Value */ 2467 uint32_t P24:1; /*!< bit: 24 Output Value */ 2468 uint32_t P25:1; /*!< bit: 25 Output Value */ 2469 uint32_t P26:1; /*!< bit: 26 Output Value */ 2470 uint32_t P27:1; /*!< bit: 27 Output Value */ 2471 uint32_t P28:1; /*!< bit: 28 Output Value */ 2472 uint32_t P29:1; /*!< bit: 29 Output Value */ 2473 uint32_t P30:1; /*!< bit: 30 Output Value */ 2474 uint32_t P31:1; /*!< bit: 31 Output Value */ 2475 } bit; /*!< Structure used for bit access */ 2476 uint32_t reg; /*!< Type used for register access */ 2477 } GPIO_OVRC_Type; 2478 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2479 2480 #define GPIO_OVRC_OFFSET 0x058 /**< \brief (GPIO_OVRC offset) Output Value Register - Clear */ 2481 2482 #define GPIO_OVRC_P0_Pos 0 /**< \brief (GPIO_OVRC) Output Value */ 2483 #define GPIO_OVRC_P0 (_U_(0x1) << GPIO_OVRC_P0_Pos) 2484 #define GPIO_OVRC_P1_Pos 1 /**< \brief (GPIO_OVRC) Output Value */ 2485 #define GPIO_OVRC_P1 (_U_(0x1) << GPIO_OVRC_P1_Pos) 2486 #define GPIO_OVRC_P2_Pos 2 /**< \brief (GPIO_OVRC) Output Value */ 2487 #define GPIO_OVRC_P2 (_U_(0x1) << GPIO_OVRC_P2_Pos) 2488 #define GPIO_OVRC_P3_Pos 3 /**< \brief (GPIO_OVRC) Output Value */ 2489 #define GPIO_OVRC_P3 (_U_(0x1) << GPIO_OVRC_P3_Pos) 2490 #define GPIO_OVRC_P4_Pos 4 /**< \brief (GPIO_OVRC) Output Value */ 2491 #define GPIO_OVRC_P4 (_U_(0x1) << GPIO_OVRC_P4_Pos) 2492 #define GPIO_OVRC_P5_Pos 5 /**< \brief (GPIO_OVRC) Output Value */ 2493 #define GPIO_OVRC_P5 (_U_(0x1) << GPIO_OVRC_P5_Pos) 2494 #define GPIO_OVRC_P6_Pos 6 /**< \brief (GPIO_OVRC) Output Value */ 2495 #define GPIO_OVRC_P6 (_U_(0x1) << GPIO_OVRC_P6_Pos) 2496 #define GPIO_OVRC_P7_Pos 7 /**< \brief (GPIO_OVRC) Output Value */ 2497 #define GPIO_OVRC_P7 (_U_(0x1) << GPIO_OVRC_P7_Pos) 2498 #define GPIO_OVRC_P8_Pos 8 /**< \brief (GPIO_OVRC) Output Value */ 2499 #define GPIO_OVRC_P8 (_U_(0x1) << GPIO_OVRC_P8_Pos) 2500 #define GPIO_OVRC_P9_Pos 9 /**< \brief (GPIO_OVRC) Output Value */ 2501 #define GPIO_OVRC_P9 (_U_(0x1) << GPIO_OVRC_P9_Pos) 2502 #define GPIO_OVRC_P10_Pos 10 /**< \brief (GPIO_OVRC) Output Value */ 2503 #define GPIO_OVRC_P10 (_U_(0x1) << GPIO_OVRC_P10_Pos) 2504 #define GPIO_OVRC_P11_Pos 11 /**< \brief (GPIO_OVRC) Output Value */ 2505 #define GPIO_OVRC_P11 (_U_(0x1) << GPIO_OVRC_P11_Pos) 2506 #define GPIO_OVRC_P12_Pos 12 /**< \brief (GPIO_OVRC) Output Value */ 2507 #define GPIO_OVRC_P12 (_U_(0x1) << GPIO_OVRC_P12_Pos) 2508 #define GPIO_OVRC_P13_Pos 13 /**< \brief (GPIO_OVRC) Output Value */ 2509 #define GPIO_OVRC_P13 (_U_(0x1) << GPIO_OVRC_P13_Pos) 2510 #define GPIO_OVRC_P14_Pos 14 /**< \brief (GPIO_OVRC) Output Value */ 2511 #define GPIO_OVRC_P14 (_U_(0x1) << GPIO_OVRC_P14_Pos) 2512 #define GPIO_OVRC_P15_Pos 15 /**< \brief (GPIO_OVRC) Output Value */ 2513 #define GPIO_OVRC_P15 (_U_(0x1) << GPIO_OVRC_P15_Pos) 2514 #define GPIO_OVRC_P16_Pos 16 /**< \brief (GPIO_OVRC) Output Value */ 2515 #define GPIO_OVRC_P16 (_U_(0x1) << GPIO_OVRC_P16_Pos) 2516 #define GPIO_OVRC_P17_Pos 17 /**< \brief (GPIO_OVRC) Output Value */ 2517 #define GPIO_OVRC_P17 (_U_(0x1) << GPIO_OVRC_P17_Pos) 2518 #define GPIO_OVRC_P18_Pos 18 /**< \brief (GPIO_OVRC) Output Value */ 2519 #define GPIO_OVRC_P18 (_U_(0x1) << GPIO_OVRC_P18_Pos) 2520 #define GPIO_OVRC_P19_Pos 19 /**< \brief (GPIO_OVRC) Output Value */ 2521 #define GPIO_OVRC_P19 (_U_(0x1) << GPIO_OVRC_P19_Pos) 2522 #define GPIO_OVRC_P20_Pos 20 /**< \brief (GPIO_OVRC) Output Value */ 2523 #define GPIO_OVRC_P20 (_U_(0x1) << GPIO_OVRC_P20_Pos) 2524 #define GPIO_OVRC_P21_Pos 21 /**< \brief (GPIO_OVRC) Output Value */ 2525 #define GPIO_OVRC_P21 (_U_(0x1) << GPIO_OVRC_P21_Pos) 2526 #define GPIO_OVRC_P22_Pos 22 /**< \brief (GPIO_OVRC) Output Value */ 2527 #define GPIO_OVRC_P22 (_U_(0x1) << GPIO_OVRC_P22_Pos) 2528 #define GPIO_OVRC_P23_Pos 23 /**< \brief (GPIO_OVRC) Output Value */ 2529 #define GPIO_OVRC_P23 (_U_(0x1) << GPIO_OVRC_P23_Pos) 2530 #define GPIO_OVRC_P24_Pos 24 /**< \brief (GPIO_OVRC) Output Value */ 2531 #define GPIO_OVRC_P24 (_U_(0x1) << GPIO_OVRC_P24_Pos) 2532 #define GPIO_OVRC_P25_Pos 25 /**< \brief (GPIO_OVRC) Output Value */ 2533 #define GPIO_OVRC_P25 (_U_(0x1) << GPIO_OVRC_P25_Pos) 2534 #define GPIO_OVRC_P26_Pos 26 /**< \brief (GPIO_OVRC) Output Value */ 2535 #define GPIO_OVRC_P26 (_U_(0x1) << GPIO_OVRC_P26_Pos) 2536 #define GPIO_OVRC_P27_Pos 27 /**< \brief (GPIO_OVRC) Output Value */ 2537 #define GPIO_OVRC_P27 (_U_(0x1) << GPIO_OVRC_P27_Pos) 2538 #define GPIO_OVRC_P28_Pos 28 /**< \brief (GPIO_OVRC) Output Value */ 2539 #define GPIO_OVRC_P28 (_U_(0x1) << GPIO_OVRC_P28_Pos) 2540 #define GPIO_OVRC_P29_Pos 29 /**< \brief (GPIO_OVRC) Output Value */ 2541 #define GPIO_OVRC_P29 (_U_(0x1) << GPIO_OVRC_P29_Pos) 2542 #define GPIO_OVRC_P30_Pos 30 /**< \brief (GPIO_OVRC) Output Value */ 2543 #define GPIO_OVRC_P30 (_U_(0x1) << GPIO_OVRC_P30_Pos) 2544 #define GPIO_OVRC_P31_Pos 31 /**< \brief (GPIO_OVRC) Output Value */ 2545 #define GPIO_OVRC_P31 (_U_(0x1) << GPIO_OVRC_P31_Pos) 2546 #define GPIO_OVRC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OVRC) MASK Register */ 2547 2548 /* -------- GPIO_OVRT : (GPIO Offset: 0x05C) ( /W 32) port Output Value Register - Toggle -------- */ 2549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2550 typedef union { 2551 struct { 2552 uint32_t P0:1; /*!< bit: 0 Output Value */ 2553 uint32_t P1:1; /*!< bit: 1 Output Value */ 2554 uint32_t P2:1; /*!< bit: 2 Output Value */ 2555 uint32_t P3:1; /*!< bit: 3 Output Value */ 2556 uint32_t P4:1; /*!< bit: 4 Output Value */ 2557 uint32_t P5:1; /*!< bit: 5 Output Value */ 2558 uint32_t P6:1; /*!< bit: 6 Output Value */ 2559 uint32_t P7:1; /*!< bit: 7 Output Value */ 2560 uint32_t P8:1; /*!< bit: 8 Output Value */ 2561 uint32_t P9:1; /*!< bit: 9 Output Value */ 2562 uint32_t P10:1; /*!< bit: 10 Output Value */ 2563 uint32_t P11:1; /*!< bit: 11 Output Value */ 2564 uint32_t P12:1; /*!< bit: 12 Output Value */ 2565 uint32_t P13:1; /*!< bit: 13 Output Value */ 2566 uint32_t P14:1; /*!< bit: 14 Output Value */ 2567 uint32_t P15:1; /*!< bit: 15 Output Value */ 2568 uint32_t P16:1; /*!< bit: 16 Output Value */ 2569 uint32_t P17:1; /*!< bit: 17 Output Value */ 2570 uint32_t P18:1; /*!< bit: 18 Output Value */ 2571 uint32_t P19:1; /*!< bit: 19 Output Value */ 2572 uint32_t P20:1; /*!< bit: 20 Output Value */ 2573 uint32_t P21:1; /*!< bit: 21 Output Value */ 2574 uint32_t P22:1; /*!< bit: 22 Output Value */ 2575 uint32_t P23:1; /*!< bit: 23 Output Value */ 2576 uint32_t P24:1; /*!< bit: 24 Output Value */ 2577 uint32_t P25:1; /*!< bit: 25 Output Value */ 2578 uint32_t P26:1; /*!< bit: 26 Output Value */ 2579 uint32_t P27:1; /*!< bit: 27 Output Value */ 2580 uint32_t P28:1; /*!< bit: 28 Output Value */ 2581 uint32_t P29:1; /*!< bit: 29 Output Value */ 2582 uint32_t P30:1; /*!< bit: 30 Output Value */ 2583 uint32_t P31:1; /*!< bit: 31 Output Value */ 2584 } bit; /*!< Structure used for bit access */ 2585 uint32_t reg; /*!< Type used for register access */ 2586 } GPIO_OVRT_Type; 2587 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2588 2589 #define GPIO_OVRT_OFFSET 0x05C /**< \brief (GPIO_OVRT offset) Output Value Register - Toggle */ 2590 2591 #define GPIO_OVRT_P0_Pos 0 /**< \brief (GPIO_OVRT) Output Value */ 2592 #define GPIO_OVRT_P0 (_U_(0x1) << GPIO_OVRT_P0_Pos) 2593 #define GPIO_OVRT_P1_Pos 1 /**< \brief (GPIO_OVRT) Output Value */ 2594 #define GPIO_OVRT_P1 (_U_(0x1) << GPIO_OVRT_P1_Pos) 2595 #define GPIO_OVRT_P2_Pos 2 /**< \brief (GPIO_OVRT) Output Value */ 2596 #define GPIO_OVRT_P2 (_U_(0x1) << GPIO_OVRT_P2_Pos) 2597 #define GPIO_OVRT_P3_Pos 3 /**< \brief (GPIO_OVRT) Output Value */ 2598 #define GPIO_OVRT_P3 (_U_(0x1) << GPIO_OVRT_P3_Pos) 2599 #define GPIO_OVRT_P4_Pos 4 /**< \brief (GPIO_OVRT) Output Value */ 2600 #define GPIO_OVRT_P4 (_U_(0x1) << GPIO_OVRT_P4_Pos) 2601 #define GPIO_OVRT_P5_Pos 5 /**< \brief (GPIO_OVRT) Output Value */ 2602 #define GPIO_OVRT_P5 (_U_(0x1) << GPIO_OVRT_P5_Pos) 2603 #define GPIO_OVRT_P6_Pos 6 /**< \brief (GPIO_OVRT) Output Value */ 2604 #define GPIO_OVRT_P6 (_U_(0x1) << GPIO_OVRT_P6_Pos) 2605 #define GPIO_OVRT_P7_Pos 7 /**< \brief (GPIO_OVRT) Output Value */ 2606 #define GPIO_OVRT_P7 (_U_(0x1) << GPIO_OVRT_P7_Pos) 2607 #define GPIO_OVRT_P8_Pos 8 /**< \brief (GPIO_OVRT) Output Value */ 2608 #define GPIO_OVRT_P8 (_U_(0x1) << GPIO_OVRT_P8_Pos) 2609 #define GPIO_OVRT_P9_Pos 9 /**< \brief (GPIO_OVRT) Output Value */ 2610 #define GPIO_OVRT_P9 (_U_(0x1) << GPIO_OVRT_P9_Pos) 2611 #define GPIO_OVRT_P10_Pos 10 /**< \brief (GPIO_OVRT) Output Value */ 2612 #define GPIO_OVRT_P10 (_U_(0x1) << GPIO_OVRT_P10_Pos) 2613 #define GPIO_OVRT_P11_Pos 11 /**< \brief (GPIO_OVRT) Output Value */ 2614 #define GPIO_OVRT_P11 (_U_(0x1) << GPIO_OVRT_P11_Pos) 2615 #define GPIO_OVRT_P12_Pos 12 /**< \brief (GPIO_OVRT) Output Value */ 2616 #define GPIO_OVRT_P12 (_U_(0x1) << GPIO_OVRT_P12_Pos) 2617 #define GPIO_OVRT_P13_Pos 13 /**< \brief (GPIO_OVRT) Output Value */ 2618 #define GPIO_OVRT_P13 (_U_(0x1) << GPIO_OVRT_P13_Pos) 2619 #define GPIO_OVRT_P14_Pos 14 /**< \brief (GPIO_OVRT) Output Value */ 2620 #define GPIO_OVRT_P14 (_U_(0x1) << GPIO_OVRT_P14_Pos) 2621 #define GPIO_OVRT_P15_Pos 15 /**< \brief (GPIO_OVRT) Output Value */ 2622 #define GPIO_OVRT_P15 (_U_(0x1) << GPIO_OVRT_P15_Pos) 2623 #define GPIO_OVRT_P16_Pos 16 /**< \brief (GPIO_OVRT) Output Value */ 2624 #define GPIO_OVRT_P16 (_U_(0x1) << GPIO_OVRT_P16_Pos) 2625 #define GPIO_OVRT_P17_Pos 17 /**< \brief (GPIO_OVRT) Output Value */ 2626 #define GPIO_OVRT_P17 (_U_(0x1) << GPIO_OVRT_P17_Pos) 2627 #define GPIO_OVRT_P18_Pos 18 /**< \brief (GPIO_OVRT) Output Value */ 2628 #define GPIO_OVRT_P18 (_U_(0x1) << GPIO_OVRT_P18_Pos) 2629 #define GPIO_OVRT_P19_Pos 19 /**< \brief (GPIO_OVRT) Output Value */ 2630 #define GPIO_OVRT_P19 (_U_(0x1) << GPIO_OVRT_P19_Pos) 2631 #define GPIO_OVRT_P20_Pos 20 /**< \brief (GPIO_OVRT) Output Value */ 2632 #define GPIO_OVRT_P20 (_U_(0x1) << GPIO_OVRT_P20_Pos) 2633 #define GPIO_OVRT_P21_Pos 21 /**< \brief (GPIO_OVRT) Output Value */ 2634 #define GPIO_OVRT_P21 (_U_(0x1) << GPIO_OVRT_P21_Pos) 2635 #define GPIO_OVRT_P22_Pos 22 /**< \brief (GPIO_OVRT) Output Value */ 2636 #define GPIO_OVRT_P22 (_U_(0x1) << GPIO_OVRT_P22_Pos) 2637 #define GPIO_OVRT_P23_Pos 23 /**< \brief (GPIO_OVRT) Output Value */ 2638 #define GPIO_OVRT_P23 (_U_(0x1) << GPIO_OVRT_P23_Pos) 2639 #define GPIO_OVRT_P24_Pos 24 /**< \brief (GPIO_OVRT) Output Value */ 2640 #define GPIO_OVRT_P24 (_U_(0x1) << GPIO_OVRT_P24_Pos) 2641 #define GPIO_OVRT_P25_Pos 25 /**< \brief (GPIO_OVRT) Output Value */ 2642 #define GPIO_OVRT_P25 (_U_(0x1) << GPIO_OVRT_P25_Pos) 2643 #define GPIO_OVRT_P26_Pos 26 /**< \brief (GPIO_OVRT) Output Value */ 2644 #define GPIO_OVRT_P26 (_U_(0x1) << GPIO_OVRT_P26_Pos) 2645 #define GPIO_OVRT_P27_Pos 27 /**< \brief (GPIO_OVRT) Output Value */ 2646 #define GPIO_OVRT_P27 (_U_(0x1) << GPIO_OVRT_P27_Pos) 2647 #define GPIO_OVRT_P28_Pos 28 /**< \brief (GPIO_OVRT) Output Value */ 2648 #define GPIO_OVRT_P28 (_U_(0x1) << GPIO_OVRT_P28_Pos) 2649 #define GPIO_OVRT_P29_Pos 29 /**< \brief (GPIO_OVRT) Output Value */ 2650 #define GPIO_OVRT_P29 (_U_(0x1) << GPIO_OVRT_P29_Pos) 2651 #define GPIO_OVRT_P30_Pos 30 /**< \brief (GPIO_OVRT) Output Value */ 2652 #define GPIO_OVRT_P30 (_U_(0x1) << GPIO_OVRT_P30_Pos) 2653 #define GPIO_OVRT_P31_Pos 31 /**< \brief (GPIO_OVRT) Output Value */ 2654 #define GPIO_OVRT_P31 (_U_(0x1) << GPIO_OVRT_P31_Pos) 2655 #define GPIO_OVRT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OVRT) MASK Register */ 2656 2657 /* -------- GPIO_PVR : (GPIO Offset: 0x060) (R/ 32) port Pin Value Register -------- */ 2658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2659 typedef union { 2660 struct { 2661 uint32_t P0:1; /*!< bit: 0 Pin Value */ 2662 uint32_t P1:1; /*!< bit: 1 Pin Value */ 2663 uint32_t P2:1; /*!< bit: 2 Pin Value */ 2664 uint32_t P3:1; /*!< bit: 3 Pin Value */ 2665 uint32_t P4:1; /*!< bit: 4 Pin Value */ 2666 uint32_t P5:1; /*!< bit: 5 Pin Value */ 2667 uint32_t P6:1; /*!< bit: 6 Pin Value */ 2668 uint32_t P7:1; /*!< bit: 7 Pin Value */ 2669 uint32_t P8:1; /*!< bit: 8 Pin Value */ 2670 uint32_t P9:1; /*!< bit: 9 Pin Value */ 2671 uint32_t P10:1; /*!< bit: 10 Pin Value */ 2672 uint32_t P11:1; /*!< bit: 11 Pin Value */ 2673 uint32_t P12:1; /*!< bit: 12 Pin Value */ 2674 uint32_t P13:1; /*!< bit: 13 Pin Value */ 2675 uint32_t P14:1; /*!< bit: 14 Pin Value */ 2676 uint32_t P15:1; /*!< bit: 15 Pin Value */ 2677 uint32_t P16:1; /*!< bit: 16 Pin Value */ 2678 uint32_t P17:1; /*!< bit: 17 Pin Value */ 2679 uint32_t P18:1; /*!< bit: 18 Pin Value */ 2680 uint32_t P19:1; /*!< bit: 19 Pin Value */ 2681 uint32_t P20:1; /*!< bit: 20 Pin Value */ 2682 uint32_t P21:1; /*!< bit: 21 Pin Value */ 2683 uint32_t P22:1; /*!< bit: 22 Pin Value */ 2684 uint32_t P23:1; /*!< bit: 23 Pin Value */ 2685 uint32_t P24:1; /*!< bit: 24 Pin Value */ 2686 uint32_t P25:1; /*!< bit: 25 Pin Value */ 2687 uint32_t P26:1; /*!< bit: 26 Pin Value */ 2688 uint32_t P27:1; /*!< bit: 27 Pin Value */ 2689 uint32_t P28:1; /*!< bit: 28 Pin Value */ 2690 uint32_t P29:1; /*!< bit: 29 Pin Value */ 2691 uint32_t P30:1; /*!< bit: 30 Pin Value */ 2692 uint32_t P31:1; /*!< bit: 31 Pin Value */ 2693 } bit; /*!< Structure used for bit access */ 2694 uint32_t reg; /*!< Type used for register access */ 2695 } GPIO_PVR_Type; 2696 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2697 2698 #define GPIO_PVR_OFFSET 0x060 /**< \brief (GPIO_PVR offset) Pin Value Register */ 2699 2700 #define GPIO_PVR_P0_Pos 0 /**< \brief (GPIO_PVR) Pin Value */ 2701 #define GPIO_PVR_P0 (_U_(0x1) << GPIO_PVR_P0_Pos) 2702 #define GPIO_PVR_P1_Pos 1 /**< \brief (GPIO_PVR) Pin Value */ 2703 #define GPIO_PVR_P1 (_U_(0x1) << GPIO_PVR_P1_Pos) 2704 #define GPIO_PVR_P2_Pos 2 /**< \brief (GPIO_PVR) Pin Value */ 2705 #define GPIO_PVR_P2 (_U_(0x1) << GPIO_PVR_P2_Pos) 2706 #define GPIO_PVR_P3_Pos 3 /**< \brief (GPIO_PVR) Pin Value */ 2707 #define GPIO_PVR_P3 (_U_(0x1) << GPIO_PVR_P3_Pos) 2708 #define GPIO_PVR_P4_Pos 4 /**< \brief (GPIO_PVR) Pin Value */ 2709 #define GPIO_PVR_P4 (_U_(0x1) << GPIO_PVR_P4_Pos) 2710 #define GPIO_PVR_P5_Pos 5 /**< \brief (GPIO_PVR) Pin Value */ 2711 #define GPIO_PVR_P5 (_U_(0x1) << GPIO_PVR_P5_Pos) 2712 #define GPIO_PVR_P6_Pos 6 /**< \brief (GPIO_PVR) Pin Value */ 2713 #define GPIO_PVR_P6 (_U_(0x1) << GPIO_PVR_P6_Pos) 2714 #define GPIO_PVR_P7_Pos 7 /**< \brief (GPIO_PVR) Pin Value */ 2715 #define GPIO_PVR_P7 (_U_(0x1) << GPIO_PVR_P7_Pos) 2716 #define GPIO_PVR_P8_Pos 8 /**< \brief (GPIO_PVR) Pin Value */ 2717 #define GPIO_PVR_P8 (_U_(0x1) << GPIO_PVR_P8_Pos) 2718 #define GPIO_PVR_P9_Pos 9 /**< \brief (GPIO_PVR) Pin Value */ 2719 #define GPIO_PVR_P9 (_U_(0x1) << GPIO_PVR_P9_Pos) 2720 #define GPIO_PVR_P10_Pos 10 /**< \brief (GPIO_PVR) Pin Value */ 2721 #define GPIO_PVR_P10 (_U_(0x1) << GPIO_PVR_P10_Pos) 2722 #define GPIO_PVR_P11_Pos 11 /**< \brief (GPIO_PVR) Pin Value */ 2723 #define GPIO_PVR_P11 (_U_(0x1) << GPIO_PVR_P11_Pos) 2724 #define GPIO_PVR_P12_Pos 12 /**< \brief (GPIO_PVR) Pin Value */ 2725 #define GPIO_PVR_P12 (_U_(0x1) << GPIO_PVR_P12_Pos) 2726 #define GPIO_PVR_P13_Pos 13 /**< \brief (GPIO_PVR) Pin Value */ 2727 #define GPIO_PVR_P13 (_U_(0x1) << GPIO_PVR_P13_Pos) 2728 #define GPIO_PVR_P14_Pos 14 /**< \brief (GPIO_PVR) Pin Value */ 2729 #define GPIO_PVR_P14 (_U_(0x1) << GPIO_PVR_P14_Pos) 2730 #define GPIO_PVR_P15_Pos 15 /**< \brief (GPIO_PVR) Pin Value */ 2731 #define GPIO_PVR_P15 (_U_(0x1) << GPIO_PVR_P15_Pos) 2732 #define GPIO_PVR_P16_Pos 16 /**< \brief (GPIO_PVR) Pin Value */ 2733 #define GPIO_PVR_P16 (_U_(0x1) << GPIO_PVR_P16_Pos) 2734 #define GPIO_PVR_P17_Pos 17 /**< \brief (GPIO_PVR) Pin Value */ 2735 #define GPIO_PVR_P17 (_U_(0x1) << GPIO_PVR_P17_Pos) 2736 #define GPIO_PVR_P18_Pos 18 /**< \brief (GPIO_PVR) Pin Value */ 2737 #define GPIO_PVR_P18 (_U_(0x1) << GPIO_PVR_P18_Pos) 2738 #define GPIO_PVR_P19_Pos 19 /**< \brief (GPIO_PVR) Pin Value */ 2739 #define GPIO_PVR_P19 (_U_(0x1) << GPIO_PVR_P19_Pos) 2740 #define GPIO_PVR_P20_Pos 20 /**< \brief (GPIO_PVR) Pin Value */ 2741 #define GPIO_PVR_P20 (_U_(0x1) << GPIO_PVR_P20_Pos) 2742 #define GPIO_PVR_P21_Pos 21 /**< \brief (GPIO_PVR) Pin Value */ 2743 #define GPIO_PVR_P21 (_U_(0x1) << GPIO_PVR_P21_Pos) 2744 #define GPIO_PVR_P22_Pos 22 /**< \brief (GPIO_PVR) Pin Value */ 2745 #define GPIO_PVR_P22 (_U_(0x1) << GPIO_PVR_P22_Pos) 2746 #define GPIO_PVR_P23_Pos 23 /**< \brief (GPIO_PVR) Pin Value */ 2747 #define GPIO_PVR_P23 (_U_(0x1) << GPIO_PVR_P23_Pos) 2748 #define GPIO_PVR_P24_Pos 24 /**< \brief (GPIO_PVR) Pin Value */ 2749 #define GPIO_PVR_P24 (_U_(0x1) << GPIO_PVR_P24_Pos) 2750 #define GPIO_PVR_P25_Pos 25 /**< \brief (GPIO_PVR) Pin Value */ 2751 #define GPIO_PVR_P25 (_U_(0x1) << GPIO_PVR_P25_Pos) 2752 #define GPIO_PVR_P26_Pos 26 /**< \brief (GPIO_PVR) Pin Value */ 2753 #define GPIO_PVR_P26 (_U_(0x1) << GPIO_PVR_P26_Pos) 2754 #define GPIO_PVR_P27_Pos 27 /**< \brief (GPIO_PVR) Pin Value */ 2755 #define GPIO_PVR_P27 (_U_(0x1) << GPIO_PVR_P27_Pos) 2756 #define GPIO_PVR_P28_Pos 28 /**< \brief (GPIO_PVR) Pin Value */ 2757 #define GPIO_PVR_P28 (_U_(0x1) << GPIO_PVR_P28_Pos) 2758 #define GPIO_PVR_P29_Pos 29 /**< \brief (GPIO_PVR) Pin Value */ 2759 #define GPIO_PVR_P29 (_U_(0x1) << GPIO_PVR_P29_Pos) 2760 #define GPIO_PVR_P30_Pos 30 /**< \brief (GPIO_PVR) Pin Value */ 2761 #define GPIO_PVR_P30 (_U_(0x1) << GPIO_PVR_P30_Pos) 2762 #define GPIO_PVR_P31_Pos 31 /**< \brief (GPIO_PVR) Pin Value */ 2763 #define GPIO_PVR_P31 (_U_(0x1) << GPIO_PVR_P31_Pos) 2764 #define GPIO_PVR_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PVR) MASK Register */ 2765 2766 /* -------- GPIO_PUER : (GPIO Offset: 0x070) (R/W 32) port Pull-up Enable Register -------- */ 2767 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2768 typedef union { 2769 struct { 2770 uint32_t P0:1; /*!< bit: 0 Pull-up Enable */ 2771 uint32_t P1:1; /*!< bit: 1 Pull-up Enable */ 2772 uint32_t P2:1; /*!< bit: 2 Pull-up Enable */ 2773 uint32_t P3:1; /*!< bit: 3 Pull-up Enable */ 2774 uint32_t P4:1; /*!< bit: 4 Pull-up Enable */ 2775 uint32_t P5:1; /*!< bit: 5 Pull-up Enable */ 2776 uint32_t P6:1; /*!< bit: 6 Pull-up Enable */ 2777 uint32_t P7:1; /*!< bit: 7 Pull-up Enable */ 2778 uint32_t P8:1; /*!< bit: 8 Pull-up Enable */ 2779 uint32_t P9:1; /*!< bit: 9 Pull-up Enable */ 2780 uint32_t P10:1; /*!< bit: 10 Pull-up Enable */ 2781 uint32_t P11:1; /*!< bit: 11 Pull-up Enable */ 2782 uint32_t P12:1; /*!< bit: 12 Pull-up Enable */ 2783 uint32_t P13:1; /*!< bit: 13 Pull-up Enable */ 2784 uint32_t P14:1; /*!< bit: 14 Pull-up Enable */ 2785 uint32_t P15:1; /*!< bit: 15 Pull-up Enable */ 2786 uint32_t P16:1; /*!< bit: 16 Pull-up Enable */ 2787 uint32_t P17:1; /*!< bit: 17 Pull-up Enable */ 2788 uint32_t P18:1; /*!< bit: 18 Pull-up Enable */ 2789 uint32_t P19:1; /*!< bit: 19 Pull-up Enable */ 2790 uint32_t P20:1; /*!< bit: 20 Pull-up Enable */ 2791 uint32_t P21:1; /*!< bit: 21 Pull-up Enable */ 2792 uint32_t P22:1; /*!< bit: 22 Pull-up Enable */ 2793 uint32_t P23:1; /*!< bit: 23 Pull-up Enable */ 2794 uint32_t P24:1; /*!< bit: 24 Pull-up Enable */ 2795 uint32_t P25:1; /*!< bit: 25 Pull-up Enable */ 2796 uint32_t P26:1; /*!< bit: 26 Pull-up Enable */ 2797 uint32_t P27:1; /*!< bit: 27 Pull-up Enable */ 2798 uint32_t P28:1; /*!< bit: 28 Pull-up Enable */ 2799 uint32_t P29:1; /*!< bit: 29 Pull-up Enable */ 2800 uint32_t P30:1; /*!< bit: 30 Pull-up Enable */ 2801 uint32_t P31:1; /*!< bit: 31 Pull-up Enable */ 2802 } bit; /*!< Structure used for bit access */ 2803 uint32_t reg; /*!< Type used for register access */ 2804 } GPIO_PUER_Type; 2805 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2806 2807 #define GPIO_PUER_OFFSET 0x070 /**< \brief (GPIO_PUER offset) Pull-up Enable Register */ 2808 2809 #define GPIO_PUER_P0_Pos 0 /**< \brief (GPIO_PUER) Pull-up Enable */ 2810 #define GPIO_PUER_P0 (_U_(0x1) << GPIO_PUER_P0_Pos) 2811 #define GPIO_PUER_P1_Pos 1 /**< \brief (GPIO_PUER) Pull-up Enable */ 2812 #define GPIO_PUER_P1 (_U_(0x1) << GPIO_PUER_P1_Pos) 2813 #define GPIO_PUER_P2_Pos 2 /**< \brief (GPIO_PUER) Pull-up Enable */ 2814 #define GPIO_PUER_P2 (_U_(0x1) << GPIO_PUER_P2_Pos) 2815 #define GPIO_PUER_P3_Pos 3 /**< \brief (GPIO_PUER) Pull-up Enable */ 2816 #define GPIO_PUER_P3 (_U_(0x1) << GPIO_PUER_P3_Pos) 2817 #define GPIO_PUER_P4_Pos 4 /**< \brief (GPIO_PUER) Pull-up Enable */ 2818 #define GPIO_PUER_P4 (_U_(0x1) << GPIO_PUER_P4_Pos) 2819 #define GPIO_PUER_P5_Pos 5 /**< \brief (GPIO_PUER) Pull-up Enable */ 2820 #define GPIO_PUER_P5 (_U_(0x1) << GPIO_PUER_P5_Pos) 2821 #define GPIO_PUER_P6_Pos 6 /**< \brief (GPIO_PUER) Pull-up Enable */ 2822 #define GPIO_PUER_P6 (_U_(0x1) << GPIO_PUER_P6_Pos) 2823 #define GPIO_PUER_P7_Pos 7 /**< \brief (GPIO_PUER) Pull-up Enable */ 2824 #define GPIO_PUER_P7 (_U_(0x1) << GPIO_PUER_P7_Pos) 2825 #define GPIO_PUER_P8_Pos 8 /**< \brief (GPIO_PUER) Pull-up Enable */ 2826 #define GPIO_PUER_P8 (_U_(0x1) << GPIO_PUER_P8_Pos) 2827 #define GPIO_PUER_P9_Pos 9 /**< \brief (GPIO_PUER) Pull-up Enable */ 2828 #define GPIO_PUER_P9 (_U_(0x1) << GPIO_PUER_P9_Pos) 2829 #define GPIO_PUER_P10_Pos 10 /**< \brief (GPIO_PUER) Pull-up Enable */ 2830 #define GPIO_PUER_P10 (_U_(0x1) << GPIO_PUER_P10_Pos) 2831 #define GPIO_PUER_P11_Pos 11 /**< \brief (GPIO_PUER) Pull-up Enable */ 2832 #define GPIO_PUER_P11 (_U_(0x1) << GPIO_PUER_P11_Pos) 2833 #define GPIO_PUER_P12_Pos 12 /**< \brief (GPIO_PUER) Pull-up Enable */ 2834 #define GPIO_PUER_P12 (_U_(0x1) << GPIO_PUER_P12_Pos) 2835 #define GPIO_PUER_P13_Pos 13 /**< \brief (GPIO_PUER) Pull-up Enable */ 2836 #define GPIO_PUER_P13 (_U_(0x1) << GPIO_PUER_P13_Pos) 2837 #define GPIO_PUER_P14_Pos 14 /**< \brief (GPIO_PUER) Pull-up Enable */ 2838 #define GPIO_PUER_P14 (_U_(0x1) << GPIO_PUER_P14_Pos) 2839 #define GPIO_PUER_P15_Pos 15 /**< \brief (GPIO_PUER) Pull-up Enable */ 2840 #define GPIO_PUER_P15 (_U_(0x1) << GPIO_PUER_P15_Pos) 2841 #define GPIO_PUER_P16_Pos 16 /**< \brief (GPIO_PUER) Pull-up Enable */ 2842 #define GPIO_PUER_P16 (_U_(0x1) << GPIO_PUER_P16_Pos) 2843 #define GPIO_PUER_P17_Pos 17 /**< \brief (GPIO_PUER) Pull-up Enable */ 2844 #define GPIO_PUER_P17 (_U_(0x1) << GPIO_PUER_P17_Pos) 2845 #define GPIO_PUER_P18_Pos 18 /**< \brief (GPIO_PUER) Pull-up Enable */ 2846 #define GPIO_PUER_P18 (_U_(0x1) << GPIO_PUER_P18_Pos) 2847 #define GPIO_PUER_P19_Pos 19 /**< \brief (GPIO_PUER) Pull-up Enable */ 2848 #define GPIO_PUER_P19 (_U_(0x1) << GPIO_PUER_P19_Pos) 2849 #define GPIO_PUER_P20_Pos 20 /**< \brief (GPIO_PUER) Pull-up Enable */ 2850 #define GPIO_PUER_P20 (_U_(0x1) << GPIO_PUER_P20_Pos) 2851 #define GPIO_PUER_P21_Pos 21 /**< \brief (GPIO_PUER) Pull-up Enable */ 2852 #define GPIO_PUER_P21 (_U_(0x1) << GPIO_PUER_P21_Pos) 2853 #define GPIO_PUER_P22_Pos 22 /**< \brief (GPIO_PUER) Pull-up Enable */ 2854 #define GPIO_PUER_P22 (_U_(0x1) << GPIO_PUER_P22_Pos) 2855 #define GPIO_PUER_P23_Pos 23 /**< \brief (GPIO_PUER) Pull-up Enable */ 2856 #define GPIO_PUER_P23 (_U_(0x1) << GPIO_PUER_P23_Pos) 2857 #define GPIO_PUER_P24_Pos 24 /**< \brief (GPIO_PUER) Pull-up Enable */ 2858 #define GPIO_PUER_P24 (_U_(0x1) << GPIO_PUER_P24_Pos) 2859 #define GPIO_PUER_P25_Pos 25 /**< \brief (GPIO_PUER) Pull-up Enable */ 2860 #define GPIO_PUER_P25 (_U_(0x1) << GPIO_PUER_P25_Pos) 2861 #define GPIO_PUER_P26_Pos 26 /**< \brief (GPIO_PUER) Pull-up Enable */ 2862 #define GPIO_PUER_P26 (_U_(0x1) << GPIO_PUER_P26_Pos) 2863 #define GPIO_PUER_P27_Pos 27 /**< \brief (GPIO_PUER) Pull-up Enable */ 2864 #define GPIO_PUER_P27 (_U_(0x1) << GPIO_PUER_P27_Pos) 2865 #define GPIO_PUER_P28_Pos 28 /**< \brief (GPIO_PUER) Pull-up Enable */ 2866 #define GPIO_PUER_P28 (_U_(0x1) << GPIO_PUER_P28_Pos) 2867 #define GPIO_PUER_P29_Pos 29 /**< \brief (GPIO_PUER) Pull-up Enable */ 2868 #define GPIO_PUER_P29 (_U_(0x1) << GPIO_PUER_P29_Pos) 2869 #define GPIO_PUER_P30_Pos 30 /**< \brief (GPIO_PUER) Pull-up Enable */ 2870 #define GPIO_PUER_P30 (_U_(0x1) << GPIO_PUER_P30_Pos) 2871 #define GPIO_PUER_P31_Pos 31 /**< \brief (GPIO_PUER) Pull-up Enable */ 2872 #define GPIO_PUER_P31 (_U_(0x1) << GPIO_PUER_P31_Pos) 2873 #define GPIO_PUER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PUER) MASK Register */ 2874 2875 /* -------- GPIO_PUERS : (GPIO Offset: 0x074) ( /W 32) port Pull-up Enable Register - Set -------- */ 2876 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2877 typedef union { 2878 struct { 2879 uint32_t P0:1; /*!< bit: 0 Pull-up Enable */ 2880 uint32_t P1:1; /*!< bit: 1 Pull-up Enable */ 2881 uint32_t P2:1; /*!< bit: 2 Pull-up Enable */ 2882 uint32_t P3:1; /*!< bit: 3 Pull-up Enable */ 2883 uint32_t P4:1; /*!< bit: 4 Pull-up Enable */ 2884 uint32_t P5:1; /*!< bit: 5 Pull-up Enable */ 2885 uint32_t P6:1; /*!< bit: 6 Pull-up Enable */ 2886 uint32_t P7:1; /*!< bit: 7 Pull-up Enable */ 2887 uint32_t P8:1; /*!< bit: 8 Pull-up Enable */ 2888 uint32_t P9:1; /*!< bit: 9 Pull-up Enable */ 2889 uint32_t P10:1; /*!< bit: 10 Pull-up Enable */ 2890 uint32_t P11:1; /*!< bit: 11 Pull-up Enable */ 2891 uint32_t P12:1; /*!< bit: 12 Pull-up Enable */ 2892 uint32_t P13:1; /*!< bit: 13 Pull-up Enable */ 2893 uint32_t P14:1; /*!< bit: 14 Pull-up Enable */ 2894 uint32_t P15:1; /*!< bit: 15 Pull-up Enable */ 2895 uint32_t P16:1; /*!< bit: 16 Pull-up Enable */ 2896 uint32_t P17:1; /*!< bit: 17 Pull-up Enable */ 2897 uint32_t P18:1; /*!< bit: 18 Pull-up Enable */ 2898 uint32_t P19:1; /*!< bit: 19 Pull-up Enable */ 2899 uint32_t P20:1; /*!< bit: 20 Pull-up Enable */ 2900 uint32_t P21:1; /*!< bit: 21 Pull-up Enable */ 2901 uint32_t P22:1; /*!< bit: 22 Pull-up Enable */ 2902 uint32_t P23:1; /*!< bit: 23 Pull-up Enable */ 2903 uint32_t P24:1; /*!< bit: 24 Pull-up Enable */ 2904 uint32_t P25:1; /*!< bit: 25 Pull-up Enable */ 2905 uint32_t P26:1; /*!< bit: 26 Pull-up Enable */ 2906 uint32_t P27:1; /*!< bit: 27 Pull-up Enable */ 2907 uint32_t P28:1; /*!< bit: 28 Pull-up Enable */ 2908 uint32_t P29:1; /*!< bit: 29 Pull-up Enable */ 2909 uint32_t P30:1; /*!< bit: 30 Pull-up Enable */ 2910 uint32_t P31:1; /*!< bit: 31 Pull-up Enable */ 2911 } bit; /*!< Structure used for bit access */ 2912 uint32_t reg; /*!< Type used for register access */ 2913 } GPIO_PUERS_Type; 2914 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2915 2916 #define GPIO_PUERS_OFFSET 0x074 /**< \brief (GPIO_PUERS offset) Pull-up Enable Register - Set */ 2917 2918 #define GPIO_PUERS_P0_Pos 0 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2919 #define GPIO_PUERS_P0 (_U_(0x1) << GPIO_PUERS_P0_Pos) 2920 #define GPIO_PUERS_P1_Pos 1 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2921 #define GPIO_PUERS_P1 (_U_(0x1) << GPIO_PUERS_P1_Pos) 2922 #define GPIO_PUERS_P2_Pos 2 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2923 #define GPIO_PUERS_P2 (_U_(0x1) << GPIO_PUERS_P2_Pos) 2924 #define GPIO_PUERS_P3_Pos 3 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2925 #define GPIO_PUERS_P3 (_U_(0x1) << GPIO_PUERS_P3_Pos) 2926 #define GPIO_PUERS_P4_Pos 4 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2927 #define GPIO_PUERS_P4 (_U_(0x1) << GPIO_PUERS_P4_Pos) 2928 #define GPIO_PUERS_P5_Pos 5 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2929 #define GPIO_PUERS_P5 (_U_(0x1) << GPIO_PUERS_P5_Pos) 2930 #define GPIO_PUERS_P6_Pos 6 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2931 #define GPIO_PUERS_P6 (_U_(0x1) << GPIO_PUERS_P6_Pos) 2932 #define GPIO_PUERS_P7_Pos 7 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2933 #define GPIO_PUERS_P7 (_U_(0x1) << GPIO_PUERS_P7_Pos) 2934 #define GPIO_PUERS_P8_Pos 8 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2935 #define GPIO_PUERS_P8 (_U_(0x1) << GPIO_PUERS_P8_Pos) 2936 #define GPIO_PUERS_P9_Pos 9 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2937 #define GPIO_PUERS_P9 (_U_(0x1) << GPIO_PUERS_P9_Pos) 2938 #define GPIO_PUERS_P10_Pos 10 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2939 #define GPIO_PUERS_P10 (_U_(0x1) << GPIO_PUERS_P10_Pos) 2940 #define GPIO_PUERS_P11_Pos 11 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2941 #define GPIO_PUERS_P11 (_U_(0x1) << GPIO_PUERS_P11_Pos) 2942 #define GPIO_PUERS_P12_Pos 12 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2943 #define GPIO_PUERS_P12 (_U_(0x1) << GPIO_PUERS_P12_Pos) 2944 #define GPIO_PUERS_P13_Pos 13 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2945 #define GPIO_PUERS_P13 (_U_(0x1) << GPIO_PUERS_P13_Pos) 2946 #define GPIO_PUERS_P14_Pos 14 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2947 #define GPIO_PUERS_P14 (_U_(0x1) << GPIO_PUERS_P14_Pos) 2948 #define GPIO_PUERS_P15_Pos 15 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2949 #define GPIO_PUERS_P15 (_U_(0x1) << GPIO_PUERS_P15_Pos) 2950 #define GPIO_PUERS_P16_Pos 16 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2951 #define GPIO_PUERS_P16 (_U_(0x1) << GPIO_PUERS_P16_Pos) 2952 #define GPIO_PUERS_P17_Pos 17 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2953 #define GPIO_PUERS_P17 (_U_(0x1) << GPIO_PUERS_P17_Pos) 2954 #define GPIO_PUERS_P18_Pos 18 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2955 #define GPIO_PUERS_P18 (_U_(0x1) << GPIO_PUERS_P18_Pos) 2956 #define GPIO_PUERS_P19_Pos 19 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2957 #define GPIO_PUERS_P19 (_U_(0x1) << GPIO_PUERS_P19_Pos) 2958 #define GPIO_PUERS_P20_Pos 20 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2959 #define GPIO_PUERS_P20 (_U_(0x1) << GPIO_PUERS_P20_Pos) 2960 #define GPIO_PUERS_P21_Pos 21 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2961 #define GPIO_PUERS_P21 (_U_(0x1) << GPIO_PUERS_P21_Pos) 2962 #define GPIO_PUERS_P22_Pos 22 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2963 #define GPIO_PUERS_P22 (_U_(0x1) << GPIO_PUERS_P22_Pos) 2964 #define GPIO_PUERS_P23_Pos 23 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2965 #define GPIO_PUERS_P23 (_U_(0x1) << GPIO_PUERS_P23_Pos) 2966 #define GPIO_PUERS_P24_Pos 24 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2967 #define GPIO_PUERS_P24 (_U_(0x1) << GPIO_PUERS_P24_Pos) 2968 #define GPIO_PUERS_P25_Pos 25 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2969 #define GPIO_PUERS_P25 (_U_(0x1) << GPIO_PUERS_P25_Pos) 2970 #define GPIO_PUERS_P26_Pos 26 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2971 #define GPIO_PUERS_P26 (_U_(0x1) << GPIO_PUERS_P26_Pos) 2972 #define GPIO_PUERS_P27_Pos 27 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2973 #define GPIO_PUERS_P27 (_U_(0x1) << GPIO_PUERS_P27_Pos) 2974 #define GPIO_PUERS_P28_Pos 28 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2975 #define GPIO_PUERS_P28 (_U_(0x1) << GPIO_PUERS_P28_Pos) 2976 #define GPIO_PUERS_P29_Pos 29 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2977 #define GPIO_PUERS_P29 (_U_(0x1) << GPIO_PUERS_P29_Pos) 2978 #define GPIO_PUERS_P30_Pos 30 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2979 #define GPIO_PUERS_P30 (_U_(0x1) << GPIO_PUERS_P30_Pos) 2980 #define GPIO_PUERS_P31_Pos 31 /**< \brief (GPIO_PUERS) Pull-up Enable */ 2981 #define GPIO_PUERS_P31 (_U_(0x1) << GPIO_PUERS_P31_Pos) 2982 #define GPIO_PUERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PUERS) MASK Register */ 2983 2984 /* -------- GPIO_PUERC : (GPIO Offset: 0x078) ( /W 32) port Pull-up Enable Register - Clear -------- */ 2985 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2986 typedef union { 2987 struct { 2988 uint32_t P0:1; /*!< bit: 0 Pull-up Enable */ 2989 uint32_t P1:1; /*!< bit: 1 Pull-up Enable */ 2990 uint32_t P2:1; /*!< bit: 2 Pull-up Enable */ 2991 uint32_t P3:1; /*!< bit: 3 Pull-up Enable */ 2992 uint32_t P4:1; /*!< bit: 4 Pull-up Enable */ 2993 uint32_t P5:1; /*!< bit: 5 Pull-up Enable */ 2994 uint32_t P6:1; /*!< bit: 6 Pull-up Enable */ 2995 uint32_t P7:1; /*!< bit: 7 Pull-up Enable */ 2996 uint32_t P8:1; /*!< bit: 8 Pull-up Enable */ 2997 uint32_t P9:1; /*!< bit: 9 Pull-up Enable */ 2998 uint32_t P10:1; /*!< bit: 10 Pull-up Enable */ 2999 uint32_t P11:1; /*!< bit: 11 Pull-up Enable */ 3000 uint32_t P12:1; /*!< bit: 12 Pull-up Enable */ 3001 uint32_t P13:1; /*!< bit: 13 Pull-up Enable */ 3002 uint32_t P14:1; /*!< bit: 14 Pull-up Enable */ 3003 uint32_t P15:1; /*!< bit: 15 Pull-up Enable */ 3004 uint32_t P16:1; /*!< bit: 16 Pull-up Enable */ 3005 uint32_t P17:1; /*!< bit: 17 Pull-up Enable */ 3006 uint32_t P18:1; /*!< bit: 18 Pull-up Enable */ 3007 uint32_t P19:1; /*!< bit: 19 Pull-up Enable */ 3008 uint32_t P20:1; /*!< bit: 20 Pull-up Enable */ 3009 uint32_t P21:1; /*!< bit: 21 Pull-up Enable */ 3010 uint32_t P22:1; /*!< bit: 22 Pull-up Enable */ 3011 uint32_t P23:1; /*!< bit: 23 Pull-up Enable */ 3012 uint32_t P24:1; /*!< bit: 24 Pull-up Enable */ 3013 uint32_t P25:1; /*!< bit: 25 Pull-up Enable */ 3014 uint32_t P26:1; /*!< bit: 26 Pull-up Enable */ 3015 uint32_t P27:1; /*!< bit: 27 Pull-up Enable */ 3016 uint32_t P28:1; /*!< bit: 28 Pull-up Enable */ 3017 uint32_t P29:1; /*!< bit: 29 Pull-up Enable */ 3018 uint32_t P30:1; /*!< bit: 30 Pull-up Enable */ 3019 uint32_t P31:1; /*!< bit: 31 Pull-up Enable */ 3020 } bit; /*!< Structure used for bit access */ 3021 uint32_t reg; /*!< Type used for register access */ 3022 } GPIO_PUERC_Type; 3023 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3024 3025 #define GPIO_PUERC_OFFSET 0x078 /**< \brief (GPIO_PUERC offset) Pull-up Enable Register - Clear */ 3026 3027 #define GPIO_PUERC_P0_Pos 0 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3028 #define GPIO_PUERC_P0 (_U_(0x1) << GPIO_PUERC_P0_Pos) 3029 #define GPIO_PUERC_P1_Pos 1 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3030 #define GPIO_PUERC_P1 (_U_(0x1) << GPIO_PUERC_P1_Pos) 3031 #define GPIO_PUERC_P2_Pos 2 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3032 #define GPIO_PUERC_P2 (_U_(0x1) << GPIO_PUERC_P2_Pos) 3033 #define GPIO_PUERC_P3_Pos 3 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3034 #define GPIO_PUERC_P3 (_U_(0x1) << GPIO_PUERC_P3_Pos) 3035 #define GPIO_PUERC_P4_Pos 4 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3036 #define GPIO_PUERC_P4 (_U_(0x1) << GPIO_PUERC_P4_Pos) 3037 #define GPIO_PUERC_P5_Pos 5 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3038 #define GPIO_PUERC_P5 (_U_(0x1) << GPIO_PUERC_P5_Pos) 3039 #define GPIO_PUERC_P6_Pos 6 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3040 #define GPIO_PUERC_P6 (_U_(0x1) << GPIO_PUERC_P6_Pos) 3041 #define GPIO_PUERC_P7_Pos 7 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3042 #define GPIO_PUERC_P7 (_U_(0x1) << GPIO_PUERC_P7_Pos) 3043 #define GPIO_PUERC_P8_Pos 8 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3044 #define GPIO_PUERC_P8 (_U_(0x1) << GPIO_PUERC_P8_Pos) 3045 #define GPIO_PUERC_P9_Pos 9 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3046 #define GPIO_PUERC_P9 (_U_(0x1) << GPIO_PUERC_P9_Pos) 3047 #define GPIO_PUERC_P10_Pos 10 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3048 #define GPIO_PUERC_P10 (_U_(0x1) << GPIO_PUERC_P10_Pos) 3049 #define GPIO_PUERC_P11_Pos 11 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3050 #define GPIO_PUERC_P11 (_U_(0x1) << GPIO_PUERC_P11_Pos) 3051 #define GPIO_PUERC_P12_Pos 12 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3052 #define GPIO_PUERC_P12 (_U_(0x1) << GPIO_PUERC_P12_Pos) 3053 #define GPIO_PUERC_P13_Pos 13 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3054 #define GPIO_PUERC_P13 (_U_(0x1) << GPIO_PUERC_P13_Pos) 3055 #define GPIO_PUERC_P14_Pos 14 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3056 #define GPIO_PUERC_P14 (_U_(0x1) << GPIO_PUERC_P14_Pos) 3057 #define GPIO_PUERC_P15_Pos 15 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3058 #define GPIO_PUERC_P15 (_U_(0x1) << GPIO_PUERC_P15_Pos) 3059 #define GPIO_PUERC_P16_Pos 16 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3060 #define GPIO_PUERC_P16 (_U_(0x1) << GPIO_PUERC_P16_Pos) 3061 #define GPIO_PUERC_P17_Pos 17 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3062 #define GPIO_PUERC_P17 (_U_(0x1) << GPIO_PUERC_P17_Pos) 3063 #define GPIO_PUERC_P18_Pos 18 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3064 #define GPIO_PUERC_P18 (_U_(0x1) << GPIO_PUERC_P18_Pos) 3065 #define GPIO_PUERC_P19_Pos 19 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3066 #define GPIO_PUERC_P19 (_U_(0x1) << GPIO_PUERC_P19_Pos) 3067 #define GPIO_PUERC_P20_Pos 20 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3068 #define GPIO_PUERC_P20 (_U_(0x1) << GPIO_PUERC_P20_Pos) 3069 #define GPIO_PUERC_P21_Pos 21 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3070 #define GPIO_PUERC_P21 (_U_(0x1) << GPIO_PUERC_P21_Pos) 3071 #define GPIO_PUERC_P22_Pos 22 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3072 #define GPIO_PUERC_P22 (_U_(0x1) << GPIO_PUERC_P22_Pos) 3073 #define GPIO_PUERC_P23_Pos 23 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3074 #define GPIO_PUERC_P23 (_U_(0x1) << GPIO_PUERC_P23_Pos) 3075 #define GPIO_PUERC_P24_Pos 24 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3076 #define GPIO_PUERC_P24 (_U_(0x1) << GPIO_PUERC_P24_Pos) 3077 #define GPIO_PUERC_P25_Pos 25 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3078 #define GPIO_PUERC_P25 (_U_(0x1) << GPIO_PUERC_P25_Pos) 3079 #define GPIO_PUERC_P26_Pos 26 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3080 #define GPIO_PUERC_P26 (_U_(0x1) << GPIO_PUERC_P26_Pos) 3081 #define GPIO_PUERC_P27_Pos 27 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3082 #define GPIO_PUERC_P27 (_U_(0x1) << GPIO_PUERC_P27_Pos) 3083 #define GPIO_PUERC_P28_Pos 28 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3084 #define GPIO_PUERC_P28 (_U_(0x1) << GPIO_PUERC_P28_Pos) 3085 #define GPIO_PUERC_P29_Pos 29 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3086 #define GPIO_PUERC_P29 (_U_(0x1) << GPIO_PUERC_P29_Pos) 3087 #define GPIO_PUERC_P30_Pos 30 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3088 #define GPIO_PUERC_P30 (_U_(0x1) << GPIO_PUERC_P30_Pos) 3089 #define GPIO_PUERC_P31_Pos 31 /**< \brief (GPIO_PUERC) Pull-up Enable */ 3090 #define GPIO_PUERC_P31 (_U_(0x1) << GPIO_PUERC_P31_Pos) 3091 #define GPIO_PUERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PUERC) MASK Register */ 3092 3093 /* -------- GPIO_PUERT : (GPIO Offset: 0x07C) ( /W 32) port Pull-up Enable Register - Toggle -------- */ 3094 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3095 typedef union { 3096 struct { 3097 uint32_t P0:1; /*!< bit: 0 Pull-up Enable */ 3098 uint32_t P1:1; /*!< bit: 1 Pull-up Enable */ 3099 uint32_t P2:1; /*!< bit: 2 Pull-up Enable */ 3100 uint32_t P3:1; /*!< bit: 3 Pull-up Enable */ 3101 uint32_t P4:1; /*!< bit: 4 Pull-up Enable */ 3102 uint32_t P5:1; /*!< bit: 5 Pull-up Enable */ 3103 uint32_t P6:1; /*!< bit: 6 Pull-up Enable */ 3104 uint32_t P7:1; /*!< bit: 7 Pull-up Enable */ 3105 uint32_t P8:1; /*!< bit: 8 Pull-up Enable */ 3106 uint32_t P9:1; /*!< bit: 9 Pull-up Enable */ 3107 uint32_t P10:1; /*!< bit: 10 Pull-up Enable */ 3108 uint32_t P11:1; /*!< bit: 11 Pull-up Enable */ 3109 uint32_t P12:1; /*!< bit: 12 Pull-up Enable */ 3110 uint32_t P13:1; /*!< bit: 13 Pull-up Enable */ 3111 uint32_t P14:1; /*!< bit: 14 Pull-up Enable */ 3112 uint32_t P15:1; /*!< bit: 15 Pull-up Enable */ 3113 uint32_t P16:1; /*!< bit: 16 Pull-up Enable */ 3114 uint32_t P17:1; /*!< bit: 17 Pull-up Enable */ 3115 uint32_t P18:1; /*!< bit: 18 Pull-up Enable */ 3116 uint32_t P19:1; /*!< bit: 19 Pull-up Enable */ 3117 uint32_t P20:1; /*!< bit: 20 Pull-up Enable */ 3118 uint32_t P21:1; /*!< bit: 21 Pull-up Enable */ 3119 uint32_t P22:1; /*!< bit: 22 Pull-up Enable */ 3120 uint32_t P23:1; /*!< bit: 23 Pull-up Enable */ 3121 uint32_t P24:1; /*!< bit: 24 Pull-up Enable */ 3122 uint32_t P25:1; /*!< bit: 25 Pull-up Enable */ 3123 uint32_t P26:1; /*!< bit: 26 Pull-up Enable */ 3124 uint32_t P27:1; /*!< bit: 27 Pull-up Enable */ 3125 uint32_t P28:1; /*!< bit: 28 Pull-up Enable */ 3126 uint32_t P29:1; /*!< bit: 29 Pull-up Enable */ 3127 uint32_t P30:1; /*!< bit: 30 Pull-up Enable */ 3128 uint32_t P31:1; /*!< bit: 31 Pull-up Enable */ 3129 } bit; /*!< Structure used for bit access */ 3130 uint32_t reg; /*!< Type used for register access */ 3131 } GPIO_PUERT_Type; 3132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3133 3134 #define GPIO_PUERT_OFFSET 0x07C /**< \brief (GPIO_PUERT offset) Pull-up Enable Register - Toggle */ 3135 3136 #define GPIO_PUERT_P0_Pos 0 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3137 #define GPIO_PUERT_P0 (_U_(0x1) << GPIO_PUERT_P0_Pos) 3138 #define GPIO_PUERT_P1_Pos 1 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3139 #define GPIO_PUERT_P1 (_U_(0x1) << GPIO_PUERT_P1_Pos) 3140 #define GPIO_PUERT_P2_Pos 2 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3141 #define GPIO_PUERT_P2 (_U_(0x1) << GPIO_PUERT_P2_Pos) 3142 #define GPIO_PUERT_P3_Pos 3 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3143 #define GPIO_PUERT_P3 (_U_(0x1) << GPIO_PUERT_P3_Pos) 3144 #define GPIO_PUERT_P4_Pos 4 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3145 #define GPIO_PUERT_P4 (_U_(0x1) << GPIO_PUERT_P4_Pos) 3146 #define GPIO_PUERT_P5_Pos 5 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3147 #define GPIO_PUERT_P5 (_U_(0x1) << GPIO_PUERT_P5_Pos) 3148 #define GPIO_PUERT_P6_Pos 6 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3149 #define GPIO_PUERT_P6 (_U_(0x1) << GPIO_PUERT_P6_Pos) 3150 #define GPIO_PUERT_P7_Pos 7 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3151 #define GPIO_PUERT_P7 (_U_(0x1) << GPIO_PUERT_P7_Pos) 3152 #define GPIO_PUERT_P8_Pos 8 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3153 #define GPIO_PUERT_P8 (_U_(0x1) << GPIO_PUERT_P8_Pos) 3154 #define GPIO_PUERT_P9_Pos 9 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3155 #define GPIO_PUERT_P9 (_U_(0x1) << GPIO_PUERT_P9_Pos) 3156 #define GPIO_PUERT_P10_Pos 10 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3157 #define GPIO_PUERT_P10 (_U_(0x1) << GPIO_PUERT_P10_Pos) 3158 #define GPIO_PUERT_P11_Pos 11 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3159 #define GPIO_PUERT_P11 (_U_(0x1) << GPIO_PUERT_P11_Pos) 3160 #define GPIO_PUERT_P12_Pos 12 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3161 #define GPIO_PUERT_P12 (_U_(0x1) << GPIO_PUERT_P12_Pos) 3162 #define GPIO_PUERT_P13_Pos 13 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3163 #define GPIO_PUERT_P13 (_U_(0x1) << GPIO_PUERT_P13_Pos) 3164 #define GPIO_PUERT_P14_Pos 14 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3165 #define GPIO_PUERT_P14 (_U_(0x1) << GPIO_PUERT_P14_Pos) 3166 #define GPIO_PUERT_P15_Pos 15 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3167 #define GPIO_PUERT_P15 (_U_(0x1) << GPIO_PUERT_P15_Pos) 3168 #define GPIO_PUERT_P16_Pos 16 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3169 #define GPIO_PUERT_P16 (_U_(0x1) << GPIO_PUERT_P16_Pos) 3170 #define GPIO_PUERT_P17_Pos 17 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3171 #define GPIO_PUERT_P17 (_U_(0x1) << GPIO_PUERT_P17_Pos) 3172 #define GPIO_PUERT_P18_Pos 18 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3173 #define GPIO_PUERT_P18 (_U_(0x1) << GPIO_PUERT_P18_Pos) 3174 #define GPIO_PUERT_P19_Pos 19 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3175 #define GPIO_PUERT_P19 (_U_(0x1) << GPIO_PUERT_P19_Pos) 3176 #define GPIO_PUERT_P20_Pos 20 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3177 #define GPIO_PUERT_P20 (_U_(0x1) << GPIO_PUERT_P20_Pos) 3178 #define GPIO_PUERT_P21_Pos 21 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3179 #define GPIO_PUERT_P21 (_U_(0x1) << GPIO_PUERT_P21_Pos) 3180 #define GPIO_PUERT_P22_Pos 22 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3181 #define GPIO_PUERT_P22 (_U_(0x1) << GPIO_PUERT_P22_Pos) 3182 #define GPIO_PUERT_P23_Pos 23 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3183 #define GPIO_PUERT_P23 (_U_(0x1) << GPIO_PUERT_P23_Pos) 3184 #define GPIO_PUERT_P24_Pos 24 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3185 #define GPIO_PUERT_P24 (_U_(0x1) << GPIO_PUERT_P24_Pos) 3186 #define GPIO_PUERT_P25_Pos 25 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3187 #define GPIO_PUERT_P25 (_U_(0x1) << GPIO_PUERT_P25_Pos) 3188 #define GPIO_PUERT_P26_Pos 26 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3189 #define GPIO_PUERT_P26 (_U_(0x1) << GPIO_PUERT_P26_Pos) 3190 #define GPIO_PUERT_P27_Pos 27 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3191 #define GPIO_PUERT_P27 (_U_(0x1) << GPIO_PUERT_P27_Pos) 3192 #define GPIO_PUERT_P28_Pos 28 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3193 #define GPIO_PUERT_P28 (_U_(0x1) << GPIO_PUERT_P28_Pos) 3194 #define GPIO_PUERT_P29_Pos 29 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3195 #define GPIO_PUERT_P29 (_U_(0x1) << GPIO_PUERT_P29_Pos) 3196 #define GPIO_PUERT_P30_Pos 30 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3197 #define GPIO_PUERT_P30 (_U_(0x1) << GPIO_PUERT_P30_Pos) 3198 #define GPIO_PUERT_P31_Pos 31 /**< \brief (GPIO_PUERT) Pull-up Enable */ 3199 #define GPIO_PUERT_P31 (_U_(0x1) << GPIO_PUERT_P31_Pos) 3200 #define GPIO_PUERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PUERT) MASK Register */ 3201 3202 /* -------- GPIO_PDER : (GPIO Offset: 0x080) (R/W 32) port Pull-down Enable Register -------- */ 3203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3204 typedef union { 3205 struct { 3206 uint32_t P0:1; /*!< bit: 0 Pull-down Enable */ 3207 uint32_t P1:1; /*!< bit: 1 Pull-down Enable */ 3208 uint32_t P2:1; /*!< bit: 2 Pull-down Enable */ 3209 uint32_t P3:1; /*!< bit: 3 Pull-down Enable */ 3210 uint32_t P4:1; /*!< bit: 4 Pull-down Enable */ 3211 uint32_t P5:1; /*!< bit: 5 Pull-down Enable */ 3212 uint32_t P6:1; /*!< bit: 6 Pull-down Enable */ 3213 uint32_t P7:1; /*!< bit: 7 Pull-down Enable */ 3214 uint32_t P8:1; /*!< bit: 8 Pull-down Enable */ 3215 uint32_t P9:1; /*!< bit: 9 Pull-down Enable */ 3216 uint32_t P10:1; /*!< bit: 10 Pull-down Enable */ 3217 uint32_t P11:1; /*!< bit: 11 Pull-down Enable */ 3218 uint32_t P12:1; /*!< bit: 12 Pull-down Enable */ 3219 uint32_t P13:1; /*!< bit: 13 Pull-down Enable */ 3220 uint32_t P14:1; /*!< bit: 14 Pull-down Enable */ 3221 uint32_t P15:1; /*!< bit: 15 Pull-down Enable */ 3222 uint32_t P16:1; /*!< bit: 16 Pull-down Enable */ 3223 uint32_t P17:1; /*!< bit: 17 Pull-down Enable */ 3224 uint32_t P18:1; /*!< bit: 18 Pull-down Enable */ 3225 uint32_t P19:1; /*!< bit: 19 Pull-down Enable */ 3226 uint32_t P20:1; /*!< bit: 20 Pull-down Enable */ 3227 uint32_t P21:1; /*!< bit: 21 Pull-down Enable */ 3228 uint32_t P22:1; /*!< bit: 22 Pull-down Enable */ 3229 uint32_t P23:1; /*!< bit: 23 Pull-down Enable */ 3230 uint32_t P24:1; /*!< bit: 24 Pull-down Enable */ 3231 uint32_t P25:1; /*!< bit: 25 Pull-down Enable */ 3232 uint32_t P26:1; /*!< bit: 26 Pull-down Enable */ 3233 uint32_t P27:1; /*!< bit: 27 Pull-down Enable */ 3234 uint32_t P28:1; /*!< bit: 28 Pull-down Enable */ 3235 uint32_t P29:1; /*!< bit: 29 Pull-down Enable */ 3236 uint32_t P30:1; /*!< bit: 30 Pull-down Enable */ 3237 uint32_t P31:1; /*!< bit: 31 Pull-down Enable */ 3238 } bit; /*!< Structure used for bit access */ 3239 uint32_t reg; /*!< Type used for register access */ 3240 } GPIO_PDER_Type; 3241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3242 3243 #define GPIO_PDER_OFFSET 0x080 /**< \brief (GPIO_PDER offset) Pull-down Enable Register */ 3244 3245 #define GPIO_PDER_P0_Pos 0 /**< \brief (GPIO_PDER) Pull-down Enable */ 3246 #define GPIO_PDER_P0 (_U_(0x1) << GPIO_PDER_P0_Pos) 3247 #define GPIO_PDER_P1_Pos 1 /**< \brief (GPIO_PDER) Pull-down Enable */ 3248 #define GPIO_PDER_P1 (_U_(0x1) << GPIO_PDER_P1_Pos) 3249 #define GPIO_PDER_P2_Pos 2 /**< \brief (GPIO_PDER) Pull-down Enable */ 3250 #define GPIO_PDER_P2 (_U_(0x1) << GPIO_PDER_P2_Pos) 3251 #define GPIO_PDER_P3_Pos 3 /**< \brief (GPIO_PDER) Pull-down Enable */ 3252 #define GPIO_PDER_P3 (_U_(0x1) << GPIO_PDER_P3_Pos) 3253 #define GPIO_PDER_P4_Pos 4 /**< \brief (GPIO_PDER) Pull-down Enable */ 3254 #define GPIO_PDER_P4 (_U_(0x1) << GPIO_PDER_P4_Pos) 3255 #define GPIO_PDER_P5_Pos 5 /**< \brief (GPIO_PDER) Pull-down Enable */ 3256 #define GPIO_PDER_P5 (_U_(0x1) << GPIO_PDER_P5_Pos) 3257 #define GPIO_PDER_P6_Pos 6 /**< \brief (GPIO_PDER) Pull-down Enable */ 3258 #define GPIO_PDER_P6 (_U_(0x1) << GPIO_PDER_P6_Pos) 3259 #define GPIO_PDER_P7_Pos 7 /**< \brief (GPIO_PDER) Pull-down Enable */ 3260 #define GPIO_PDER_P7 (_U_(0x1) << GPIO_PDER_P7_Pos) 3261 #define GPIO_PDER_P8_Pos 8 /**< \brief (GPIO_PDER) Pull-down Enable */ 3262 #define GPIO_PDER_P8 (_U_(0x1) << GPIO_PDER_P8_Pos) 3263 #define GPIO_PDER_P9_Pos 9 /**< \brief (GPIO_PDER) Pull-down Enable */ 3264 #define GPIO_PDER_P9 (_U_(0x1) << GPIO_PDER_P9_Pos) 3265 #define GPIO_PDER_P10_Pos 10 /**< \brief (GPIO_PDER) Pull-down Enable */ 3266 #define GPIO_PDER_P10 (_U_(0x1) << GPIO_PDER_P10_Pos) 3267 #define GPIO_PDER_P11_Pos 11 /**< \brief (GPIO_PDER) Pull-down Enable */ 3268 #define GPIO_PDER_P11 (_U_(0x1) << GPIO_PDER_P11_Pos) 3269 #define GPIO_PDER_P12_Pos 12 /**< \brief (GPIO_PDER) Pull-down Enable */ 3270 #define GPIO_PDER_P12 (_U_(0x1) << GPIO_PDER_P12_Pos) 3271 #define GPIO_PDER_P13_Pos 13 /**< \brief (GPIO_PDER) Pull-down Enable */ 3272 #define GPIO_PDER_P13 (_U_(0x1) << GPIO_PDER_P13_Pos) 3273 #define GPIO_PDER_P14_Pos 14 /**< \brief (GPIO_PDER) Pull-down Enable */ 3274 #define GPIO_PDER_P14 (_U_(0x1) << GPIO_PDER_P14_Pos) 3275 #define GPIO_PDER_P15_Pos 15 /**< \brief (GPIO_PDER) Pull-down Enable */ 3276 #define GPIO_PDER_P15 (_U_(0x1) << GPIO_PDER_P15_Pos) 3277 #define GPIO_PDER_P16_Pos 16 /**< \brief (GPIO_PDER) Pull-down Enable */ 3278 #define GPIO_PDER_P16 (_U_(0x1) << GPIO_PDER_P16_Pos) 3279 #define GPIO_PDER_P17_Pos 17 /**< \brief (GPIO_PDER) Pull-down Enable */ 3280 #define GPIO_PDER_P17 (_U_(0x1) << GPIO_PDER_P17_Pos) 3281 #define GPIO_PDER_P18_Pos 18 /**< \brief (GPIO_PDER) Pull-down Enable */ 3282 #define GPIO_PDER_P18 (_U_(0x1) << GPIO_PDER_P18_Pos) 3283 #define GPIO_PDER_P19_Pos 19 /**< \brief (GPIO_PDER) Pull-down Enable */ 3284 #define GPIO_PDER_P19 (_U_(0x1) << GPIO_PDER_P19_Pos) 3285 #define GPIO_PDER_P20_Pos 20 /**< \brief (GPIO_PDER) Pull-down Enable */ 3286 #define GPIO_PDER_P20 (_U_(0x1) << GPIO_PDER_P20_Pos) 3287 #define GPIO_PDER_P21_Pos 21 /**< \brief (GPIO_PDER) Pull-down Enable */ 3288 #define GPIO_PDER_P21 (_U_(0x1) << GPIO_PDER_P21_Pos) 3289 #define GPIO_PDER_P22_Pos 22 /**< \brief (GPIO_PDER) Pull-down Enable */ 3290 #define GPIO_PDER_P22 (_U_(0x1) << GPIO_PDER_P22_Pos) 3291 #define GPIO_PDER_P23_Pos 23 /**< \brief (GPIO_PDER) Pull-down Enable */ 3292 #define GPIO_PDER_P23 (_U_(0x1) << GPIO_PDER_P23_Pos) 3293 #define GPIO_PDER_P24_Pos 24 /**< \brief (GPIO_PDER) Pull-down Enable */ 3294 #define GPIO_PDER_P24 (_U_(0x1) << GPIO_PDER_P24_Pos) 3295 #define GPIO_PDER_P25_Pos 25 /**< \brief (GPIO_PDER) Pull-down Enable */ 3296 #define GPIO_PDER_P25 (_U_(0x1) << GPIO_PDER_P25_Pos) 3297 #define GPIO_PDER_P26_Pos 26 /**< \brief (GPIO_PDER) Pull-down Enable */ 3298 #define GPIO_PDER_P26 (_U_(0x1) << GPIO_PDER_P26_Pos) 3299 #define GPIO_PDER_P27_Pos 27 /**< \brief (GPIO_PDER) Pull-down Enable */ 3300 #define GPIO_PDER_P27 (_U_(0x1) << GPIO_PDER_P27_Pos) 3301 #define GPIO_PDER_P28_Pos 28 /**< \brief (GPIO_PDER) Pull-down Enable */ 3302 #define GPIO_PDER_P28 (_U_(0x1) << GPIO_PDER_P28_Pos) 3303 #define GPIO_PDER_P29_Pos 29 /**< \brief (GPIO_PDER) Pull-down Enable */ 3304 #define GPIO_PDER_P29 (_U_(0x1) << GPIO_PDER_P29_Pos) 3305 #define GPIO_PDER_P30_Pos 30 /**< \brief (GPIO_PDER) Pull-down Enable */ 3306 #define GPIO_PDER_P30 (_U_(0x1) << GPIO_PDER_P30_Pos) 3307 #define GPIO_PDER_P31_Pos 31 /**< \brief (GPIO_PDER) Pull-down Enable */ 3308 #define GPIO_PDER_P31 (_U_(0x1) << GPIO_PDER_P31_Pos) 3309 #define GPIO_PDER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PDER) MASK Register */ 3310 3311 /* -------- GPIO_PDERS : (GPIO Offset: 0x084) ( /W 32) port Pull-down Enable Register - Set -------- */ 3312 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3313 typedef union { 3314 struct { 3315 uint32_t P0:1; /*!< bit: 0 Pull-down Enable */ 3316 uint32_t P1:1; /*!< bit: 1 Pull-down Enable */ 3317 uint32_t P2:1; /*!< bit: 2 Pull-down Enable */ 3318 uint32_t P3:1; /*!< bit: 3 Pull-down Enable */ 3319 uint32_t P4:1; /*!< bit: 4 Pull-down Enable */ 3320 uint32_t P5:1; /*!< bit: 5 Pull-down Enable */ 3321 uint32_t P6:1; /*!< bit: 6 Pull-down Enable */ 3322 uint32_t P7:1; /*!< bit: 7 Pull-down Enable */ 3323 uint32_t P8:1; /*!< bit: 8 Pull-down Enable */ 3324 uint32_t P9:1; /*!< bit: 9 Pull-down Enable */ 3325 uint32_t P10:1; /*!< bit: 10 Pull-down Enable */ 3326 uint32_t P11:1; /*!< bit: 11 Pull-down Enable */ 3327 uint32_t P12:1; /*!< bit: 12 Pull-down Enable */ 3328 uint32_t P13:1; /*!< bit: 13 Pull-down Enable */ 3329 uint32_t P14:1; /*!< bit: 14 Pull-down Enable */ 3330 uint32_t P15:1; /*!< bit: 15 Pull-down Enable */ 3331 uint32_t P16:1; /*!< bit: 16 Pull-down Enable */ 3332 uint32_t P17:1; /*!< bit: 17 Pull-down Enable */ 3333 uint32_t P18:1; /*!< bit: 18 Pull-down Enable */ 3334 uint32_t P19:1; /*!< bit: 19 Pull-down Enable */ 3335 uint32_t P20:1; /*!< bit: 20 Pull-down Enable */ 3336 uint32_t P21:1; /*!< bit: 21 Pull-down Enable */ 3337 uint32_t P22:1; /*!< bit: 22 Pull-down Enable */ 3338 uint32_t P23:1; /*!< bit: 23 Pull-down Enable */ 3339 uint32_t P24:1; /*!< bit: 24 Pull-down Enable */ 3340 uint32_t P25:1; /*!< bit: 25 Pull-down Enable */ 3341 uint32_t P26:1; /*!< bit: 26 Pull-down Enable */ 3342 uint32_t P27:1; /*!< bit: 27 Pull-down Enable */ 3343 uint32_t P28:1; /*!< bit: 28 Pull-down Enable */ 3344 uint32_t P29:1; /*!< bit: 29 Pull-down Enable */ 3345 uint32_t P30:1; /*!< bit: 30 Pull-down Enable */ 3346 uint32_t P31:1; /*!< bit: 31 Pull-down Enable */ 3347 } bit; /*!< Structure used for bit access */ 3348 uint32_t reg; /*!< Type used for register access */ 3349 } GPIO_PDERS_Type; 3350 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3351 3352 #define GPIO_PDERS_OFFSET 0x084 /**< \brief (GPIO_PDERS offset) Pull-down Enable Register - Set */ 3353 3354 #define GPIO_PDERS_P0_Pos 0 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3355 #define GPIO_PDERS_P0 (_U_(0x1) << GPIO_PDERS_P0_Pos) 3356 #define GPIO_PDERS_P1_Pos 1 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3357 #define GPIO_PDERS_P1 (_U_(0x1) << GPIO_PDERS_P1_Pos) 3358 #define GPIO_PDERS_P2_Pos 2 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3359 #define GPIO_PDERS_P2 (_U_(0x1) << GPIO_PDERS_P2_Pos) 3360 #define GPIO_PDERS_P3_Pos 3 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3361 #define GPIO_PDERS_P3 (_U_(0x1) << GPIO_PDERS_P3_Pos) 3362 #define GPIO_PDERS_P4_Pos 4 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3363 #define GPIO_PDERS_P4 (_U_(0x1) << GPIO_PDERS_P4_Pos) 3364 #define GPIO_PDERS_P5_Pos 5 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3365 #define GPIO_PDERS_P5 (_U_(0x1) << GPIO_PDERS_P5_Pos) 3366 #define GPIO_PDERS_P6_Pos 6 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3367 #define GPIO_PDERS_P6 (_U_(0x1) << GPIO_PDERS_P6_Pos) 3368 #define GPIO_PDERS_P7_Pos 7 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3369 #define GPIO_PDERS_P7 (_U_(0x1) << GPIO_PDERS_P7_Pos) 3370 #define GPIO_PDERS_P8_Pos 8 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3371 #define GPIO_PDERS_P8 (_U_(0x1) << GPIO_PDERS_P8_Pos) 3372 #define GPIO_PDERS_P9_Pos 9 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3373 #define GPIO_PDERS_P9 (_U_(0x1) << GPIO_PDERS_P9_Pos) 3374 #define GPIO_PDERS_P10_Pos 10 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3375 #define GPIO_PDERS_P10 (_U_(0x1) << GPIO_PDERS_P10_Pos) 3376 #define GPIO_PDERS_P11_Pos 11 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3377 #define GPIO_PDERS_P11 (_U_(0x1) << GPIO_PDERS_P11_Pos) 3378 #define GPIO_PDERS_P12_Pos 12 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3379 #define GPIO_PDERS_P12 (_U_(0x1) << GPIO_PDERS_P12_Pos) 3380 #define GPIO_PDERS_P13_Pos 13 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3381 #define GPIO_PDERS_P13 (_U_(0x1) << GPIO_PDERS_P13_Pos) 3382 #define GPIO_PDERS_P14_Pos 14 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3383 #define GPIO_PDERS_P14 (_U_(0x1) << GPIO_PDERS_P14_Pos) 3384 #define GPIO_PDERS_P15_Pos 15 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3385 #define GPIO_PDERS_P15 (_U_(0x1) << GPIO_PDERS_P15_Pos) 3386 #define GPIO_PDERS_P16_Pos 16 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3387 #define GPIO_PDERS_P16 (_U_(0x1) << GPIO_PDERS_P16_Pos) 3388 #define GPIO_PDERS_P17_Pos 17 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3389 #define GPIO_PDERS_P17 (_U_(0x1) << GPIO_PDERS_P17_Pos) 3390 #define GPIO_PDERS_P18_Pos 18 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3391 #define GPIO_PDERS_P18 (_U_(0x1) << GPIO_PDERS_P18_Pos) 3392 #define GPIO_PDERS_P19_Pos 19 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3393 #define GPIO_PDERS_P19 (_U_(0x1) << GPIO_PDERS_P19_Pos) 3394 #define GPIO_PDERS_P20_Pos 20 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3395 #define GPIO_PDERS_P20 (_U_(0x1) << GPIO_PDERS_P20_Pos) 3396 #define GPIO_PDERS_P21_Pos 21 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3397 #define GPIO_PDERS_P21 (_U_(0x1) << GPIO_PDERS_P21_Pos) 3398 #define GPIO_PDERS_P22_Pos 22 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3399 #define GPIO_PDERS_P22 (_U_(0x1) << GPIO_PDERS_P22_Pos) 3400 #define GPIO_PDERS_P23_Pos 23 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3401 #define GPIO_PDERS_P23 (_U_(0x1) << GPIO_PDERS_P23_Pos) 3402 #define GPIO_PDERS_P24_Pos 24 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3403 #define GPIO_PDERS_P24 (_U_(0x1) << GPIO_PDERS_P24_Pos) 3404 #define GPIO_PDERS_P25_Pos 25 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3405 #define GPIO_PDERS_P25 (_U_(0x1) << GPIO_PDERS_P25_Pos) 3406 #define GPIO_PDERS_P26_Pos 26 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3407 #define GPIO_PDERS_P26 (_U_(0x1) << GPIO_PDERS_P26_Pos) 3408 #define GPIO_PDERS_P27_Pos 27 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3409 #define GPIO_PDERS_P27 (_U_(0x1) << GPIO_PDERS_P27_Pos) 3410 #define GPIO_PDERS_P28_Pos 28 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3411 #define GPIO_PDERS_P28 (_U_(0x1) << GPIO_PDERS_P28_Pos) 3412 #define GPIO_PDERS_P29_Pos 29 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3413 #define GPIO_PDERS_P29 (_U_(0x1) << GPIO_PDERS_P29_Pos) 3414 #define GPIO_PDERS_P30_Pos 30 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3415 #define GPIO_PDERS_P30 (_U_(0x1) << GPIO_PDERS_P30_Pos) 3416 #define GPIO_PDERS_P31_Pos 31 /**< \brief (GPIO_PDERS) Pull-down Enable */ 3417 #define GPIO_PDERS_P31 (_U_(0x1) << GPIO_PDERS_P31_Pos) 3418 #define GPIO_PDERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PDERS) MASK Register */ 3419 3420 /* -------- GPIO_PDERC : (GPIO Offset: 0x088) ( /W 32) port Pull-down Enable Register - Clear -------- */ 3421 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3422 typedef union { 3423 struct { 3424 uint32_t P0:1; /*!< bit: 0 Pull-down Enable */ 3425 uint32_t P1:1; /*!< bit: 1 Pull-down Enable */ 3426 uint32_t P2:1; /*!< bit: 2 Pull-down Enable */ 3427 uint32_t P3:1; /*!< bit: 3 Pull-down Enable */ 3428 uint32_t P4:1; /*!< bit: 4 Pull-down Enable */ 3429 uint32_t P5:1; /*!< bit: 5 Pull-down Enable */ 3430 uint32_t P6:1; /*!< bit: 6 Pull-down Enable */ 3431 uint32_t P7:1; /*!< bit: 7 Pull-down Enable */ 3432 uint32_t P8:1; /*!< bit: 8 Pull-down Enable */ 3433 uint32_t P9:1; /*!< bit: 9 Pull-down Enable */ 3434 uint32_t P10:1; /*!< bit: 10 Pull-down Enable */ 3435 uint32_t P11:1; /*!< bit: 11 Pull-down Enable */ 3436 uint32_t P12:1; /*!< bit: 12 Pull-down Enable */ 3437 uint32_t P13:1; /*!< bit: 13 Pull-down Enable */ 3438 uint32_t P14:1; /*!< bit: 14 Pull-down Enable */ 3439 uint32_t P15:1; /*!< bit: 15 Pull-down Enable */ 3440 uint32_t P16:1; /*!< bit: 16 Pull-down Enable */ 3441 uint32_t P17:1; /*!< bit: 17 Pull-down Enable */ 3442 uint32_t P18:1; /*!< bit: 18 Pull-down Enable */ 3443 uint32_t P19:1; /*!< bit: 19 Pull-down Enable */ 3444 uint32_t P20:1; /*!< bit: 20 Pull-down Enable */ 3445 uint32_t P21:1; /*!< bit: 21 Pull-down Enable */ 3446 uint32_t P22:1; /*!< bit: 22 Pull-down Enable */ 3447 uint32_t P23:1; /*!< bit: 23 Pull-down Enable */ 3448 uint32_t P24:1; /*!< bit: 24 Pull-down Enable */ 3449 uint32_t P25:1; /*!< bit: 25 Pull-down Enable */ 3450 uint32_t P26:1; /*!< bit: 26 Pull-down Enable */ 3451 uint32_t P27:1; /*!< bit: 27 Pull-down Enable */ 3452 uint32_t P28:1; /*!< bit: 28 Pull-down Enable */ 3453 uint32_t P29:1; /*!< bit: 29 Pull-down Enable */ 3454 uint32_t P30:1; /*!< bit: 30 Pull-down Enable */ 3455 uint32_t P31:1; /*!< bit: 31 Pull-down Enable */ 3456 } bit; /*!< Structure used for bit access */ 3457 uint32_t reg; /*!< Type used for register access */ 3458 } GPIO_PDERC_Type; 3459 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3460 3461 #define GPIO_PDERC_OFFSET 0x088 /**< \brief (GPIO_PDERC offset) Pull-down Enable Register - Clear */ 3462 3463 #define GPIO_PDERC_P0_Pos 0 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3464 #define GPIO_PDERC_P0 (_U_(0x1) << GPIO_PDERC_P0_Pos) 3465 #define GPIO_PDERC_P1_Pos 1 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3466 #define GPIO_PDERC_P1 (_U_(0x1) << GPIO_PDERC_P1_Pos) 3467 #define GPIO_PDERC_P2_Pos 2 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3468 #define GPIO_PDERC_P2 (_U_(0x1) << GPIO_PDERC_P2_Pos) 3469 #define GPIO_PDERC_P3_Pos 3 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3470 #define GPIO_PDERC_P3 (_U_(0x1) << GPIO_PDERC_P3_Pos) 3471 #define GPIO_PDERC_P4_Pos 4 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3472 #define GPIO_PDERC_P4 (_U_(0x1) << GPIO_PDERC_P4_Pos) 3473 #define GPIO_PDERC_P5_Pos 5 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3474 #define GPIO_PDERC_P5 (_U_(0x1) << GPIO_PDERC_P5_Pos) 3475 #define GPIO_PDERC_P6_Pos 6 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3476 #define GPIO_PDERC_P6 (_U_(0x1) << GPIO_PDERC_P6_Pos) 3477 #define GPIO_PDERC_P7_Pos 7 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3478 #define GPIO_PDERC_P7 (_U_(0x1) << GPIO_PDERC_P7_Pos) 3479 #define GPIO_PDERC_P8_Pos 8 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3480 #define GPIO_PDERC_P8 (_U_(0x1) << GPIO_PDERC_P8_Pos) 3481 #define GPIO_PDERC_P9_Pos 9 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3482 #define GPIO_PDERC_P9 (_U_(0x1) << GPIO_PDERC_P9_Pos) 3483 #define GPIO_PDERC_P10_Pos 10 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3484 #define GPIO_PDERC_P10 (_U_(0x1) << GPIO_PDERC_P10_Pos) 3485 #define GPIO_PDERC_P11_Pos 11 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3486 #define GPIO_PDERC_P11 (_U_(0x1) << GPIO_PDERC_P11_Pos) 3487 #define GPIO_PDERC_P12_Pos 12 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3488 #define GPIO_PDERC_P12 (_U_(0x1) << GPIO_PDERC_P12_Pos) 3489 #define GPIO_PDERC_P13_Pos 13 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3490 #define GPIO_PDERC_P13 (_U_(0x1) << GPIO_PDERC_P13_Pos) 3491 #define GPIO_PDERC_P14_Pos 14 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3492 #define GPIO_PDERC_P14 (_U_(0x1) << GPIO_PDERC_P14_Pos) 3493 #define GPIO_PDERC_P15_Pos 15 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3494 #define GPIO_PDERC_P15 (_U_(0x1) << GPIO_PDERC_P15_Pos) 3495 #define GPIO_PDERC_P16_Pos 16 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3496 #define GPIO_PDERC_P16 (_U_(0x1) << GPIO_PDERC_P16_Pos) 3497 #define GPIO_PDERC_P17_Pos 17 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3498 #define GPIO_PDERC_P17 (_U_(0x1) << GPIO_PDERC_P17_Pos) 3499 #define GPIO_PDERC_P18_Pos 18 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3500 #define GPIO_PDERC_P18 (_U_(0x1) << GPIO_PDERC_P18_Pos) 3501 #define GPIO_PDERC_P19_Pos 19 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3502 #define GPIO_PDERC_P19 (_U_(0x1) << GPIO_PDERC_P19_Pos) 3503 #define GPIO_PDERC_P20_Pos 20 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3504 #define GPIO_PDERC_P20 (_U_(0x1) << GPIO_PDERC_P20_Pos) 3505 #define GPIO_PDERC_P21_Pos 21 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3506 #define GPIO_PDERC_P21 (_U_(0x1) << GPIO_PDERC_P21_Pos) 3507 #define GPIO_PDERC_P22_Pos 22 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3508 #define GPIO_PDERC_P22 (_U_(0x1) << GPIO_PDERC_P22_Pos) 3509 #define GPIO_PDERC_P23_Pos 23 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3510 #define GPIO_PDERC_P23 (_U_(0x1) << GPIO_PDERC_P23_Pos) 3511 #define GPIO_PDERC_P24_Pos 24 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3512 #define GPIO_PDERC_P24 (_U_(0x1) << GPIO_PDERC_P24_Pos) 3513 #define GPIO_PDERC_P25_Pos 25 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3514 #define GPIO_PDERC_P25 (_U_(0x1) << GPIO_PDERC_P25_Pos) 3515 #define GPIO_PDERC_P26_Pos 26 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3516 #define GPIO_PDERC_P26 (_U_(0x1) << GPIO_PDERC_P26_Pos) 3517 #define GPIO_PDERC_P27_Pos 27 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3518 #define GPIO_PDERC_P27 (_U_(0x1) << GPIO_PDERC_P27_Pos) 3519 #define GPIO_PDERC_P28_Pos 28 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3520 #define GPIO_PDERC_P28 (_U_(0x1) << GPIO_PDERC_P28_Pos) 3521 #define GPIO_PDERC_P29_Pos 29 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3522 #define GPIO_PDERC_P29 (_U_(0x1) << GPIO_PDERC_P29_Pos) 3523 #define GPIO_PDERC_P30_Pos 30 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3524 #define GPIO_PDERC_P30 (_U_(0x1) << GPIO_PDERC_P30_Pos) 3525 #define GPIO_PDERC_P31_Pos 31 /**< \brief (GPIO_PDERC) Pull-down Enable */ 3526 #define GPIO_PDERC_P31 (_U_(0x1) << GPIO_PDERC_P31_Pos) 3527 #define GPIO_PDERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PDERC) MASK Register */ 3528 3529 /* -------- GPIO_PDERT : (GPIO Offset: 0x08C) ( /W 32) port Pull-down Enable Register - Toggle -------- */ 3530 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3531 typedef union { 3532 struct { 3533 uint32_t P0:1; /*!< bit: 0 Pull-down Enable */ 3534 uint32_t P1:1; /*!< bit: 1 Pull-down Enable */ 3535 uint32_t P2:1; /*!< bit: 2 Pull-down Enable */ 3536 uint32_t P3:1; /*!< bit: 3 Pull-down Enable */ 3537 uint32_t P4:1; /*!< bit: 4 Pull-down Enable */ 3538 uint32_t P5:1; /*!< bit: 5 Pull-down Enable */ 3539 uint32_t P6:1; /*!< bit: 6 Pull-down Enable */ 3540 uint32_t P7:1; /*!< bit: 7 Pull-down Enable */ 3541 uint32_t P8:1; /*!< bit: 8 Pull-down Enable */ 3542 uint32_t P9:1; /*!< bit: 9 Pull-down Enable */ 3543 uint32_t P10:1; /*!< bit: 10 Pull-down Enable */ 3544 uint32_t P11:1; /*!< bit: 11 Pull-down Enable */ 3545 uint32_t P12:1; /*!< bit: 12 Pull-down Enable */ 3546 uint32_t P13:1; /*!< bit: 13 Pull-down Enable */ 3547 uint32_t P14:1; /*!< bit: 14 Pull-down Enable */ 3548 uint32_t P15:1; /*!< bit: 15 Pull-down Enable */ 3549 uint32_t P16:1; /*!< bit: 16 Pull-down Enable */ 3550 uint32_t P17:1; /*!< bit: 17 Pull-down Enable */ 3551 uint32_t P18:1; /*!< bit: 18 Pull-down Enable */ 3552 uint32_t P19:1; /*!< bit: 19 Pull-down Enable */ 3553 uint32_t P20:1; /*!< bit: 20 Pull-down Enable */ 3554 uint32_t P21:1; /*!< bit: 21 Pull-down Enable */ 3555 uint32_t P22:1; /*!< bit: 22 Pull-down Enable */ 3556 uint32_t P23:1; /*!< bit: 23 Pull-down Enable */ 3557 uint32_t P24:1; /*!< bit: 24 Pull-down Enable */ 3558 uint32_t P25:1; /*!< bit: 25 Pull-down Enable */ 3559 uint32_t P26:1; /*!< bit: 26 Pull-down Enable */ 3560 uint32_t P27:1; /*!< bit: 27 Pull-down Enable */ 3561 uint32_t P28:1; /*!< bit: 28 Pull-down Enable */ 3562 uint32_t P29:1; /*!< bit: 29 Pull-down Enable */ 3563 uint32_t P30:1; /*!< bit: 30 Pull-down Enable */ 3564 uint32_t P31:1; /*!< bit: 31 Pull-down Enable */ 3565 } bit; /*!< Structure used for bit access */ 3566 uint32_t reg; /*!< Type used for register access */ 3567 } GPIO_PDERT_Type; 3568 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3569 3570 #define GPIO_PDERT_OFFSET 0x08C /**< \brief (GPIO_PDERT offset) Pull-down Enable Register - Toggle */ 3571 3572 #define GPIO_PDERT_P0_Pos 0 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3573 #define GPIO_PDERT_P0 (_U_(0x1) << GPIO_PDERT_P0_Pos) 3574 #define GPIO_PDERT_P1_Pos 1 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3575 #define GPIO_PDERT_P1 (_U_(0x1) << GPIO_PDERT_P1_Pos) 3576 #define GPIO_PDERT_P2_Pos 2 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3577 #define GPIO_PDERT_P2 (_U_(0x1) << GPIO_PDERT_P2_Pos) 3578 #define GPIO_PDERT_P3_Pos 3 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3579 #define GPIO_PDERT_P3 (_U_(0x1) << GPIO_PDERT_P3_Pos) 3580 #define GPIO_PDERT_P4_Pos 4 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3581 #define GPIO_PDERT_P4 (_U_(0x1) << GPIO_PDERT_P4_Pos) 3582 #define GPIO_PDERT_P5_Pos 5 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3583 #define GPIO_PDERT_P5 (_U_(0x1) << GPIO_PDERT_P5_Pos) 3584 #define GPIO_PDERT_P6_Pos 6 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3585 #define GPIO_PDERT_P6 (_U_(0x1) << GPIO_PDERT_P6_Pos) 3586 #define GPIO_PDERT_P7_Pos 7 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3587 #define GPIO_PDERT_P7 (_U_(0x1) << GPIO_PDERT_P7_Pos) 3588 #define GPIO_PDERT_P8_Pos 8 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3589 #define GPIO_PDERT_P8 (_U_(0x1) << GPIO_PDERT_P8_Pos) 3590 #define GPIO_PDERT_P9_Pos 9 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3591 #define GPIO_PDERT_P9 (_U_(0x1) << GPIO_PDERT_P9_Pos) 3592 #define GPIO_PDERT_P10_Pos 10 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3593 #define GPIO_PDERT_P10 (_U_(0x1) << GPIO_PDERT_P10_Pos) 3594 #define GPIO_PDERT_P11_Pos 11 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3595 #define GPIO_PDERT_P11 (_U_(0x1) << GPIO_PDERT_P11_Pos) 3596 #define GPIO_PDERT_P12_Pos 12 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3597 #define GPIO_PDERT_P12 (_U_(0x1) << GPIO_PDERT_P12_Pos) 3598 #define GPIO_PDERT_P13_Pos 13 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3599 #define GPIO_PDERT_P13 (_U_(0x1) << GPIO_PDERT_P13_Pos) 3600 #define GPIO_PDERT_P14_Pos 14 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3601 #define GPIO_PDERT_P14 (_U_(0x1) << GPIO_PDERT_P14_Pos) 3602 #define GPIO_PDERT_P15_Pos 15 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3603 #define GPIO_PDERT_P15 (_U_(0x1) << GPIO_PDERT_P15_Pos) 3604 #define GPIO_PDERT_P16_Pos 16 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3605 #define GPIO_PDERT_P16 (_U_(0x1) << GPIO_PDERT_P16_Pos) 3606 #define GPIO_PDERT_P17_Pos 17 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3607 #define GPIO_PDERT_P17 (_U_(0x1) << GPIO_PDERT_P17_Pos) 3608 #define GPIO_PDERT_P18_Pos 18 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3609 #define GPIO_PDERT_P18 (_U_(0x1) << GPIO_PDERT_P18_Pos) 3610 #define GPIO_PDERT_P19_Pos 19 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3611 #define GPIO_PDERT_P19 (_U_(0x1) << GPIO_PDERT_P19_Pos) 3612 #define GPIO_PDERT_P20_Pos 20 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3613 #define GPIO_PDERT_P20 (_U_(0x1) << GPIO_PDERT_P20_Pos) 3614 #define GPIO_PDERT_P21_Pos 21 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3615 #define GPIO_PDERT_P21 (_U_(0x1) << GPIO_PDERT_P21_Pos) 3616 #define GPIO_PDERT_P22_Pos 22 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3617 #define GPIO_PDERT_P22 (_U_(0x1) << GPIO_PDERT_P22_Pos) 3618 #define GPIO_PDERT_P23_Pos 23 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3619 #define GPIO_PDERT_P23 (_U_(0x1) << GPIO_PDERT_P23_Pos) 3620 #define GPIO_PDERT_P24_Pos 24 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3621 #define GPIO_PDERT_P24 (_U_(0x1) << GPIO_PDERT_P24_Pos) 3622 #define GPIO_PDERT_P25_Pos 25 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3623 #define GPIO_PDERT_P25 (_U_(0x1) << GPIO_PDERT_P25_Pos) 3624 #define GPIO_PDERT_P26_Pos 26 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3625 #define GPIO_PDERT_P26 (_U_(0x1) << GPIO_PDERT_P26_Pos) 3626 #define GPIO_PDERT_P27_Pos 27 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3627 #define GPIO_PDERT_P27 (_U_(0x1) << GPIO_PDERT_P27_Pos) 3628 #define GPIO_PDERT_P28_Pos 28 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3629 #define GPIO_PDERT_P28 (_U_(0x1) << GPIO_PDERT_P28_Pos) 3630 #define GPIO_PDERT_P29_Pos 29 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3631 #define GPIO_PDERT_P29 (_U_(0x1) << GPIO_PDERT_P29_Pos) 3632 #define GPIO_PDERT_P30_Pos 30 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3633 #define GPIO_PDERT_P30 (_U_(0x1) << GPIO_PDERT_P30_Pos) 3634 #define GPIO_PDERT_P31_Pos 31 /**< \brief (GPIO_PDERT) Pull-down Enable */ 3635 #define GPIO_PDERT_P31 (_U_(0x1) << GPIO_PDERT_P31_Pos) 3636 #define GPIO_PDERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PDERT) MASK Register */ 3637 3638 /* -------- GPIO_IER : (GPIO Offset: 0x090) (R/W 32) port Interrupt Enable Register -------- */ 3639 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3640 typedef union { 3641 struct { 3642 uint32_t P0:1; /*!< bit: 0 Interrupt Enable */ 3643 uint32_t P1:1; /*!< bit: 1 Interrupt Enable */ 3644 uint32_t P2:1; /*!< bit: 2 Interrupt Enable */ 3645 uint32_t P3:1; /*!< bit: 3 Interrupt Enable */ 3646 uint32_t P4:1; /*!< bit: 4 Interrupt Enable */ 3647 uint32_t P5:1; /*!< bit: 5 Interrupt Enable */ 3648 uint32_t P6:1; /*!< bit: 6 Interrupt Enable */ 3649 uint32_t P7:1; /*!< bit: 7 Interrupt Enable */ 3650 uint32_t P8:1; /*!< bit: 8 Interrupt Enable */ 3651 uint32_t P9:1; /*!< bit: 9 Interrupt Enable */ 3652 uint32_t P10:1; /*!< bit: 10 Interrupt Enable */ 3653 uint32_t P11:1; /*!< bit: 11 Interrupt Enable */ 3654 uint32_t P12:1; /*!< bit: 12 Interrupt Enable */ 3655 uint32_t P13:1; /*!< bit: 13 Interrupt Enable */ 3656 uint32_t P14:1; /*!< bit: 14 Interrupt Enable */ 3657 uint32_t P15:1; /*!< bit: 15 Interrupt Enable */ 3658 uint32_t P16:1; /*!< bit: 16 Interrupt Enable */ 3659 uint32_t P17:1; /*!< bit: 17 Interrupt Enable */ 3660 uint32_t P18:1; /*!< bit: 18 Interrupt Enable */ 3661 uint32_t P19:1; /*!< bit: 19 Interrupt Enable */ 3662 uint32_t P20:1; /*!< bit: 20 Interrupt Enable */ 3663 uint32_t P21:1; /*!< bit: 21 Interrupt Enable */ 3664 uint32_t P22:1; /*!< bit: 22 Interrupt Enable */ 3665 uint32_t P23:1; /*!< bit: 23 Interrupt Enable */ 3666 uint32_t P24:1; /*!< bit: 24 Interrupt Enable */ 3667 uint32_t P25:1; /*!< bit: 25 Interrupt Enable */ 3668 uint32_t P26:1; /*!< bit: 26 Interrupt Enable */ 3669 uint32_t P27:1; /*!< bit: 27 Interrupt Enable */ 3670 uint32_t P28:1; /*!< bit: 28 Interrupt Enable */ 3671 uint32_t P29:1; /*!< bit: 29 Interrupt Enable */ 3672 uint32_t P30:1; /*!< bit: 30 Interrupt Enable */ 3673 uint32_t P31:1; /*!< bit: 31 Interrupt Enable */ 3674 } bit; /*!< Structure used for bit access */ 3675 uint32_t reg; /*!< Type used for register access */ 3676 } GPIO_IER_Type; 3677 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3678 3679 #define GPIO_IER_OFFSET 0x090 /**< \brief (GPIO_IER offset) Interrupt Enable Register */ 3680 3681 #define GPIO_IER_P0_Pos 0 /**< \brief (GPIO_IER) Interrupt Enable */ 3682 #define GPIO_IER_P0 (_U_(0x1) << GPIO_IER_P0_Pos) 3683 #define GPIO_IER_P1_Pos 1 /**< \brief (GPIO_IER) Interrupt Enable */ 3684 #define GPIO_IER_P1 (_U_(0x1) << GPIO_IER_P1_Pos) 3685 #define GPIO_IER_P2_Pos 2 /**< \brief (GPIO_IER) Interrupt Enable */ 3686 #define GPIO_IER_P2 (_U_(0x1) << GPIO_IER_P2_Pos) 3687 #define GPIO_IER_P3_Pos 3 /**< \brief (GPIO_IER) Interrupt Enable */ 3688 #define GPIO_IER_P3 (_U_(0x1) << GPIO_IER_P3_Pos) 3689 #define GPIO_IER_P4_Pos 4 /**< \brief (GPIO_IER) Interrupt Enable */ 3690 #define GPIO_IER_P4 (_U_(0x1) << GPIO_IER_P4_Pos) 3691 #define GPIO_IER_P5_Pos 5 /**< \brief (GPIO_IER) Interrupt Enable */ 3692 #define GPIO_IER_P5 (_U_(0x1) << GPIO_IER_P5_Pos) 3693 #define GPIO_IER_P6_Pos 6 /**< \brief (GPIO_IER) Interrupt Enable */ 3694 #define GPIO_IER_P6 (_U_(0x1) << GPIO_IER_P6_Pos) 3695 #define GPIO_IER_P7_Pos 7 /**< \brief (GPIO_IER) Interrupt Enable */ 3696 #define GPIO_IER_P7 (_U_(0x1) << GPIO_IER_P7_Pos) 3697 #define GPIO_IER_P8_Pos 8 /**< \brief (GPIO_IER) Interrupt Enable */ 3698 #define GPIO_IER_P8 (_U_(0x1) << GPIO_IER_P8_Pos) 3699 #define GPIO_IER_P9_Pos 9 /**< \brief (GPIO_IER) Interrupt Enable */ 3700 #define GPIO_IER_P9 (_U_(0x1) << GPIO_IER_P9_Pos) 3701 #define GPIO_IER_P10_Pos 10 /**< \brief (GPIO_IER) Interrupt Enable */ 3702 #define GPIO_IER_P10 (_U_(0x1) << GPIO_IER_P10_Pos) 3703 #define GPIO_IER_P11_Pos 11 /**< \brief (GPIO_IER) Interrupt Enable */ 3704 #define GPIO_IER_P11 (_U_(0x1) << GPIO_IER_P11_Pos) 3705 #define GPIO_IER_P12_Pos 12 /**< \brief (GPIO_IER) Interrupt Enable */ 3706 #define GPIO_IER_P12 (_U_(0x1) << GPIO_IER_P12_Pos) 3707 #define GPIO_IER_P13_Pos 13 /**< \brief (GPIO_IER) Interrupt Enable */ 3708 #define GPIO_IER_P13 (_U_(0x1) << GPIO_IER_P13_Pos) 3709 #define GPIO_IER_P14_Pos 14 /**< \brief (GPIO_IER) Interrupt Enable */ 3710 #define GPIO_IER_P14 (_U_(0x1) << GPIO_IER_P14_Pos) 3711 #define GPIO_IER_P15_Pos 15 /**< \brief (GPIO_IER) Interrupt Enable */ 3712 #define GPIO_IER_P15 (_U_(0x1) << GPIO_IER_P15_Pos) 3713 #define GPIO_IER_P16_Pos 16 /**< \brief (GPIO_IER) Interrupt Enable */ 3714 #define GPIO_IER_P16 (_U_(0x1) << GPIO_IER_P16_Pos) 3715 #define GPIO_IER_P17_Pos 17 /**< \brief (GPIO_IER) Interrupt Enable */ 3716 #define GPIO_IER_P17 (_U_(0x1) << GPIO_IER_P17_Pos) 3717 #define GPIO_IER_P18_Pos 18 /**< \brief (GPIO_IER) Interrupt Enable */ 3718 #define GPIO_IER_P18 (_U_(0x1) << GPIO_IER_P18_Pos) 3719 #define GPIO_IER_P19_Pos 19 /**< \brief (GPIO_IER) Interrupt Enable */ 3720 #define GPIO_IER_P19 (_U_(0x1) << GPIO_IER_P19_Pos) 3721 #define GPIO_IER_P20_Pos 20 /**< \brief (GPIO_IER) Interrupt Enable */ 3722 #define GPIO_IER_P20 (_U_(0x1) << GPIO_IER_P20_Pos) 3723 #define GPIO_IER_P21_Pos 21 /**< \brief (GPIO_IER) Interrupt Enable */ 3724 #define GPIO_IER_P21 (_U_(0x1) << GPIO_IER_P21_Pos) 3725 #define GPIO_IER_P22_Pos 22 /**< \brief (GPIO_IER) Interrupt Enable */ 3726 #define GPIO_IER_P22 (_U_(0x1) << GPIO_IER_P22_Pos) 3727 #define GPIO_IER_P23_Pos 23 /**< \brief (GPIO_IER) Interrupt Enable */ 3728 #define GPIO_IER_P23 (_U_(0x1) << GPIO_IER_P23_Pos) 3729 #define GPIO_IER_P24_Pos 24 /**< \brief (GPIO_IER) Interrupt Enable */ 3730 #define GPIO_IER_P24 (_U_(0x1) << GPIO_IER_P24_Pos) 3731 #define GPIO_IER_P25_Pos 25 /**< \brief (GPIO_IER) Interrupt Enable */ 3732 #define GPIO_IER_P25 (_U_(0x1) << GPIO_IER_P25_Pos) 3733 #define GPIO_IER_P26_Pos 26 /**< \brief (GPIO_IER) Interrupt Enable */ 3734 #define GPIO_IER_P26 (_U_(0x1) << GPIO_IER_P26_Pos) 3735 #define GPIO_IER_P27_Pos 27 /**< \brief (GPIO_IER) Interrupt Enable */ 3736 #define GPIO_IER_P27 (_U_(0x1) << GPIO_IER_P27_Pos) 3737 #define GPIO_IER_P28_Pos 28 /**< \brief (GPIO_IER) Interrupt Enable */ 3738 #define GPIO_IER_P28 (_U_(0x1) << GPIO_IER_P28_Pos) 3739 #define GPIO_IER_P29_Pos 29 /**< \brief (GPIO_IER) Interrupt Enable */ 3740 #define GPIO_IER_P29 (_U_(0x1) << GPIO_IER_P29_Pos) 3741 #define GPIO_IER_P30_Pos 30 /**< \brief (GPIO_IER) Interrupt Enable */ 3742 #define GPIO_IER_P30 (_U_(0x1) << GPIO_IER_P30_Pos) 3743 #define GPIO_IER_P31_Pos 31 /**< \brief (GPIO_IER) Interrupt Enable */ 3744 #define GPIO_IER_P31 (_U_(0x1) << GPIO_IER_P31_Pos) 3745 #define GPIO_IER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IER) MASK Register */ 3746 3747 /* -------- GPIO_IERS : (GPIO Offset: 0x094) ( /W 32) port Interrupt Enable Register - Set -------- */ 3748 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3749 typedef union { 3750 struct { 3751 uint32_t P0:1; /*!< bit: 0 Interrupt Enable */ 3752 uint32_t P1:1; /*!< bit: 1 Interrupt Enable */ 3753 uint32_t P2:1; /*!< bit: 2 Interrupt Enable */ 3754 uint32_t P3:1; /*!< bit: 3 Interrupt Enable */ 3755 uint32_t P4:1; /*!< bit: 4 Interrupt Enable */ 3756 uint32_t P5:1; /*!< bit: 5 Interrupt Enable */ 3757 uint32_t P6:1; /*!< bit: 6 Interrupt Enable */ 3758 uint32_t P7:1; /*!< bit: 7 Interrupt Enable */ 3759 uint32_t P8:1; /*!< bit: 8 Interrupt Enable */ 3760 uint32_t P9:1; /*!< bit: 9 Interrupt Enable */ 3761 uint32_t P10:1; /*!< bit: 10 Interrupt Enable */ 3762 uint32_t P11:1; /*!< bit: 11 Interrupt Enable */ 3763 uint32_t P12:1; /*!< bit: 12 Interrupt Enable */ 3764 uint32_t P13:1; /*!< bit: 13 Interrupt Enable */ 3765 uint32_t P14:1; /*!< bit: 14 Interrupt Enable */ 3766 uint32_t P15:1; /*!< bit: 15 Interrupt Enable */ 3767 uint32_t P16:1; /*!< bit: 16 Interrupt Enable */ 3768 uint32_t P17:1; /*!< bit: 17 Interrupt Enable */ 3769 uint32_t P18:1; /*!< bit: 18 Interrupt Enable */ 3770 uint32_t P19:1; /*!< bit: 19 Interrupt Enable */ 3771 uint32_t P20:1; /*!< bit: 20 Interrupt Enable */ 3772 uint32_t P21:1; /*!< bit: 21 Interrupt Enable */ 3773 uint32_t P22:1; /*!< bit: 22 Interrupt Enable */ 3774 uint32_t P23:1; /*!< bit: 23 Interrupt Enable */ 3775 uint32_t P24:1; /*!< bit: 24 Interrupt Enable */ 3776 uint32_t P25:1; /*!< bit: 25 Interrupt Enable */ 3777 uint32_t P26:1; /*!< bit: 26 Interrupt Enable */ 3778 uint32_t P27:1; /*!< bit: 27 Interrupt Enable */ 3779 uint32_t P28:1; /*!< bit: 28 Interrupt Enable */ 3780 uint32_t P29:1; /*!< bit: 29 Interrupt Enable */ 3781 uint32_t P30:1; /*!< bit: 30 Interrupt Enable */ 3782 uint32_t P31:1; /*!< bit: 31 Interrupt Enable */ 3783 } bit; /*!< Structure used for bit access */ 3784 uint32_t reg; /*!< Type used for register access */ 3785 } GPIO_IERS_Type; 3786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3787 3788 #define GPIO_IERS_OFFSET 0x094 /**< \brief (GPIO_IERS offset) Interrupt Enable Register - Set */ 3789 3790 #define GPIO_IERS_P0_Pos 0 /**< \brief (GPIO_IERS) Interrupt Enable */ 3791 #define GPIO_IERS_P0 (_U_(0x1) << GPIO_IERS_P0_Pos) 3792 #define GPIO_IERS_P1_Pos 1 /**< \brief (GPIO_IERS) Interrupt Enable */ 3793 #define GPIO_IERS_P1 (_U_(0x1) << GPIO_IERS_P1_Pos) 3794 #define GPIO_IERS_P2_Pos 2 /**< \brief (GPIO_IERS) Interrupt Enable */ 3795 #define GPIO_IERS_P2 (_U_(0x1) << GPIO_IERS_P2_Pos) 3796 #define GPIO_IERS_P3_Pos 3 /**< \brief (GPIO_IERS) Interrupt Enable */ 3797 #define GPIO_IERS_P3 (_U_(0x1) << GPIO_IERS_P3_Pos) 3798 #define GPIO_IERS_P4_Pos 4 /**< \brief (GPIO_IERS) Interrupt Enable */ 3799 #define GPIO_IERS_P4 (_U_(0x1) << GPIO_IERS_P4_Pos) 3800 #define GPIO_IERS_P5_Pos 5 /**< \brief (GPIO_IERS) Interrupt Enable */ 3801 #define GPIO_IERS_P5 (_U_(0x1) << GPIO_IERS_P5_Pos) 3802 #define GPIO_IERS_P6_Pos 6 /**< \brief (GPIO_IERS) Interrupt Enable */ 3803 #define GPIO_IERS_P6 (_U_(0x1) << GPIO_IERS_P6_Pos) 3804 #define GPIO_IERS_P7_Pos 7 /**< \brief (GPIO_IERS) Interrupt Enable */ 3805 #define GPIO_IERS_P7 (_U_(0x1) << GPIO_IERS_P7_Pos) 3806 #define GPIO_IERS_P8_Pos 8 /**< \brief (GPIO_IERS) Interrupt Enable */ 3807 #define GPIO_IERS_P8 (_U_(0x1) << GPIO_IERS_P8_Pos) 3808 #define GPIO_IERS_P9_Pos 9 /**< \brief (GPIO_IERS) Interrupt Enable */ 3809 #define GPIO_IERS_P9 (_U_(0x1) << GPIO_IERS_P9_Pos) 3810 #define GPIO_IERS_P10_Pos 10 /**< \brief (GPIO_IERS) Interrupt Enable */ 3811 #define GPIO_IERS_P10 (_U_(0x1) << GPIO_IERS_P10_Pos) 3812 #define GPIO_IERS_P11_Pos 11 /**< \brief (GPIO_IERS) Interrupt Enable */ 3813 #define GPIO_IERS_P11 (_U_(0x1) << GPIO_IERS_P11_Pos) 3814 #define GPIO_IERS_P12_Pos 12 /**< \brief (GPIO_IERS) Interrupt Enable */ 3815 #define GPIO_IERS_P12 (_U_(0x1) << GPIO_IERS_P12_Pos) 3816 #define GPIO_IERS_P13_Pos 13 /**< \brief (GPIO_IERS) Interrupt Enable */ 3817 #define GPIO_IERS_P13 (_U_(0x1) << GPIO_IERS_P13_Pos) 3818 #define GPIO_IERS_P14_Pos 14 /**< \brief (GPIO_IERS) Interrupt Enable */ 3819 #define GPIO_IERS_P14 (_U_(0x1) << GPIO_IERS_P14_Pos) 3820 #define GPIO_IERS_P15_Pos 15 /**< \brief (GPIO_IERS) Interrupt Enable */ 3821 #define GPIO_IERS_P15 (_U_(0x1) << GPIO_IERS_P15_Pos) 3822 #define GPIO_IERS_P16_Pos 16 /**< \brief (GPIO_IERS) Interrupt Enable */ 3823 #define GPIO_IERS_P16 (_U_(0x1) << GPIO_IERS_P16_Pos) 3824 #define GPIO_IERS_P17_Pos 17 /**< \brief (GPIO_IERS) Interrupt Enable */ 3825 #define GPIO_IERS_P17 (_U_(0x1) << GPIO_IERS_P17_Pos) 3826 #define GPIO_IERS_P18_Pos 18 /**< \brief (GPIO_IERS) Interrupt Enable */ 3827 #define GPIO_IERS_P18 (_U_(0x1) << GPIO_IERS_P18_Pos) 3828 #define GPIO_IERS_P19_Pos 19 /**< \brief (GPIO_IERS) Interrupt Enable */ 3829 #define GPIO_IERS_P19 (_U_(0x1) << GPIO_IERS_P19_Pos) 3830 #define GPIO_IERS_P20_Pos 20 /**< \brief (GPIO_IERS) Interrupt Enable */ 3831 #define GPIO_IERS_P20 (_U_(0x1) << GPIO_IERS_P20_Pos) 3832 #define GPIO_IERS_P21_Pos 21 /**< \brief (GPIO_IERS) Interrupt Enable */ 3833 #define GPIO_IERS_P21 (_U_(0x1) << GPIO_IERS_P21_Pos) 3834 #define GPIO_IERS_P22_Pos 22 /**< \brief (GPIO_IERS) Interrupt Enable */ 3835 #define GPIO_IERS_P22 (_U_(0x1) << GPIO_IERS_P22_Pos) 3836 #define GPIO_IERS_P23_Pos 23 /**< \brief (GPIO_IERS) Interrupt Enable */ 3837 #define GPIO_IERS_P23 (_U_(0x1) << GPIO_IERS_P23_Pos) 3838 #define GPIO_IERS_P24_Pos 24 /**< \brief (GPIO_IERS) Interrupt Enable */ 3839 #define GPIO_IERS_P24 (_U_(0x1) << GPIO_IERS_P24_Pos) 3840 #define GPIO_IERS_P25_Pos 25 /**< \brief (GPIO_IERS) Interrupt Enable */ 3841 #define GPIO_IERS_P25 (_U_(0x1) << GPIO_IERS_P25_Pos) 3842 #define GPIO_IERS_P26_Pos 26 /**< \brief (GPIO_IERS) Interrupt Enable */ 3843 #define GPIO_IERS_P26 (_U_(0x1) << GPIO_IERS_P26_Pos) 3844 #define GPIO_IERS_P27_Pos 27 /**< \brief (GPIO_IERS) Interrupt Enable */ 3845 #define GPIO_IERS_P27 (_U_(0x1) << GPIO_IERS_P27_Pos) 3846 #define GPIO_IERS_P28_Pos 28 /**< \brief (GPIO_IERS) Interrupt Enable */ 3847 #define GPIO_IERS_P28 (_U_(0x1) << GPIO_IERS_P28_Pos) 3848 #define GPIO_IERS_P29_Pos 29 /**< \brief (GPIO_IERS) Interrupt Enable */ 3849 #define GPIO_IERS_P29 (_U_(0x1) << GPIO_IERS_P29_Pos) 3850 #define GPIO_IERS_P30_Pos 30 /**< \brief (GPIO_IERS) Interrupt Enable */ 3851 #define GPIO_IERS_P30 (_U_(0x1) << GPIO_IERS_P30_Pos) 3852 #define GPIO_IERS_P31_Pos 31 /**< \brief (GPIO_IERS) Interrupt Enable */ 3853 #define GPIO_IERS_P31 (_U_(0x1) << GPIO_IERS_P31_Pos) 3854 #define GPIO_IERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IERS) MASK Register */ 3855 3856 /* -------- GPIO_IERC : (GPIO Offset: 0x098) ( /W 32) port Interrupt Enable Register - Clear -------- */ 3857 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3858 typedef union { 3859 struct { 3860 uint32_t P0:1; /*!< bit: 0 Interrupt Enable */ 3861 uint32_t P1:1; /*!< bit: 1 Interrupt Enable */ 3862 uint32_t P2:1; /*!< bit: 2 Interrupt Enable */ 3863 uint32_t P3:1; /*!< bit: 3 Interrupt Enable */ 3864 uint32_t P4:1; /*!< bit: 4 Interrupt Enable */ 3865 uint32_t P5:1; /*!< bit: 5 Interrupt Enable */ 3866 uint32_t P6:1; /*!< bit: 6 Interrupt Enable */ 3867 uint32_t P7:1; /*!< bit: 7 Interrupt Enable */ 3868 uint32_t P8:1; /*!< bit: 8 Interrupt Enable */ 3869 uint32_t P9:1; /*!< bit: 9 Interrupt Enable */ 3870 uint32_t P10:1; /*!< bit: 10 Interrupt Enable */ 3871 uint32_t P11:1; /*!< bit: 11 Interrupt Enable */ 3872 uint32_t P12:1; /*!< bit: 12 Interrupt Enable */ 3873 uint32_t P13:1; /*!< bit: 13 Interrupt Enable */ 3874 uint32_t P14:1; /*!< bit: 14 Interrupt Enable */ 3875 uint32_t P15:1; /*!< bit: 15 Interrupt Enable */ 3876 uint32_t P16:1; /*!< bit: 16 Interrupt Enable */ 3877 uint32_t P17:1; /*!< bit: 17 Interrupt Enable */ 3878 uint32_t P18:1; /*!< bit: 18 Interrupt Enable */ 3879 uint32_t P19:1; /*!< bit: 19 Interrupt Enable */ 3880 uint32_t P20:1; /*!< bit: 20 Interrupt Enable */ 3881 uint32_t P21:1; /*!< bit: 21 Interrupt Enable */ 3882 uint32_t P22:1; /*!< bit: 22 Interrupt Enable */ 3883 uint32_t P23:1; /*!< bit: 23 Interrupt Enable */ 3884 uint32_t P24:1; /*!< bit: 24 Interrupt Enable */ 3885 uint32_t P25:1; /*!< bit: 25 Interrupt Enable */ 3886 uint32_t P26:1; /*!< bit: 26 Interrupt Enable */ 3887 uint32_t P27:1; /*!< bit: 27 Interrupt Enable */ 3888 uint32_t P28:1; /*!< bit: 28 Interrupt Enable */ 3889 uint32_t P29:1; /*!< bit: 29 Interrupt Enable */ 3890 uint32_t P30:1; /*!< bit: 30 Interrupt Enable */ 3891 uint32_t P31:1; /*!< bit: 31 Interrupt Enable */ 3892 } bit; /*!< Structure used for bit access */ 3893 uint32_t reg; /*!< Type used for register access */ 3894 } GPIO_IERC_Type; 3895 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3896 3897 #define GPIO_IERC_OFFSET 0x098 /**< \brief (GPIO_IERC offset) Interrupt Enable Register - Clear */ 3898 3899 #define GPIO_IERC_P0_Pos 0 /**< \brief (GPIO_IERC) Interrupt Enable */ 3900 #define GPIO_IERC_P0 (_U_(0x1) << GPIO_IERC_P0_Pos) 3901 #define GPIO_IERC_P1_Pos 1 /**< \brief (GPIO_IERC) Interrupt Enable */ 3902 #define GPIO_IERC_P1 (_U_(0x1) << GPIO_IERC_P1_Pos) 3903 #define GPIO_IERC_P2_Pos 2 /**< \brief (GPIO_IERC) Interrupt Enable */ 3904 #define GPIO_IERC_P2 (_U_(0x1) << GPIO_IERC_P2_Pos) 3905 #define GPIO_IERC_P3_Pos 3 /**< \brief (GPIO_IERC) Interrupt Enable */ 3906 #define GPIO_IERC_P3 (_U_(0x1) << GPIO_IERC_P3_Pos) 3907 #define GPIO_IERC_P4_Pos 4 /**< \brief (GPIO_IERC) Interrupt Enable */ 3908 #define GPIO_IERC_P4 (_U_(0x1) << GPIO_IERC_P4_Pos) 3909 #define GPIO_IERC_P5_Pos 5 /**< \brief (GPIO_IERC) Interrupt Enable */ 3910 #define GPIO_IERC_P5 (_U_(0x1) << GPIO_IERC_P5_Pos) 3911 #define GPIO_IERC_P6_Pos 6 /**< \brief (GPIO_IERC) Interrupt Enable */ 3912 #define GPIO_IERC_P6 (_U_(0x1) << GPIO_IERC_P6_Pos) 3913 #define GPIO_IERC_P7_Pos 7 /**< \brief (GPIO_IERC) Interrupt Enable */ 3914 #define GPIO_IERC_P7 (_U_(0x1) << GPIO_IERC_P7_Pos) 3915 #define GPIO_IERC_P8_Pos 8 /**< \brief (GPIO_IERC) Interrupt Enable */ 3916 #define GPIO_IERC_P8 (_U_(0x1) << GPIO_IERC_P8_Pos) 3917 #define GPIO_IERC_P9_Pos 9 /**< \brief (GPIO_IERC) Interrupt Enable */ 3918 #define GPIO_IERC_P9 (_U_(0x1) << GPIO_IERC_P9_Pos) 3919 #define GPIO_IERC_P10_Pos 10 /**< \brief (GPIO_IERC) Interrupt Enable */ 3920 #define GPIO_IERC_P10 (_U_(0x1) << GPIO_IERC_P10_Pos) 3921 #define GPIO_IERC_P11_Pos 11 /**< \brief (GPIO_IERC) Interrupt Enable */ 3922 #define GPIO_IERC_P11 (_U_(0x1) << GPIO_IERC_P11_Pos) 3923 #define GPIO_IERC_P12_Pos 12 /**< \brief (GPIO_IERC) Interrupt Enable */ 3924 #define GPIO_IERC_P12 (_U_(0x1) << GPIO_IERC_P12_Pos) 3925 #define GPIO_IERC_P13_Pos 13 /**< \brief (GPIO_IERC) Interrupt Enable */ 3926 #define GPIO_IERC_P13 (_U_(0x1) << GPIO_IERC_P13_Pos) 3927 #define GPIO_IERC_P14_Pos 14 /**< \brief (GPIO_IERC) Interrupt Enable */ 3928 #define GPIO_IERC_P14 (_U_(0x1) << GPIO_IERC_P14_Pos) 3929 #define GPIO_IERC_P15_Pos 15 /**< \brief (GPIO_IERC) Interrupt Enable */ 3930 #define GPIO_IERC_P15 (_U_(0x1) << GPIO_IERC_P15_Pos) 3931 #define GPIO_IERC_P16_Pos 16 /**< \brief (GPIO_IERC) Interrupt Enable */ 3932 #define GPIO_IERC_P16 (_U_(0x1) << GPIO_IERC_P16_Pos) 3933 #define GPIO_IERC_P17_Pos 17 /**< \brief (GPIO_IERC) Interrupt Enable */ 3934 #define GPIO_IERC_P17 (_U_(0x1) << GPIO_IERC_P17_Pos) 3935 #define GPIO_IERC_P18_Pos 18 /**< \brief (GPIO_IERC) Interrupt Enable */ 3936 #define GPIO_IERC_P18 (_U_(0x1) << GPIO_IERC_P18_Pos) 3937 #define GPIO_IERC_P19_Pos 19 /**< \brief (GPIO_IERC) Interrupt Enable */ 3938 #define GPIO_IERC_P19 (_U_(0x1) << GPIO_IERC_P19_Pos) 3939 #define GPIO_IERC_P20_Pos 20 /**< \brief (GPIO_IERC) Interrupt Enable */ 3940 #define GPIO_IERC_P20 (_U_(0x1) << GPIO_IERC_P20_Pos) 3941 #define GPIO_IERC_P21_Pos 21 /**< \brief (GPIO_IERC) Interrupt Enable */ 3942 #define GPIO_IERC_P21 (_U_(0x1) << GPIO_IERC_P21_Pos) 3943 #define GPIO_IERC_P22_Pos 22 /**< \brief (GPIO_IERC) Interrupt Enable */ 3944 #define GPIO_IERC_P22 (_U_(0x1) << GPIO_IERC_P22_Pos) 3945 #define GPIO_IERC_P23_Pos 23 /**< \brief (GPIO_IERC) Interrupt Enable */ 3946 #define GPIO_IERC_P23 (_U_(0x1) << GPIO_IERC_P23_Pos) 3947 #define GPIO_IERC_P24_Pos 24 /**< \brief (GPIO_IERC) Interrupt Enable */ 3948 #define GPIO_IERC_P24 (_U_(0x1) << GPIO_IERC_P24_Pos) 3949 #define GPIO_IERC_P25_Pos 25 /**< \brief (GPIO_IERC) Interrupt Enable */ 3950 #define GPIO_IERC_P25 (_U_(0x1) << GPIO_IERC_P25_Pos) 3951 #define GPIO_IERC_P26_Pos 26 /**< \brief (GPIO_IERC) Interrupt Enable */ 3952 #define GPIO_IERC_P26 (_U_(0x1) << GPIO_IERC_P26_Pos) 3953 #define GPIO_IERC_P27_Pos 27 /**< \brief (GPIO_IERC) Interrupt Enable */ 3954 #define GPIO_IERC_P27 (_U_(0x1) << GPIO_IERC_P27_Pos) 3955 #define GPIO_IERC_P28_Pos 28 /**< \brief (GPIO_IERC) Interrupt Enable */ 3956 #define GPIO_IERC_P28 (_U_(0x1) << GPIO_IERC_P28_Pos) 3957 #define GPIO_IERC_P29_Pos 29 /**< \brief (GPIO_IERC) Interrupt Enable */ 3958 #define GPIO_IERC_P29 (_U_(0x1) << GPIO_IERC_P29_Pos) 3959 #define GPIO_IERC_P30_Pos 30 /**< \brief (GPIO_IERC) Interrupt Enable */ 3960 #define GPIO_IERC_P30 (_U_(0x1) << GPIO_IERC_P30_Pos) 3961 #define GPIO_IERC_P31_Pos 31 /**< \brief (GPIO_IERC) Interrupt Enable */ 3962 #define GPIO_IERC_P31 (_U_(0x1) << GPIO_IERC_P31_Pos) 3963 #define GPIO_IERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IERC) MASK Register */ 3964 3965 /* -------- GPIO_IERT : (GPIO Offset: 0x09C) ( /W 32) port Interrupt Enable Register - Toggle -------- */ 3966 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3967 typedef union { 3968 struct { 3969 uint32_t P0:1; /*!< bit: 0 Interrupt Enable */ 3970 uint32_t P1:1; /*!< bit: 1 Interrupt Enable */ 3971 uint32_t P2:1; /*!< bit: 2 Interrupt Enable */ 3972 uint32_t P3:1; /*!< bit: 3 Interrupt Enable */ 3973 uint32_t P4:1; /*!< bit: 4 Interrupt Enable */ 3974 uint32_t P5:1; /*!< bit: 5 Interrupt Enable */ 3975 uint32_t P6:1; /*!< bit: 6 Interrupt Enable */ 3976 uint32_t P7:1; /*!< bit: 7 Interrupt Enable */ 3977 uint32_t P8:1; /*!< bit: 8 Interrupt Enable */ 3978 uint32_t P9:1; /*!< bit: 9 Interrupt Enable */ 3979 uint32_t P10:1; /*!< bit: 10 Interrupt Enable */ 3980 uint32_t P11:1; /*!< bit: 11 Interrupt Enable */ 3981 uint32_t P12:1; /*!< bit: 12 Interrupt Enable */ 3982 uint32_t P13:1; /*!< bit: 13 Interrupt Enable */ 3983 uint32_t P14:1; /*!< bit: 14 Interrupt Enable */ 3984 uint32_t P15:1; /*!< bit: 15 Interrupt Enable */ 3985 uint32_t P16:1; /*!< bit: 16 Interrupt Enable */ 3986 uint32_t P17:1; /*!< bit: 17 Interrupt Enable */ 3987 uint32_t P18:1; /*!< bit: 18 Interrupt Enable */ 3988 uint32_t P19:1; /*!< bit: 19 Interrupt Enable */ 3989 uint32_t P20:1; /*!< bit: 20 Interrupt Enable */ 3990 uint32_t P21:1; /*!< bit: 21 Interrupt Enable */ 3991 uint32_t P22:1; /*!< bit: 22 Interrupt Enable */ 3992 uint32_t P23:1; /*!< bit: 23 Interrupt Enable */ 3993 uint32_t P24:1; /*!< bit: 24 Interrupt Enable */ 3994 uint32_t P25:1; /*!< bit: 25 Interrupt Enable */ 3995 uint32_t P26:1; /*!< bit: 26 Interrupt Enable */ 3996 uint32_t P27:1; /*!< bit: 27 Interrupt Enable */ 3997 uint32_t P28:1; /*!< bit: 28 Interrupt Enable */ 3998 uint32_t P29:1; /*!< bit: 29 Interrupt Enable */ 3999 uint32_t P30:1; /*!< bit: 30 Interrupt Enable */ 4000 uint32_t P31:1; /*!< bit: 31 Interrupt Enable */ 4001 } bit; /*!< Structure used for bit access */ 4002 uint32_t reg; /*!< Type used for register access */ 4003 } GPIO_IERT_Type; 4004 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4005 4006 #define GPIO_IERT_OFFSET 0x09C /**< \brief (GPIO_IERT offset) Interrupt Enable Register - Toggle */ 4007 4008 #define GPIO_IERT_P0_Pos 0 /**< \brief (GPIO_IERT) Interrupt Enable */ 4009 #define GPIO_IERT_P0 (_U_(0x1) << GPIO_IERT_P0_Pos) 4010 #define GPIO_IERT_P1_Pos 1 /**< \brief (GPIO_IERT) Interrupt Enable */ 4011 #define GPIO_IERT_P1 (_U_(0x1) << GPIO_IERT_P1_Pos) 4012 #define GPIO_IERT_P2_Pos 2 /**< \brief (GPIO_IERT) Interrupt Enable */ 4013 #define GPIO_IERT_P2 (_U_(0x1) << GPIO_IERT_P2_Pos) 4014 #define GPIO_IERT_P3_Pos 3 /**< \brief (GPIO_IERT) Interrupt Enable */ 4015 #define GPIO_IERT_P3 (_U_(0x1) << GPIO_IERT_P3_Pos) 4016 #define GPIO_IERT_P4_Pos 4 /**< \brief (GPIO_IERT) Interrupt Enable */ 4017 #define GPIO_IERT_P4 (_U_(0x1) << GPIO_IERT_P4_Pos) 4018 #define GPIO_IERT_P5_Pos 5 /**< \brief (GPIO_IERT) Interrupt Enable */ 4019 #define GPIO_IERT_P5 (_U_(0x1) << GPIO_IERT_P5_Pos) 4020 #define GPIO_IERT_P6_Pos 6 /**< \brief (GPIO_IERT) Interrupt Enable */ 4021 #define GPIO_IERT_P6 (_U_(0x1) << GPIO_IERT_P6_Pos) 4022 #define GPIO_IERT_P7_Pos 7 /**< \brief (GPIO_IERT) Interrupt Enable */ 4023 #define GPIO_IERT_P7 (_U_(0x1) << GPIO_IERT_P7_Pos) 4024 #define GPIO_IERT_P8_Pos 8 /**< \brief (GPIO_IERT) Interrupt Enable */ 4025 #define GPIO_IERT_P8 (_U_(0x1) << GPIO_IERT_P8_Pos) 4026 #define GPIO_IERT_P9_Pos 9 /**< \brief (GPIO_IERT) Interrupt Enable */ 4027 #define GPIO_IERT_P9 (_U_(0x1) << GPIO_IERT_P9_Pos) 4028 #define GPIO_IERT_P10_Pos 10 /**< \brief (GPIO_IERT) Interrupt Enable */ 4029 #define GPIO_IERT_P10 (_U_(0x1) << GPIO_IERT_P10_Pos) 4030 #define GPIO_IERT_P11_Pos 11 /**< \brief (GPIO_IERT) Interrupt Enable */ 4031 #define GPIO_IERT_P11 (_U_(0x1) << GPIO_IERT_P11_Pos) 4032 #define GPIO_IERT_P12_Pos 12 /**< \brief (GPIO_IERT) Interrupt Enable */ 4033 #define GPIO_IERT_P12 (_U_(0x1) << GPIO_IERT_P12_Pos) 4034 #define GPIO_IERT_P13_Pos 13 /**< \brief (GPIO_IERT) Interrupt Enable */ 4035 #define GPIO_IERT_P13 (_U_(0x1) << GPIO_IERT_P13_Pos) 4036 #define GPIO_IERT_P14_Pos 14 /**< \brief (GPIO_IERT) Interrupt Enable */ 4037 #define GPIO_IERT_P14 (_U_(0x1) << GPIO_IERT_P14_Pos) 4038 #define GPIO_IERT_P15_Pos 15 /**< \brief (GPIO_IERT) Interrupt Enable */ 4039 #define GPIO_IERT_P15 (_U_(0x1) << GPIO_IERT_P15_Pos) 4040 #define GPIO_IERT_P16_Pos 16 /**< \brief (GPIO_IERT) Interrupt Enable */ 4041 #define GPIO_IERT_P16 (_U_(0x1) << GPIO_IERT_P16_Pos) 4042 #define GPIO_IERT_P17_Pos 17 /**< \brief (GPIO_IERT) Interrupt Enable */ 4043 #define GPIO_IERT_P17 (_U_(0x1) << GPIO_IERT_P17_Pos) 4044 #define GPIO_IERT_P18_Pos 18 /**< \brief (GPIO_IERT) Interrupt Enable */ 4045 #define GPIO_IERT_P18 (_U_(0x1) << GPIO_IERT_P18_Pos) 4046 #define GPIO_IERT_P19_Pos 19 /**< \brief (GPIO_IERT) Interrupt Enable */ 4047 #define GPIO_IERT_P19 (_U_(0x1) << GPIO_IERT_P19_Pos) 4048 #define GPIO_IERT_P20_Pos 20 /**< \brief (GPIO_IERT) Interrupt Enable */ 4049 #define GPIO_IERT_P20 (_U_(0x1) << GPIO_IERT_P20_Pos) 4050 #define GPIO_IERT_P21_Pos 21 /**< \brief (GPIO_IERT) Interrupt Enable */ 4051 #define GPIO_IERT_P21 (_U_(0x1) << GPIO_IERT_P21_Pos) 4052 #define GPIO_IERT_P22_Pos 22 /**< \brief (GPIO_IERT) Interrupt Enable */ 4053 #define GPIO_IERT_P22 (_U_(0x1) << GPIO_IERT_P22_Pos) 4054 #define GPIO_IERT_P23_Pos 23 /**< \brief (GPIO_IERT) Interrupt Enable */ 4055 #define GPIO_IERT_P23 (_U_(0x1) << GPIO_IERT_P23_Pos) 4056 #define GPIO_IERT_P24_Pos 24 /**< \brief (GPIO_IERT) Interrupt Enable */ 4057 #define GPIO_IERT_P24 (_U_(0x1) << GPIO_IERT_P24_Pos) 4058 #define GPIO_IERT_P25_Pos 25 /**< \brief (GPIO_IERT) Interrupt Enable */ 4059 #define GPIO_IERT_P25 (_U_(0x1) << GPIO_IERT_P25_Pos) 4060 #define GPIO_IERT_P26_Pos 26 /**< \brief (GPIO_IERT) Interrupt Enable */ 4061 #define GPIO_IERT_P26 (_U_(0x1) << GPIO_IERT_P26_Pos) 4062 #define GPIO_IERT_P27_Pos 27 /**< \brief (GPIO_IERT) Interrupt Enable */ 4063 #define GPIO_IERT_P27 (_U_(0x1) << GPIO_IERT_P27_Pos) 4064 #define GPIO_IERT_P28_Pos 28 /**< \brief (GPIO_IERT) Interrupt Enable */ 4065 #define GPIO_IERT_P28 (_U_(0x1) << GPIO_IERT_P28_Pos) 4066 #define GPIO_IERT_P29_Pos 29 /**< \brief (GPIO_IERT) Interrupt Enable */ 4067 #define GPIO_IERT_P29 (_U_(0x1) << GPIO_IERT_P29_Pos) 4068 #define GPIO_IERT_P30_Pos 30 /**< \brief (GPIO_IERT) Interrupt Enable */ 4069 #define GPIO_IERT_P30 (_U_(0x1) << GPIO_IERT_P30_Pos) 4070 #define GPIO_IERT_P31_Pos 31 /**< \brief (GPIO_IERT) Interrupt Enable */ 4071 #define GPIO_IERT_P31 (_U_(0x1) << GPIO_IERT_P31_Pos) 4072 #define GPIO_IERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IERT) MASK Register */ 4073 4074 /* -------- GPIO_IMR0 : (GPIO Offset: 0x0A0) (R/W 32) port Interrupt Mode Register 0 -------- */ 4075 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4076 typedef union { 4077 struct { 4078 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 0 */ 4079 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 0 */ 4080 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 0 */ 4081 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 0 */ 4082 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 0 */ 4083 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 0 */ 4084 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 0 */ 4085 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 0 */ 4086 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 0 */ 4087 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 0 */ 4088 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 0 */ 4089 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 0 */ 4090 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 0 */ 4091 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 0 */ 4092 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 0 */ 4093 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 0 */ 4094 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 0 */ 4095 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 0 */ 4096 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 0 */ 4097 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 0 */ 4098 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 0 */ 4099 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 0 */ 4100 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 0 */ 4101 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 0 */ 4102 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 0 */ 4103 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 0 */ 4104 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 0 */ 4105 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 0 */ 4106 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 0 */ 4107 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 0 */ 4108 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 0 */ 4109 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 0 */ 4110 } bit; /*!< Structure used for bit access */ 4111 uint32_t reg; /*!< Type used for register access */ 4112 } GPIO_IMR0_Type; 4113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4114 4115 #define GPIO_IMR0_OFFSET 0x0A0 /**< \brief (GPIO_IMR0 offset) Interrupt Mode Register 0 */ 4116 4117 #define GPIO_IMR0_P0_Pos 0 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4118 #define GPIO_IMR0_P0 (_U_(0x1) << GPIO_IMR0_P0_Pos) 4119 #define GPIO_IMR0_P1_Pos 1 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4120 #define GPIO_IMR0_P1 (_U_(0x1) << GPIO_IMR0_P1_Pos) 4121 #define GPIO_IMR0_P2_Pos 2 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4122 #define GPIO_IMR0_P2 (_U_(0x1) << GPIO_IMR0_P2_Pos) 4123 #define GPIO_IMR0_P3_Pos 3 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4124 #define GPIO_IMR0_P3 (_U_(0x1) << GPIO_IMR0_P3_Pos) 4125 #define GPIO_IMR0_P4_Pos 4 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4126 #define GPIO_IMR0_P4 (_U_(0x1) << GPIO_IMR0_P4_Pos) 4127 #define GPIO_IMR0_P5_Pos 5 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4128 #define GPIO_IMR0_P5 (_U_(0x1) << GPIO_IMR0_P5_Pos) 4129 #define GPIO_IMR0_P6_Pos 6 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4130 #define GPIO_IMR0_P6 (_U_(0x1) << GPIO_IMR0_P6_Pos) 4131 #define GPIO_IMR0_P7_Pos 7 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4132 #define GPIO_IMR0_P7 (_U_(0x1) << GPIO_IMR0_P7_Pos) 4133 #define GPIO_IMR0_P8_Pos 8 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4134 #define GPIO_IMR0_P8 (_U_(0x1) << GPIO_IMR0_P8_Pos) 4135 #define GPIO_IMR0_P9_Pos 9 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4136 #define GPIO_IMR0_P9 (_U_(0x1) << GPIO_IMR0_P9_Pos) 4137 #define GPIO_IMR0_P10_Pos 10 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4138 #define GPIO_IMR0_P10 (_U_(0x1) << GPIO_IMR0_P10_Pos) 4139 #define GPIO_IMR0_P11_Pos 11 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4140 #define GPIO_IMR0_P11 (_U_(0x1) << GPIO_IMR0_P11_Pos) 4141 #define GPIO_IMR0_P12_Pos 12 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4142 #define GPIO_IMR0_P12 (_U_(0x1) << GPIO_IMR0_P12_Pos) 4143 #define GPIO_IMR0_P13_Pos 13 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4144 #define GPIO_IMR0_P13 (_U_(0x1) << GPIO_IMR0_P13_Pos) 4145 #define GPIO_IMR0_P14_Pos 14 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4146 #define GPIO_IMR0_P14 (_U_(0x1) << GPIO_IMR0_P14_Pos) 4147 #define GPIO_IMR0_P15_Pos 15 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4148 #define GPIO_IMR0_P15 (_U_(0x1) << GPIO_IMR0_P15_Pos) 4149 #define GPIO_IMR0_P16_Pos 16 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4150 #define GPIO_IMR0_P16 (_U_(0x1) << GPIO_IMR0_P16_Pos) 4151 #define GPIO_IMR0_P17_Pos 17 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4152 #define GPIO_IMR0_P17 (_U_(0x1) << GPIO_IMR0_P17_Pos) 4153 #define GPIO_IMR0_P18_Pos 18 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4154 #define GPIO_IMR0_P18 (_U_(0x1) << GPIO_IMR0_P18_Pos) 4155 #define GPIO_IMR0_P19_Pos 19 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4156 #define GPIO_IMR0_P19 (_U_(0x1) << GPIO_IMR0_P19_Pos) 4157 #define GPIO_IMR0_P20_Pos 20 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4158 #define GPIO_IMR0_P20 (_U_(0x1) << GPIO_IMR0_P20_Pos) 4159 #define GPIO_IMR0_P21_Pos 21 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4160 #define GPIO_IMR0_P21 (_U_(0x1) << GPIO_IMR0_P21_Pos) 4161 #define GPIO_IMR0_P22_Pos 22 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4162 #define GPIO_IMR0_P22 (_U_(0x1) << GPIO_IMR0_P22_Pos) 4163 #define GPIO_IMR0_P23_Pos 23 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4164 #define GPIO_IMR0_P23 (_U_(0x1) << GPIO_IMR0_P23_Pos) 4165 #define GPIO_IMR0_P24_Pos 24 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4166 #define GPIO_IMR0_P24 (_U_(0x1) << GPIO_IMR0_P24_Pos) 4167 #define GPIO_IMR0_P25_Pos 25 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4168 #define GPIO_IMR0_P25 (_U_(0x1) << GPIO_IMR0_P25_Pos) 4169 #define GPIO_IMR0_P26_Pos 26 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4170 #define GPIO_IMR0_P26 (_U_(0x1) << GPIO_IMR0_P26_Pos) 4171 #define GPIO_IMR0_P27_Pos 27 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4172 #define GPIO_IMR0_P27 (_U_(0x1) << GPIO_IMR0_P27_Pos) 4173 #define GPIO_IMR0_P28_Pos 28 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4174 #define GPIO_IMR0_P28 (_U_(0x1) << GPIO_IMR0_P28_Pos) 4175 #define GPIO_IMR0_P29_Pos 29 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4176 #define GPIO_IMR0_P29 (_U_(0x1) << GPIO_IMR0_P29_Pos) 4177 #define GPIO_IMR0_P30_Pos 30 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4178 #define GPIO_IMR0_P30 (_U_(0x1) << GPIO_IMR0_P30_Pos) 4179 #define GPIO_IMR0_P31_Pos 31 /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */ 4180 #define GPIO_IMR0_P31 (_U_(0x1) << GPIO_IMR0_P31_Pos) 4181 #define GPIO_IMR0_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR0) MASK Register */ 4182 4183 /* -------- GPIO_IMR0S : (GPIO Offset: 0x0A4) ( /W 32) port Interrupt Mode Register 0 - Set -------- */ 4184 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4185 typedef union { 4186 struct { 4187 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 0 */ 4188 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 0 */ 4189 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 0 */ 4190 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 0 */ 4191 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 0 */ 4192 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 0 */ 4193 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 0 */ 4194 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 0 */ 4195 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 0 */ 4196 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 0 */ 4197 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 0 */ 4198 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 0 */ 4199 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 0 */ 4200 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 0 */ 4201 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 0 */ 4202 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 0 */ 4203 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 0 */ 4204 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 0 */ 4205 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 0 */ 4206 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 0 */ 4207 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 0 */ 4208 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 0 */ 4209 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 0 */ 4210 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 0 */ 4211 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 0 */ 4212 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 0 */ 4213 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 0 */ 4214 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 0 */ 4215 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 0 */ 4216 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 0 */ 4217 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 0 */ 4218 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 0 */ 4219 } bit; /*!< Structure used for bit access */ 4220 uint32_t reg; /*!< Type used for register access */ 4221 } GPIO_IMR0S_Type; 4222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4223 4224 #define GPIO_IMR0S_OFFSET 0x0A4 /**< \brief (GPIO_IMR0S offset) Interrupt Mode Register 0 - Set */ 4225 4226 #define GPIO_IMR0S_P0_Pos 0 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4227 #define GPIO_IMR0S_P0 (_U_(0x1) << GPIO_IMR0S_P0_Pos) 4228 #define GPIO_IMR0S_P1_Pos 1 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4229 #define GPIO_IMR0S_P1 (_U_(0x1) << GPIO_IMR0S_P1_Pos) 4230 #define GPIO_IMR0S_P2_Pos 2 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4231 #define GPIO_IMR0S_P2 (_U_(0x1) << GPIO_IMR0S_P2_Pos) 4232 #define GPIO_IMR0S_P3_Pos 3 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4233 #define GPIO_IMR0S_P3 (_U_(0x1) << GPIO_IMR0S_P3_Pos) 4234 #define GPIO_IMR0S_P4_Pos 4 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4235 #define GPIO_IMR0S_P4 (_U_(0x1) << GPIO_IMR0S_P4_Pos) 4236 #define GPIO_IMR0S_P5_Pos 5 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4237 #define GPIO_IMR0S_P5 (_U_(0x1) << GPIO_IMR0S_P5_Pos) 4238 #define GPIO_IMR0S_P6_Pos 6 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4239 #define GPIO_IMR0S_P6 (_U_(0x1) << GPIO_IMR0S_P6_Pos) 4240 #define GPIO_IMR0S_P7_Pos 7 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4241 #define GPIO_IMR0S_P7 (_U_(0x1) << GPIO_IMR0S_P7_Pos) 4242 #define GPIO_IMR0S_P8_Pos 8 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4243 #define GPIO_IMR0S_P8 (_U_(0x1) << GPIO_IMR0S_P8_Pos) 4244 #define GPIO_IMR0S_P9_Pos 9 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4245 #define GPIO_IMR0S_P9 (_U_(0x1) << GPIO_IMR0S_P9_Pos) 4246 #define GPIO_IMR0S_P10_Pos 10 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4247 #define GPIO_IMR0S_P10 (_U_(0x1) << GPIO_IMR0S_P10_Pos) 4248 #define GPIO_IMR0S_P11_Pos 11 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4249 #define GPIO_IMR0S_P11 (_U_(0x1) << GPIO_IMR0S_P11_Pos) 4250 #define GPIO_IMR0S_P12_Pos 12 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4251 #define GPIO_IMR0S_P12 (_U_(0x1) << GPIO_IMR0S_P12_Pos) 4252 #define GPIO_IMR0S_P13_Pos 13 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4253 #define GPIO_IMR0S_P13 (_U_(0x1) << GPIO_IMR0S_P13_Pos) 4254 #define GPIO_IMR0S_P14_Pos 14 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4255 #define GPIO_IMR0S_P14 (_U_(0x1) << GPIO_IMR0S_P14_Pos) 4256 #define GPIO_IMR0S_P15_Pos 15 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4257 #define GPIO_IMR0S_P15 (_U_(0x1) << GPIO_IMR0S_P15_Pos) 4258 #define GPIO_IMR0S_P16_Pos 16 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4259 #define GPIO_IMR0S_P16 (_U_(0x1) << GPIO_IMR0S_P16_Pos) 4260 #define GPIO_IMR0S_P17_Pos 17 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4261 #define GPIO_IMR0S_P17 (_U_(0x1) << GPIO_IMR0S_P17_Pos) 4262 #define GPIO_IMR0S_P18_Pos 18 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4263 #define GPIO_IMR0S_P18 (_U_(0x1) << GPIO_IMR0S_P18_Pos) 4264 #define GPIO_IMR0S_P19_Pos 19 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4265 #define GPIO_IMR0S_P19 (_U_(0x1) << GPIO_IMR0S_P19_Pos) 4266 #define GPIO_IMR0S_P20_Pos 20 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4267 #define GPIO_IMR0S_P20 (_U_(0x1) << GPIO_IMR0S_P20_Pos) 4268 #define GPIO_IMR0S_P21_Pos 21 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4269 #define GPIO_IMR0S_P21 (_U_(0x1) << GPIO_IMR0S_P21_Pos) 4270 #define GPIO_IMR0S_P22_Pos 22 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4271 #define GPIO_IMR0S_P22 (_U_(0x1) << GPIO_IMR0S_P22_Pos) 4272 #define GPIO_IMR0S_P23_Pos 23 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4273 #define GPIO_IMR0S_P23 (_U_(0x1) << GPIO_IMR0S_P23_Pos) 4274 #define GPIO_IMR0S_P24_Pos 24 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4275 #define GPIO_IMR0S_P24 (_U_(0x1) << GPIO_IMR0S_P24_Pos) 4276 #define GPIO_IMR0S_P25_Pos 25 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4277 #define GPIO_IMR0S_P25 (_U_(0x1) << GPIO_IMR0S_P25_Pos) 4278 #define GPIO_IMR0S_P26_Pos 26 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4279 #define GPIO_IMR0S_P26 (_U_(0x1) << GPIO_IMR0S_P26_Pos) 4280 #define GPIO_IMR0S_P27_Pos 27 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4281 #define GPIO_IMR0S_P27 (_U_(0x1) << GPIO_IMR0S_P27_Pos) 4282 #define GPIO_IMR0S_P28_Pos 28 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4283 #define GPIO_IMR0S_P28 (_U_(0x1) << GPIO_IMR0S_P28_Pos) 4284 #define GPIO_IMR0S_P29_Pos 29 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4285 #define GPIO_IMR0S_P29 (_U_(0x1) << GPIO_IMR0S_P29_Pos) 4286 #define GPIO_IMR0S_P30_Pos 30 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4287 #define GPIO_IMR0S_P30 (_U_(0x1) << GPIO_IMR0S_P30_Pos) 4288 #define GPIO_IMR0S_P31_Pos 31 /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */ 4289 #define GPIO_IMR0S_P31 (_U_(0x1) << GPIO_IMR0S_P31_Pos) 4290 #define GPIO_IMR0S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR0S) MASK Register */ 4291 4292 /* -------- GPIO_IMR0C : (GPIO Offset: 0x0A8) ( /W 32) port Interrupt Mode Register 0 - Clear -------- */ 4293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4294 typedef union { 4295 struct { 4296 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 0 */ 4297 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 0 */ 4298 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 0 */ 4299 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 0 */ 4300 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 0 */ 4301 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 0 */ 4302 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 0 */ 4303 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 0 */ 4304 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 0 */ 4305 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 0 */ 4306 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 0 */ 4307 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 0 */ 4308 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 0 */ 4309 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 0 */ 4310 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 0 */ 4311 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 0 */ 4312 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 0 */ 4313 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 0 */ 4314 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 0 */ 4315 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 0 */ 4316 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 0 */ 4317 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 0 */ 4318 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 0 */ 4319 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 0 */ 4320 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 0 */ 4321 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 0 */ 4322 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 0 */ 4323 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 0 */ 4324 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 0 */ 4325 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 0 */ 4326 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 0 */ 4327 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 0 */ 4328 } bit; /*!< Structure used for bit access */ 4329 uint32_t reg; /*!< Type used for register access */ 4330 } GPIO_IMR0C_Type; 4331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4332 4333 #define GPIO_IMR0C_OFFSET 0x0A8 /**< \brief (GPIO_IMR0C offset) Interrupt Mode Register 0 - Clear */ 4334 4335 #define GPIO_IMR0C_P0_Pos 0 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4336 #define GPIO_IMR0C_P0 (_U_(0x1) << GPIO_IMR0C_P0_Pos) 4337 #define GPIO_IMR0C_P1_Pos 1 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4338 #define GPIO_IMR0C_P1 (_U_(0x1) << GPIO_IMR0C_P1_Pos) 4339 #define GPIO_IMR0C_P2_Pos 2 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4340 #define GPIO_IMR0C_P2 (_U_(0x1) << GPIO_IMR0C_P2_Pos) 4341 #define GPIO_IMR0C_P3_Pos 3 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4342 #define GPIO_IMR0C_P3 (_U_(0x1) << GPIO_IMR0C_P3_Pos) 4343 #define GPIO_IMR0C_P4_Pos 4 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4344 #define GPIO_IMR0C_P4 (_U_(0x1) << GPIO_IMR0C_P4_Pos) 4345 #define GPIO_IMR0C_P5_Pos 5 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4346 #define GPIO_IMR0C_P5 (_U_(0x1) << GPIO_IMR0C_P5_Pos) 4347 #define GPIO_IMR0C_P6_Pos 6 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4348 #define GPIO_IMR0C_P6 (_U_(0x1) << GPIO_IMR0C_P6_Pos) 4349 #define GPIO_IMR0C_P7_Pos 7 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4350 #define GPIO_IMR0C_P7 (_U_(0x1) << GPIO_IMR0C_P7_Pos) 4351 #define GPIO_IMR0C_P8_Pos 8 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4352 #define GPIO_IMR0C_P8 (_U_(0x1) << GPIO_IMR0C_P8_Pos) 4353 #define GPIO_IMR0C_P9_Pos 9 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4354 #define GPIO_IMR0C_P9 (_U_(0x1) << GPIO_IMR0C_P9_Pos) 4355 #define GPIO_IMR0C_P10_Pos 10 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4356 #define GPIO_IMR0C_P10 (_U_(0x1) << GPIO_IMR0C_P10_Pos) 4357 #define GPIO_IMR0C_P11_Pos 11 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4358 #define GPIO_IMR0C_P11 (_U_(0x1) << GPIO_IMR0C_P11_Pos) 4359 #define GPIO_IMR0C_P12_Pos 12 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4360 #define GPIO_IMR0C_P12 (_U_(0x1) << GPIO_IMR0C_P12_Pos) 4361 #define GPIO_IMR0C_P13_Pos 13 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4362 #define GPIO_IMR0C_P13 (_U_(0x1) << GPIO_IMR0C_P13_Pos) 4363 #define GPIO_IMR0C_P14_Pos 14 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4364 #define GPIO_IMR0C_P14 (_U_(0x1) << GPIO_IMR0C_P14_Pos) 4365 #define GPIO_IMR0C_P15_Pos 15 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4366 #define GPIO_IMR0C_P15 (_U_(0x1) << GPIO_IMR0C_P15_Pos) 4367 #define GPIO_IMR0C_P16_Pos 16 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4368 #define GPIO_IMR0C_P16 (_U_(0x1) << GPIO_IMR0C_P16_Pos) 4369 #define GPIO_IMR0C_P17_Pos 17 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4370 #define GPIO_IMR0C_P17 (_U_(0x1) << GPIO_IMR0C_P17_Pos) 4371 #define GPIO_IMR0C_P18_Pos 18 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4372 #define GPIO_IMR0C_P18 (_U_(0x1) << GPIO_IMR0C_P18_Pos) 4373 #define GPIO_IMR0C_P19_Pos 19 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4374 #define GPIO_IMR0C_P19 (_U_(0x1) << GPIO_IMR0C_P19_Pos) 4375 #define GPIO_IMR0C_P20_Pos 20 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4376 #define GPIO_IMR0C_P20 (_U_(0x1) << GPIO_IMR0C_P20_Pos) 4377 #define GPIO_IMR0C_P21_Pos 21 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4378 #define GPIO_IMR0C_P21 (_U_(0x1) << GPIO_IMR0C_P21_Pos) 4379 #define GPIO_IMR0C_P22_Pos 22 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4380 #define GPIO_IMR0C_P22 (_U_(0x1) << GPIO_IMR0C_P22_Pos) 4381 #define GPIO_IMR0C_P23_Pos 23 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4382 #define GPIO_IMR0C_P23 (_U_(0x1) << GPIO_IMR0C_P23_Pos) 4383 #define GPIO_IMR0C_P24_Pos 24 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4384 #define GPIO_IMR0C_P24 (_U_(0x1) << GPIO_IMR0C_P24_Pos) 4385 #define GPIO_IMR0C_P25_Pos 25 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4386 #define GPIO_IMR0C_P25 (_U_(0x1) << GPIO_IMR0C_P25_Pos) 4387 #define GPIO_IMR0C_P26_Pos 26 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4388 #define GPIO_IMR0C_P26 (_U_(0x1) << GPIO_IMR0C_P26_Pos) 4389 #define GPIO_IMR0C_P27_Pos 27 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4390 #define GPIO_IMR0C_P27 (_U_(0x1) << GPIO_IMR0C_P27_Pos) 4391 #define GPIO_IMR0C_P28_Pos 28 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4392 #define GPIO_IMR0C_P28 (_U_(0x1) << GPIO_IMR0C_P28_Pos) 4393 #define GPIO_IMR0C_P29_Pos 29 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4394 #define GPIO_IMR0C_P29 (_U_(0x1) << GPIO_IMR0C_P29_Pos) 4395 #define GPIO_IMR0C_P30_Pos 30 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4396 #define GPIO_IMR0C_P30 (_U_(0x1) << GPIO_IMR0C_P30_Pos) 4397 #define GPIO_IMR0C_P31_Pos 31 /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */ 4398 #define GPIO_IMR0C_P31 (_U_(0x1) << GPIO_IMR0C_P31_Pos) 4399 #define GPIO_IMR0C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR0C) MASK Register */ 4400 4401 /* -------- GPIO_IMR0T : (GPIO Offset: 0x0AC) ( /W 32) port Interrupt Mode Register 0 - Toggle -------- */ 4402 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4403 typedef union { 4404 struct { 4405 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 0 */ 4406 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 0 */ 4407 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 0 */ 4408 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 0 */ 4409 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 0 */ 4410 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 0 */ 4411 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 0 */ 4412 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 0 */ 4413 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 0 */ 4414 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 0 */ 4415 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 0 */ 4416 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 0 */ 4417 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 0 */ 4418 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 0 */ 4419 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 0 */ 4420 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 0 */ 4421 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 0 */ 4422 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 0 */ 4423 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 0 */ 4424 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 0 */ 4425 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 0 */ 4426 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 0 */ 4427 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 0 */ 4428 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 0 */ 4429 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 0 */ 4430 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 0 */ 4431 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 0 */ 4432 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 0 */ 4433 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 0 */ 4434 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 0 */ 4435 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 0 */ 4436 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 0 */ 4437 } bit; /*!< Structure used for bit access */ 4438 uint32_t reg; /*!< Type used for register access */ 4439 } GPIO_IMR0T_Type; 4440 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4441 4442 #define GPIO_IMR0T_OFFSET 0x0AC /**< \brief (GPIO_IMR0T offset) Interrupt Mode Register 0 - Toggle */ 4443 4444 #define GPIO_IMR0T_P0_Pos 0 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4445 #define GPIO_IMR0T_P0 (_U_(0x1) << GPIO_IMR0T_P0_Pos) 4446 #define GPIO_IMR0T_P1_Pos 1 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4447 #define GPIO_IMR0T_P1 (_U_(0x1) << GPIO_IMR0T_P1_Pos) 4448 #define GPIO_IMR0T_P2_Pos 2 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4449 #define GPIO_IMR0T_P2 (_U_(0x1) << GPIO_IMR0T_P2_Pos) 4450 #define GPIO_IMR0T_P3_Pos 3 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4451 #define GPIO_IMR0T_P3 (_U_(0x1) << GPIO_IMR0T_P3_Pos) 4452 #define GPIO_IMR0T_P4_Pos 4 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4453 #define GPIO_IMR0T_P4 (_U_(0x1) << GPIO_IMR0T_P4_Pos) 4454 #define GPIO_IMR0T_P5_Pos 5 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4455 #define GPIO_IMR0T_P5 (_U_(0x1) << GPIO_IMR0T_P5_Pos) 4456 #define GPIO_IMR0T_P6_Pos 6 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4457 #define GPIO_IMR0T_P6 (_U_(0x1) << GPIO_IMR0T_P6_Pos) 4458 #define GPIO_IMR0T_P7_Pos 7 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4459 #define GPIO_IMR0T_P7 (_U_(0x1) << GPIO_IMR0T_P7_Pos) 4460 #define GPIO_IMR0T_P8_Pos 8 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4461 #define GPIO_IMR0T_P8 (_U_(0x1) << GPIO_IMR0T_P8_Pos) 4462 #define GPIO_IMR0T_P9_Pos 9 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4463 #define GPIO_IMR0T_P9 (_U_(0x1) << GPIO_IMR0T_P9_Pos) 4464 #define GPIO_IMR0T_P10_Pos 10 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4465 #define GPIO_IMR0T_P10 (_U_(0x1) << GPIO_IMR0T_P10_Pos) 4466 #define GPIO_IMR0T_P11_Pos 11 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4467 #define GPIO_IMR0T_P11 (_U_(0x1) << GPIO_IMR0T_P11_Pos) 4468 #define GPIO_IMR0T_P12_Pos 12 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4469 #define GPIO_IMR0T_P12 (_U_(0x1) << GPIO_IMR0T_P12_Pos) 4470 #define GPIO_IMR0T_P13_Pos 13 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4471 #define GPIO_IMR0T_P13 (_U_(0x1) << GPIO_IMR0T_P13_Pos) 4472 #define GPIO_IMR0T_P14_Pos 14 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4473 #define GPIO_IMR0T_P14 (_U_(0x1) << GPIO_IMR0T_P14_Pos) 4474 #define GPIO_IMR0T_P15_Pos 15 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4475 #define GPIO_IMR0T_P15 (_U_(0x1) << GPIO_IMR0T_P15_Pos) 4476 #define GPIO_IMR0T_P16_Pos 16 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4477 #define GPIO_IMR0T_P16 (_U_(0x1) << GPIO_IMR0T_P16_Pos) 4478 #define GPIO_IMR0T_P17_Pos 17 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4479 #define GPIO_IMR0T_P17 (_U_(0x1) << GPIO_IMR0T_P17_Pos) 4480 #define GPIO_IMR0T_P18_Pos 18 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4481 #define GPIO_IMR0T_P18 (_U_(0x1) << GPIO_IMR0T_P18_Pos) 4482 #define GPIO_IMR0T_P19_Pos 19 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4483 #define GPIO_IMR0T_P19 (_U_(0x1) << GPIO_IMR0T_P19_Pos) 4484 #define GPIO_IMR0T_P20_Pos 20 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4485 #define GPIO_IMR0T_P20 (_U_(0x1) << GPIO_IMR0T_P20_Pos) 4486 #define GPIO_IMR0T_P21_Pos 21 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4487 #define GPIO_IMR0T_P21 (_U_(0x1) << GPIO_IMR0T_P21_Pos) 4488 #define GPIO_IMR0T_P22_Pos 22 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4489 #define GPIO_IMR0T_P22 (_U_(0x1) << GPIO_IMR0T_P22_Pos) 4490 #define GPIO_IMR0T_P23_Pos 23 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4491 #define GPIO_IMR0T_P23 (_U_(0x1) << GPIO_IMR0T_P23_Pos) 4492 #define GPIO_IMR0T_P24_Pos 24 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4493 #define GPIO_IMR0T_P24 (_U_(0x1) << GPIO_IMR0T_P24_Pos) 4494 #define GPIO_IMR0T_P25_Pos 25 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4495 #define GPIO_IMR0T_P25 (_U_(0x1) << GPIO_IMR0T_P25_Pos) 4496 #define GPIO_IMR0T_P26_Pos 26 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4497 #define GPIO_IMR0T_P26 (_U_(0x1) << GPIO_IMR0T_P26_Pos) 4498 #define GPIO_IMR0T_P27_Pos 27 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4499 #define GPIO_IMR0T_P27 (_U_(0x1) << GPIO_IMR0T_P27_Pos) 4500 #define GPIO_IMR0T_P28_Pos 28 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4501 #define GPIO_IMR0T_P28 (_U_(0x1) << GPIO_IMR0T_P28_Pos) 4502 #define GPIO_IMR0T_P29_Pos 29 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4503 #define GPIO_IMR0T_P29 (_U_(0x1) << GPIO_IMR0T_P29_Pos) 4504 #define GPIO_IMR0T_P30_Pos 30 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4505 #define GPIO_IMR0T_P30 (_U_(0x1) << GPIO_IMR0T_P30_Pos) 4506 #define GPIO_IMR0T_P31_Pos 31 /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */ 4507 #define GPIO_IMR0T_P31 (_U_(0x1) << GPIO_IMR0T_P31_Pos) 4508 #define GPIO_IMR0T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR0T) MASK Register */ 4509 4510 /* -------- GPIO_IMR1 : (GPIO Offset: 0x0B0) (R/W 32) port Interrupt Mode Register 1 -------- */ 4511 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4512 typedef union { 4513 struct { 4514 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 1 */ 4515 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 1 */ 4516 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 1 */ 4517 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 1 */ 4518 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 1 */ 4519 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 1 */ 4520 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 1 */ 4521 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 1 */ 4522 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 1 */ 4523 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 1 */ 4524 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 1 */ 4525 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 1 */ 4526 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 1 */ 4527 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 1 */ 4528 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 1 */ 4529 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 1 */ 4530 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 1 */ 4531 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 1 */ 4532 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 1 */ 4533 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 1 */ 4534 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 1 */ 4535 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 1 */ 4536 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 1 */ 4537 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 1 */ 4538 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 1 */ 4539 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 1 */ 4540 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 1 */ 4541 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 1 */ 4542 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 1 */ 4543 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 1 */ 4544 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 1 */ 4545 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 1 */ 4546 } bit; /*!< Structure used for bit access */ 4547 uint32_t reg; /*!< Type used for register access */ 4548 } GPIO_IMR1_Type; 4549 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4550 4551 #define GPIO_IMR1_OFFSET 0x0B0 /**< \brief (GPIO_IMR1 offset) Interrupt Mode Register 1 */ 4552 4553 #define GPIO_IMR1_P0_Pos 0 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4554 #define GPIO_IMR1_P0 (_U_(0x1) << GPIO_IMR1_P0_Pos) 4555 #define GPIO_IMR1_P1_Pos 1 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4556 #define GPIO_IMR1_P1 (_U_(0x1) << GPIO_IMR1_P1_Pos) 4557 #define GPIO_IMR1_P2_Pos 2 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4558 #define GPIO_IMR1_P2 (_U_(0x1) << GPIO_IMR1_P2_Pos) 4559 #define GPIO_IMR1_P3_Pos 3 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4560 #define GPIO_IMR1_P3 (_U_(0x1) << GPIO_IMR1_P3_Pos) 4561 #define GPIO_IMR1_P4_Pos 4 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4562 #define GPIO_IMR1_P4 (_U_(0x1) << GPIO_IMR1_P4_Pos) 4563 #define GPIO_IMR1_P5_Pos 5 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4564 #define GPIO_IMR1_P5 (_U_(0x1) << GPIO_IMR1_P5_Pos) 4565 #define GPIO_IMR1_P6_Pos 6 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4566 #define GPIO_IMR1_P6 (_U_(0x1) << GPIO_IMR1_P6_Pos) 4567 #define GPIO_IMR1_P7_Pos 7 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4568 #define GPIO_IMR1_P7 (_U_(0x1) << GPIO_IMR1_P7_Pos) 4569 #define GPIO_IMR1_P8_Pos 8 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4570 #define GPIO_IMR1_P8 (_U_(0x1) << GPIO_IMR1_P8_Pos) 4571 #define GPIO_IMR1_P9_Pos 9 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4572 #define GPIO_IMR1_P9 (_U_(0x1) << GPIO_IMR1_P9_Pos) 4573 #define GPIO_IMR1_P10_Pos 10 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4574 #define GPIO_IMR1_P10 (_U_(0x1) << GPIO_IMR1_P10_Pos) 4575 #define GPIO_IMR1_P11_Pos 11 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4576 #define GPIO_IMR1_P11 (_U_(0x1) << GPIO_IMR1_P11_Pos) 4577 #define GPIO_IMR1_P12_Pos 12 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4578 #define GPIO_IMR1_P12 (_U_(0x1) << GPIO_IMR1_P12_Pos) 4579 #define GPIO_IMR1_P13_Pos 13 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4580 #define GPIO_IMR1_P13 (_U_(0x1) << GPIO_IMR1_P13_Pos) 4581 #define GPIO_IMR1_P14_Pos 14 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4582 #define GPIO_IMR1_P14 (_U_(0x1) << GPIO_IMR1_P14_Pos) 4583 #define GPIO_IMR1_P15_Pos 15 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4584 #define GPIO_IMR1_P15 (_U_(0x1) << GPIO_IMR1_P15_Pos) 4585 #define GPIO_IMR1_P16_Pos 16 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4586 #define GPIO_IMR1_P16 (_U_(0x1) << GPIO_IMR1_P16_Pos) 4587 #define GPIO_IMR1_P17_Pos 17 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4588 #define GPIO_IMR1_P17 (_U_(0x1) << GPIO_IMR1_P17_Pos) 4589 #define GPIO_IMR1_P18_Pos 18 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4590 #define GPIO_IMR1_P18 (_U_(0x1) << GPIO_IMR1_P18_Pos) 4591 #define GPIO_IMR1_P19_Pos 19 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4592 #define GPIO_IMR1_P19 (_U_(0x1) << GPIO_IMR1_P19_Pos) 4593 #define GPIO_IMR1_P20_Pos 20 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4594 #define GPIO_IMR1_P20 (_U_(0x1) << GPIO_IMR1_P20_Pos) 4595 #define GPIO_IMR1_P21_Pos 21 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4596 #define GPIO_IMR1_P21 (_U_(0x1) << GPIO_IMR1_P21_Pos) 4597 #define GPIO_IMR1_P22_Pos 22 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4598 #define GPIO_IMR1_P22 (_U_(0x1) << GPIO_IMR1_P22_Pos) 4599 #define GPIO_IMR1_P23_Pos 23 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4600 #define GPIO_IMR1_P23 (_U_(0x1) << GPIO_IMR1_P23_Pos) 4601 #define GPIO_IMR1_P24_Pos 24 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4602 #define GPIO_IMR1_P24 (_U_(0x1) << GPIO_IMR1_P24_Pos) 4603 #define GPIO_IMR1_P25_Pos 25 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4604 #define GPIO_IMR1_P25 (_U_(0x1) << GPIO_IMR1_P25_Pos) 4605 #define GPIO_IMR1_P26_Pos 26 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4606 #define GPIO_IMR1_P26 (_U_(0x1) << GPIO_IMR1_P26_Pos) 4607 #define GPIO_IMR1_P27_Pos 27 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4608 #define GPIO_IMR1_P27 (_U_(0x1) << GPIO_IMR1_P27_Pos) 4609 #define GPIO_IMR1_P28_Pos 28 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4610 #define GPIO_IMR1_P28 (_U_(0x1) << GPIO_IMR1_P28_Pos) 4611 #define GPIO_IMR1_P29_Pos 29 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4612 #define GPIO_IMR1_P29 (_U_(0x1) << GPIO_IMR1_P29_Pos) 4613 #define GPIO_IMR1_P30_Pos 30 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4614 #define GPIO_IMR1_P30 (_U_(0x1) << GPIO_IMR1_P30_Pos) 4615 #define GPIO_IMR1_P31_Pos 31 /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */ 4616 #define GPIO_IMR1_P31 (_U_(0x1) << GPIO_IMR1_P31_Pos) 4617 #define GPIO_IMR1_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR1) MASK Register */ 4618 4619 /* -------- GPIO_IMR1S : (GPIO Offset: 0x0B4) ( /W 32) port Interrupt Mode Register 1 - Set -------- */ 4620 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4621 typedef union { 4622 struct { 4623 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 1 */ 4624 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 1 */ 4625 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 1 */ 4626 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 1 */ 4627 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 1 */ 4628 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 1 */ 4629 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 1 */ 4630 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 1 */ 4631 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 1 */ 4632 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 1 */ 4633 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 1 */ 4634 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 1 */ 4635 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 1 */ 4636 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 1 */ 4637 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 1 */ 4638 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 1 */ 4639 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 1 */ 4640 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 1 */ 4641 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 1 */ 4642 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 1 */ 4643 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 1 */ 4644 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 1 */ 4645 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 1 */ 4646 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 1 */ 4647 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 1 */ 4648 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 1 */ 4649 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 1 */ 4650 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 1 */ 4651 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 1 */ 4652 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 1 */ 4653 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 1 */ 4654 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 1 */ 4655 } bit; /*!< Structure used for bit access */ 4656 uint32_t reg; /*!< Type used for register access */ 4657 } GPIO_IMR1S_Type; 4658 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4659 4660 #define GPIO_IMR1S_OFFSET 0x0B4 /**< \brief (GPIO_IMR1S offset) Interrupt Mode Register 1 - Set */ 4661 4662 #define GPIO_IMR1S_P0_Pos 0 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4663 #define GPIO_IMR1S_P0 (_U_(0x1) << GPIO_IMR1S_P0_Pos) 4664 #define GPIO_IMR1S_P1_Pos 1 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4665 #define GPIO_IMR1S_P1 (_U_(0x1) << GPIO_IMR1S_P1_Pos) 4666 #define GPIO_IMR1S_P2_Pos 2 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4667 #define GPIO_IMR1S_P2 (_U_(0x1) << GPIO_IMR1S_P2_Pos) 4668 #define GPIO_IMR1S_P3_Pos 3 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4669 #define GPIO_IMR1S_P3 (_U_(0x1) << GPIO_IMR1S_P3_Pos) 4670 #define GPIO_IMR1S_P4_Pos 4 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4671 #define GPIO_IMR1S_P4 (_U_(0x1) << GPIO_IMR1S_P4_Pos) 4672 #define GPIO_IMR1S_P5_Pos 5 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4673 #define GPIO_IMR1S_P5 (_U_(0x1) << GPIO_IMR1S_P5_Pos) 4674 #define GPIO_IMR1S_P6_Pos 6 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4675 #define GPIO_IMR1S_P6 (_U_(0x1) << GPIO_IMR1S_P6_Pos) 4676 #define GPIO_IMR1S_P7_Pos 7 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4677 #define GPIO_IMR1S_P7 (_U_(0x1) << GPIO_IMR1S_P7_Pos) 4678 #define GPIO_IMR1S_P8_Pos 8 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4679 #define GPIO_IMR1S_P8 (_U_(0x1) << GPIO_IMR1S_P8_Pos) 4680 #define GPIO_IMR1S_P9_Pos 9 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4681 #define GPIO_IMR1S_P9 (_U_(0x1) << GPIO_IMR1S_P9_Pos) 4682 #define GPIO_IMR1S_P10_Pos 10 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4683 #define GPIO_IMR1S_P10 (_U_(0x1) << GPIO_IMR1S_P10_Pos) 4684 #define GPIO_IMR1S_P11_Pos 11 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4685 #define GPIO_IMR1S_P11 (_U_(0x1) << GPIO_IMR1S_P11_Pos) 4686 #define GPIO_IMR1S_P12_Pos 12 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4687 #define GPIO_IMR1S_P12 (_U_(0x1) << GPIO_IMR1S_P12_Pos) 4688 #define GPIO_IMR1S_P13_Pos 13 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4689 #define GPIO_IMR1S_P13 (_U_(0x1) << GPIO_IMR1S_P13_Pos) 4690 #define GPIO_IMR1S_P14_Pos 14 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4691 #define GPIO_IMR1S_P14 (_U_(0x1) << GPIO_IMR1S_P14_Pos) 4692 #define GPIO_IMR1S_P15_Pos 15 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4693 #define GPIO_IMR1S_P15 (_U_(0x1) << GPIO_IMR1S_P15_Pos) 4694 #define GPIO_IMR1S_P16_Pos 16 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4695 #define GPIO_IMR1S_P16 (_U_(0x1) << GPIO_IMR1S_P16_Pos) 4696 #define GPIO_IMR1S_P17_Pos 17 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4697 #define GPIO_IMR1S_P17 (_U_(0x1) << GPIO_IMR1S_P17_Pos) 4698 #define GPIO_IMR1S_P18_Pos 18 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4699 #define GPIO_IMR1S_P18 (_U_(0x1) << GPIO_IMR1S_P18_Pos) 4700 #define GPIO_IMR1S_P19_Pos 19 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4701 #define GPIO_IMR1S_P19 (_U_(0x1) << GPIO_IMR1S_P19_Pos) 4702 #define GPIO_IMR1S_P20_Pos 20 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4703 #define GPIO_IMR1S_P20 (_U_(0x1) << GPIO_IMR1S_P20_Pos) 4704 #define GPIO_IMR1S_P21_Pos 21 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4705 #define GPIO_IMR1S_P21 (_U_(0x1) << GPIO_IMR1S_P21_Pos) 4706 #define GPIO_IMR1S_P22_Pos 22 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4707 #define GPIO_IMR1S_P22 (_U_(0x1) << GPIO_IMR1S_P22_Pos) 4708 #define GPIO_IMR1S_P23_Pos 23 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4709 #define GPIO_IMR1S_P23 (_U_(0x1) << GPIO_IMR1S_P23_Pos) 4710 #define GPIO_IMR1S_P24_Pos 24 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4711 #define GPIO_IMR1S_P24 (_U_(0x1) << GPIO_IMR1S_P24_Pos) 4712 #define GPIO_IMR1S_P25_Pos 25 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4713 #define GPIO_IMR1S_P25 (_U_(0x1) << GPIO_IMR1S_P25_Pos) 4714 #define GPIO_IMR1S_P26_Pos 26 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4715 #define GPIO_IMR1S_P26 (_U_(0x1) << GPIO_IMR1S_P26_Pos) 4716 #define GPIO_IMR1S_P27_Pos 27 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4717 #define GPIO_IMR1S_P27 (_U_(0x1) << GPIO_IMR1S_P27_Pos) 4718 #define GPIO_IMR1S_P28_Pos 28 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4719 #define GPIO_IMR1S_P28 (_U_(0x1) << GPIO_IMR1S_P28_Pos) 4720 #define GPIO_IMR1S_P29_Pos 29 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4721 #define GPIO_IMR1S_P29 (_U_(0x1) << GPIO_IMR1S_P29_Pos) 4722 #define GPIO_IMR1S_P30_Pos 30 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4723 #define GPIO_IMR1S_P30 (_U_(0x1) << GPIO_IMR1S_P30_Pos) 4724 #define GPIO_IMR1S_P31_Pos 31 /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */ 4725 #define GPIO_IMR1S_P31 (_U_(0x1) << GPIO_IMR1S_P31_Pos) 4726 #define GPIO_IMR1S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR1S) MASK Register */ 4727 4728 /* -------- GPIO_IMR1C : (GPIO Offset: 0x0B8) ( /W 32) port Interrupt Mode Register 1 - Clear -------- */ 4729 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4730 typedef union { 4731 struct { 4732 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 1 */ 4733 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 1 */ 4734 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 1 */ 4735 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 1 */ 4736 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 1 */ 4737 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 1 */ 4738 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 1 */ 4739 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 1 */ 4740 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 1 */ 4741 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 1 */ 4742 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 1 */ 4743 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 1 */ 4744 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 1 */ 4745 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 1 */ 4746 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 1 */ 4747 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 1 */ 4748 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 1 */ 4749 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 1 */ 4750 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 1 */ 4751 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 1 */ 4752 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 1 */ 4753 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 1 */ 4754 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 1 */ 4755 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 1 */ 4756 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 1 */ 4757 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 1 */ 4758 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 1 */ 4759 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 1 */ 4760 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 1 */ 4761 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 1 */ 4762 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 1 */ 4763 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 1 */ 4764 } bit; /*!< Structure used for bit access */ 4765 uint32_t reg; /*!< Type used for register access */ 4766 } GPIO_IMR1C_Type; 4767 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4768 4769 #define GPIO_IMR1C_OFFSET 0x0B8 /**< \brief (GPIO_IMR1C offset) Interrupt Mode Register 1 - Clear */ 4770 4771 #define GPIO_IMR1C_P0_Pos 0 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4772 #define GPIO_IMR1C_P0 (_U_(0x1) << GPIO_IMR1C_P0_Pos) 4773 #define GPIO_IMR1C_P1_Pos 1 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4774 #define GPIO_IMR1C_P1 (_U_(0x1) << GPIO_IMR1C_P1_Pos) 4775 #define GPIO_IMR1C_P2_Pos 2 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4776 #define GPIO_IMR1C_P2 (_U_(0x1) << GPIO_IMR1C_P2_Pos) 4777 #define GPIO_IMR1C_P3_Pos 3 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4778 #define GPIO_IMR1C_P3 (_U_(0x1) << GPIO_IMR1C_P3_Pos) 4779 #define GPIO_IMR1C_P4_Pos 4 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4780 #define GPIO_IMR1C_P4 (_U_(0x1) << GPIO_IMR1C_P4_Pos) 4781 #define GPIO_IMR1C_P5_Pos 5 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4782 #define GPIO_IMR1C_P5 (_U_(0x1) << GPIO_IMR1C_P5_Pos) 4783 #define GPIO_IMR1C_P6_Pos 6 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4784 #define GPIO_IMR1C_P6 (_U_(0x1) << GPIO_IMR1C_P6_Pos) 4785 #define GPIO_IMR1C_P7_Pos 7 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4786 #define GPIO_IMR1C_P7 (_U_(0x1) << GPIO_IMR1C_P7_Pos) 4787 #define GPIO_IMR1C_P8_Pos 8 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4788 #define GPIO_IMR1C_P8 (_U_(0x1) << GPIO_IMR1C_P8_Pos) 4789 #define GPIO_IMR1C_P9_Pos 9 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4790 #define GPIO_IMR1C_P9 (_U_(0x1) << GPIO_IMR1C_P9_Pos) 4791 #define GPIO_IMR1C_P10_Pos 10 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4792 #define GPIO_IMR1C_P10 (_U_(0x1) << GPIO_IMR1C_P10_Pos) 4793 #define GPIO_IMR1C_P11_Pos 11 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4794 #define GPIO_IMR1C_P11 (_U_(0x1) << GPIO_IMR1C_P11_Pos) 4795 #define GPIO_IMR1C_P12_Pos 12 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4796 #define GPIO_IMR1C_P12 (_U_(0x1) << GPIO_IMR1C_P12_Pos) 4797 #define GPIO_IMR1C_P13_Pos 13 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4798 #define GPIO_IMR1C_P13 (_U_(0x1) << GPIO_IMR1C_P13_Pos) 4799 #define GPIO_IMR1C_P14_Pos 14 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4800 #define GPIO_IMR1C_P14 (_U_(0x1) << GPIO_IMR1C_P14_Pos) 4801 #define GPIO_IMR1C_P15_Pos 15 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4802 #define GPIO_IMR1C_P15 (_U_(0x1) << GPIO_IMR1C_P15_Pos) 4803 #define GPIO_IMR1C_P16_Pos 16 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4804 #define GPIO_IMR1C_P16 (_U_(0x1) << GPIO_IMR1C_P16_Pos) 4805 #define GPIO_IMR1C_P17_Pos 17 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4806 #define GPIO_IMR1C_P17 (_U_(0x1) << GPIO_IMR1C_P17_Pos) 4807 #define GPIO_IMR1C_P18_Pos 18 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4808 #define GPIO_IMR1C_P18 (_U_(0x1) << GPIO_IMR1C_P18_Pos) 4809 #define GPIO_IMR1C_P19_Pos 19 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4810 #define GPIO_IMR1C_P19 (_U_(0x1) << GPIO_IMR1C_P19_Pos) 4811 #define GPIO_IMR1C_P20_Pos 20 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4812 #define GPIO_IMR1C_P20 (_U_(0x1) << GPIO_IMR1C_P20_Pos) 4813 #define GPIO_IMR1C_P21_Pos 21 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4814 #define GPIO_IMR1C_P21 (_U_(0x1) << GPIO_IMR1C_P21_Pos) 4815 #define GPIO_IMR1C_P22_Pos 22 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4816 #define GPIO_IMR1C_P22 (_U_(0x1) << GPIO_IMR1C_P22_Pos) 4817 #define GPIO_IMR1C_P23_Pos 23 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4818 #define GPIO_IMR1C_P23 (_U_(0x1) << GPIO_IMR1C_P23_Pos) 4819 #define GPIO_IMR1C_P24_Pos 24 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4820 #define GPIO_IMR1C_P24 (_U_(0x1) << GPIO_IMR1C_P24_Pos) 4821 #define GPIO_IMR1C_P25_Pos 25 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4822 #define GPIO_IMR1C_P25 (_U_(0x1) << GPIO_IMR1C_P25_Pos) 4823 #define GPIO_IMR1C_P26_Pos 26 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4824 #define GPIO_IMR1C_P26 (_U_(0x1) << GPIO_IMR1C_P26_Pos) 4825 #define GPIO_IMR1C_P27_Pos 27 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4826 #define GPIO_IMR1C_P27 (_U_(0x1) << GPIO_IMR1C_P27_Pos) 4827 #define GPIO_IMR1C_P28_Pos 28 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4828 #define GPIO_IMR1C_P28 (_U_(0x1) << GPIO_IMR1C_P28_Pos) 4829 #define GPIO_IMR1C_P29_Pos 29 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4830 #define GPIO_IMR1C_P29 (_U_(0x1) << GPIO_IMR1C_P29_Pos) 4831 #define GPIO_IMR1C_P30_Pos 30 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4832 #define GPIO_IMR1C_P30 (_U_(0x1) << GPIO_IMR1C_P30_Pos) 4833 #define GPIO_IMR1C_P31_Pos 31 /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */ 4834 #define GPIO_IMR1C_P31 (_U_(0x1) << GPIO_IMR1C_P31_Pos) 4835 #define GPIO_IMR1C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR1C) MASK Register */ 4836 4837 /* -------- GPIO_IMR1T : (GPIO Offset: 0x0BC) ( /W 32) port Interrupt Mode Register 1 - Toggle -------- */ 4838 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4839 typedef union { 4840 struct { 4841 uint32_t P0:1; /*!< bit: 0 Interrupt Mode Bit 1 */ 4842 uint32_t P1:1; /*!< bit: 1 Interrupt Mode Bit 1 */ 4843 uint32_t P2:1; /*!< bit: 2 Interrupt Mode Bit 1 */ 4844 uint32_t P3:1; /*!< bit: 3 Interrupt Mode Bit 1 */ 4845 uint32_t P4:1; /*!< bit: 4 Interrupt Mode Bit 1 */ 4846 uint32_t P5:1; /*!< bit: 5 Interrupt Mode Bit 1 */ 4847 uint32_t P6:1; /*!< bit: 6 Interrupt Mode Bit 1 */ 4848 uint32_t P7:1; /*!< bit: 7 Interrupt Mode Bit 1 */ 4849 uint32_t P8:1; /*!< bit: 8 Interrupt Mode Bit 1 */ 4850 uint32_t P9:1; /*!< bit: 9 Interrupt Mode Bit 1 */ 4851 uint32_t P10:1; /*!< bit: 10 Interrupt Mode Bit 1 */ 4852 uint32_t P11:1; /*!< bit: 11 Interrupt Mode Bit 1 */ 4853 uint32_t P12:1; /*!< bit: 12 Interrupt Mode Bit 1 */ 4854 uint32_t P13:1; /*!< bit: 13 Interrupt Mode Bit 1 */ 4855 uint32_t P14:1; /*!< bit: 14 Interrupt Mode Bit 1 */ 4856 uint32_t P15:1; /*!< bit: 15 Interrupt Mode Bit 1 */ 4857 uint32_t P16:1; /*!< bit: 16 Interrupt Mode Bit 1 */ 4858 uint32_t P17:1; /*!< bit: 17 Interrupt Mode Bit 1 */ 4859 uint32_t P18:1; /*!< bit: 18 Interrupt Mode Bit 1 */ 4860 uint32_t P19:1; /*!< bit: 19 Interrupt Mode Bit 1 */ 4861 uint32_t P20:1; /*!< bit: 20 Interrupt Mode Bit 1 */ 4862 uint32_t P21:1; /*!< bit: 21 Interrupt Mode Bit 1 */ 4863 uint32_t P22:1; /*!< bit: 22 Interrupt Mode Bit 1 */ 4864 uint32_t P23:1; /*!< bit: 23 Interrupt Mode Bit 1 */ 4865 uint32_t P24:1; /*!< bit: 24 Interrupt Mode Bit 1 */ 4866 uint32_t P25:1; /*!< bit: 25 Interrupt Mode Bit 1 */ 4867 uint32_t P26:1; /*!< bit: 26 Interrupt Mode Bit 1 */ 4868 uint32_t P27:1; /*!< bit: 27 Interrupt Mode Bit 1 */ 4869 uint32_t P28:1; /*!< bit: 28 Interrupt Mode Bit 1 */ 4870 uint32_t P29:1; /*!< bit: 29 Interrupt Mode Bit 1 */ 4871 uint32_t P30:1; /*!< bit: 30 Interrupt Mode Bit 1 */ 4872 uint32_t P31:1; /*!< bit: 31 Interrupt Mode Bit 1 */ 4873 } bit; /*!< Structure used for bit access */ 4874 uint32_t reg; /*!< Type used for register access */ 4875 } GPIO_IMR1T_Type; 4876 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4877 4878 #define GPIO_IMR1T_OFFSET 0x0BC /**< \brief (GPIO_IMR1T offset) Interrupt Mode Register 1 - Toggle */ 4879 4880 #define GPIO_IMR1T_P0_Pos 0 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4881 #define GPIO_IMR1T_P0 (_U_(0x1) << GPIO_IMR1T_P0_Pos) 4882 #define GPIO_IMR1T_P1_Pos 1 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4883 #define GPIO_IMR1T_P1 (_U_(0x1) << GPIO_IMR1T_P1_Pos) 4884 #define GPIO_IMR1T_P2_Pos 2 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4885 #define GPIO_IMR1T_P2 (_U_(0x1) << GPIO_IMR1T_P2_Pos) 4886 #define GPIO_IMR1T_P3_Pos 3 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4887 #define GPIO_IMR1T_P3 (_U_(0x1) << GPIO_IMR1T_P3_Pos) 4888 #define GPIO_IMR1T_P4_Pos 4 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4889 #define GPIO_IMR1T_P4 (_U_(0x1) << GPIO_IMR1T_P4_Pos) 4890 #define GPIO_IMR1T_P5_Pos 5 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4891 #define GPIO_IMR1T_P5 (_U_(0x1) << GPIO_IMR1T_P5_Pos) 4892 #define GPIO_IMR1T_P6_Pos 6 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4893 #define GPIO_IMR1T_P6 (_U_(0x1) << GPIO_IMR1T_P6_Pos) 4894 #define GPIO_IMR1T_P7_Pos 7 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4895 #define GPIO_IMR1T_P7 (_U_(0x1) << GPIO_IMR1T_P7_Pos) 4896 #define GPIO_IMR1T_P8_Pos 8 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4897 #define GPIO_IMR1T_P8 (_U_(0x1) << GPIO_IMR1T_P8_Pos) 4898 #define GPIO_IMR1T_P9_Pos 9 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4899 #define GPIO_IMR1T_P9 (_U_(0x1) << GPIO_IMR1T_P9_Pos) 4900 #define GPIO_IMR1T_P10_Pos 10 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4901 #define GPIO_IMR1T_P10 (_U_(0x1) << GPIO_IMR1T_P10_Pos) 4902 #define GPIO_IMR1T_P11_Pos 11 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4903 #define GPIO_IMR1T_P11 (_U_(0x1) << GPIO_IMR1T_P11_Pos) 4904 #define GPIO_IMR1T_P12_Pos 12 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4905 #define GPIO_IMR1T_P12 (_U_(0x1) << GPIO_IMR1T_P12_Pos) 4906 #define GPIO_IMR1T_P13_Pos 13 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4907 #define GPIO_IMR1T_P13 (_U_(0x1) << GPIO_IMR1T_P13_Pos) 4908 #define GPIO_IMR1T_P14_Pos 14 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4909 #define GPIO_IMR1T_P14 (_U_(0x1) << GPIO_IMR1T_P14_Pos) 4910 #define GPIO_IMR1T_P15_Pos 15 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4911 #define GPIO_IMR1T_P15 (_U_(0x1) << GPIO_IMR1T_P15_Pos) 4912 #define GPIO_IMR1T_P16_Pos 16 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4913 #define GPIO_IMR1T_P16 (_U_(0x1) << GPIO_IMR1T_P16_Pos) 4914 #define GPIO_IMR1T_P17_Pos 17 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4915 #define GPIO_IMR1T_P17 (_U_(0x1) << GPIO_IMR1T_P17_Pos) 4916 #define GPIO_IMR1T_P18_Pos 18 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4917 #define GPIO_IMR1T_P18 (_U_(0x1) << GPIO_IMR1T_P18_Pos) 4918 #define GPIO_IMR1T_P19_Pos 19 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4919 #define GPIO_IMR1T_P19 (_U_(0x1) << GPIO_IMR1T_P19_Pos) 4920 #define GPIO_IMR1T_P20_Pos 20 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4921 #define GPIO_IMR1T_P20 (_U_(0x1) << GPIO_IMR1T_P20_Pos) 4922 #define GPIO_IMR1T_P21_Pos 21 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4923 #define GPIO_IMR1T_P21 (_U_(0x1) << GPIO_IMR1T_P21_Pos) 4924 #define GPIO_IMR1T_P22_Pos 22 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4925 #define GPIO_IMR1T_P22 (_U_(0x1) << GPIO_IMR1T_P22_Pos) 4926 #define GPIO_IMR1T_P23_Pos 23 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4927 #define GPIO_IMR1T_P23 (_U_(0x1) << GPIO_IMR1T_P23_Pos) 4928 #define GPIO_IMR1T_P24_Pos 24 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4929 #define GPIO_IMR1T_P24 (_U_(0x1) << GPIO_IMR1T_P24_Pos) 4930 #define GPIO_IMR1T_P25_Pos 25 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4931 #define GPIO_IMR1T_P25 (_U_(0x1) << GPIO_IMR1T_P25_Pos) 4932 #define GPIO_IMR1T_P26_Pos 26 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4933 #define GPIO_IMR1T_P26 (_U_(0x1) << GPIO_IMR1T_P26_Pos) 4934 #define GPIO_IMR1T_P27_Pos 27 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4935 #define GPIO_IMR1T_P27 (_U_(0x1) << GPIO_IMR1T_P27_Pos) 4936 #define GPIO_IMR1T_P28_Pos 28 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4937 #define GPIO_IMR1T_P28 (_U_(0x1) << GPIO_IMR1T_P28_Pos) 4938 #define GPIO_IMR1T_P29_Pos 29 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4939 #define GPIO_IMR1T_P29 (_U_(0x1) << GPIO_IMR1T_P29_Pos) 4940 #define GPIO_IMR1T_P30_Pos 30 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4941 #define GPIO_IMR1T_P30 (_U_(0x1) << GPIO_IMR1T_P30_Pos) 4942 #define GPIO_IMR1T_P31_Pos 31 /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */ 4943 #define GPIO_IMR1T_P31 (_U_(0x1) << GPIO_IMR1T_P31_Pos) 4944 #define GPIO_IMR1T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IMR1T) MASK Register */ 4945 4946 /* -------- GPIO_GFER : (GPIO Offset: 0x0C0) (R/W 32) port Glitch Filter Enable Register -------- */ 4947 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4948 typedef union { 4949 struct { 4950 uint32_t P0:1; /*!< bit: 0 Glitch Filter Enable */ 4951 uint32_t P1:1; /*!< bit: 1 Glitch Filter Enable */ 4952 uint32_t P2:1; /*!< bit: 2 Glitch Filter Enable */ 4953 uint32_t P3:1; /*!< bit: 3 Glitch Filter Enable */ 4954 uint32_t P4:1; /*!< bit: 4 Glitch Filter Enable */ 4955 uint32_t P5:1; /*!< bit: 5 Glitch Filter Enable */ 4956 uint32_t P6:1; /*!< bit: 6 Glitch Filter Enable */ 4957 uint32_t P7:1; /*!< bit: 7 Glitch Filter Enable */ 4958 uint32_t P8:1; /*!< bit: 8 Glitch Filter Enable */ 4959 uint32_t P9:1; /*!< bit: 9 Glitch Filter Enable */ 4960 uint32_t P10:1; /*!< bit: 10 Glitch Filter Enable */ 4961 uint32_t P11:1; /*!< bit: 11 Glitch Filter Enable */ 4962 uint32_t P12:1; /*!< bit: 12 Glitch Filter Enable */ 4963 uint32_t P13:1; /*!< bit: 13 Glitch Filter Enable */ 4964 uint32_t P14:1; /*!< bit: 14 Glitch Filter Enable */ 4965 uint32_t P15:1; /*!< bit: 15 Glitch Filter Enable */ 4966 uint32_t P16:1; /*!< bit: 16 Glitch Filter Enable */ 4967 uint32_t P17:1; /*!< bit: 17 Glitch Filter Enable */ 4968 uint32_t P18:1; /*!< bit: 18 Glitch Filter Enable */ 4969 uint32_t P19:1; /*!< bit: 19 Glitch Filter Enable */ 4970 uint32_t P20:1; /*!< bit: 20 Glitch Filter Enable */ 4971 uint32_t P21:1; /*!< bit: 21 Glitch Filter Enable */ 4972 uint32_t P22:1; /*!< bit: 22 Glitch Filter Enable */ 4973 uint32_t P23:1; /*!< bit: 23 Glitch Filter Enable */ 4974 uint32_t P24:1; /*!< bit: 24 Glitch Filter Enable */ 4975 uint32_t P25:1; /*!< bit: 25 Glitch Filter Enable */ 4976 uint32_t P26:1; /*!< bit: 26 Glitch Filter Enable */ 4977 uint32_t P27:1; /*!< bit: 27 Glitch Filter Enable */ 4978 uint32_t P28:1; /*!< bit: 28 Glitch Filter Enable */ 4979 uint32_t P29:1; /*!< bit: 29 Glitch Filter Enable */ 4980 uint32_t P30:1; /*!< bit: 30 Glitch Filter Enable */ 4981 uint32_t P31:1; /*!< bit: 31 Glitch Filter Enable */ 4982 } bit; /*!< Structure used for bit access */ 4983 uint32_t reg; /*!< Type used for register access */ 4984 } GPIO_GFER_Type; 4985 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4986 4987 #define GPIO_GFER_OFFSET 0x0C0 /**< \brief (GPIO_GFER offset) Glitch Filter Enable Register */ 4988 4989 #define GPIO_GFER_P0_Pos 0 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 4990 #define GPIO_GFER_P0 (_U_(0x1) << GPIO_GFER_P0_Pos) 4991 #define GPIO_GFER_P1_Pos 1 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 4992 #define GPIO_GFER_P1 (_U_(0x1) << GPIO_GFER_P1_Pos) 4993 #define GPIO_GFER_P2_Pos 2 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 4994 #define GPIO_GFER_P2 (_U_(0x1) << GPIO_GFER_P2_Pos) 4995 #define GPIO_GFER_P3_Pos 3 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 4996 #define GPIO_GFER_P3 (_U_(0x1) << GPIO_GFER_P3_Pos) 4997 #define GPIO_GFER_P4_Pos 4 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 4998 #define GPIO_GFER_P4 (_U_(0x1) << GPIO_GFER_P4_Pos) 4999 #define GPIO_GFER_P5_Pos 5 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5000 #define GPIO_GFER_P5 (_U_(0x1) << GPIO_GFER_P5_Pos) 5001 #define GPIO_GFER_P6_Pos 6 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5002 #define GPIO_GFER_P6 (_U_(0x1) << GPIO_GFER_P6_Pos) 5003 #define GPIO_GFER_P7_Pos 7 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5004 #define GPIO_GFER_P7 (_U_(0x1) << GPIO_GFER_P7_Pos) 5005 #define GPIO_GFER_P8_Pos 8 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5006 #define GPIO_GFER_P8 (_U_(0x1) << GPIO_GFER_P8_Pos) 5007 #define GPIO_GFER_P9_Pos 9 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5008 #define GPIO_GFER_P9 (_U_(0x1) << GPIO_GFER_P9_Pos) 5009 #define GPIO_GFER_P10_Pos 10 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5010 #define GPIO_GFER_P10 (_U_(0x1) << GPIO_GFER_P10_Pos) 5011 #define GPIO_GFER_P11_Pos 11 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5012 #define GPIO_GFER_P11 (_U_(0x1) << GPIO_GFER_P11_Pos) 5013 #define GPIO_GFER_P12_Pos 12 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5014 #define GPIO_GFER_P12 (_U_(0x1) << GPIO_GFER_P12_Pos) 5015 #define GPIO_GFER_P13_Pos 13 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5016 #define GPIO_GFER_P13 (_U_(0x1) << GPIO_GFER_P13_Pos) 5017 #define GPIO_GFER_P14_Pos 14 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5018 #define GPIO_GFER_P14 (_U_(0x1) << GPIO_GFER_P14_Pos) 5019 #define GPIO_GFER_P15_Pos 15 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5020 #define GPIO_GFER_P15 (_U_(0x1) << GPIO_GFER_P15_Pos) 5021 #define GPIO_GFER_P16_Pos 16 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5022 #define GPIO_GFER_P16 (_U_(0x1) << GPIO_GFER_P16_Pos) 5023 #define GPIO_GFER_P17_Pos 17 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5024 #define GPIO_GFER_P17 (_U_(0x1) << GPIO_GFER_P17_Pos) 5025 #define GPIO_GFER_P18_Pos 18 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5026 #define GPIO_GFER_P18 (_U_(0x1) << GPIO_GFER_P18_Pos) 5027 #define GPIO_GFER_P19_Pos 19 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5028 #define GPIO_GFER_P19 (_U_(0x1) << GPIO_GFER_P19_Pos) 5029 #define GPIO_GFER_P20_Pos 20 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5030 #define GPIO_GFER_P20 (_U_(0x1) << GPIO_GFER_P20_Pos) 5031 #define GPIO_GFER_P21_Pos 21 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5032 #define GPIO_GFER_P21 (_U_(0x1) << GPIO_GFER_P21_Pos) 5033 #define GPIO_GFER_P22_Pos 22 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5034 #define GPIO_GFER_P22 (_U_(0x1) << GPIO_GFER_P22_Pos) 5035 #define GPIO_GFER_P23_Pos 23 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5036 #define GPIO_GFER_P23 (_U_(0x1) << GPIO_GFER_P23_Pos) 5037 #define GPIO_GFER_P24_Pos 24 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5038 #define GPIO_GFER_P24 (_U_(0x1) << GPIO_GFER_P24_Pos) 5039 #define GPIO_GFER_P25_Pos 25 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5040 #define GPIO_GFER_P25 (_U_(0x1) << GPIO_GFER_P25_Pos) 5041 #define GPIO_GFER_P26_Pos 26 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5042 #define GPIO_GFER_P26 (_U_(0x1) << GPIO_GFER_P26_Pos) 5043 #define GPIO_GFER_P27_Pos 27 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5044 #define GPIO_GFER_P27 (_U_(0x1) << GPIO_GFER_P27_Pos) 5045 #define GPIO_GFER_P28_Pos 28 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5046 #define GPIO_GFER_P28 (_U_(0x1) << GPIO_GFER_P28_Pos) 5047 #define GPIO_GFER_P29_Pos 29 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5048 #define GPIO_GFER_P29 (_U_(0x1) << GPIO_GFER_P29_Pos) 5049 #define GPIO_GFER_P30_Pos 30 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5050 #define GPIO_GFER_P30 (_U_(0x1) << GPIO_GFER_P30_Pos) 5051 #define GPIO_GFER_P31_Pos 31 /**< \brief (GPIO_GFER) Glitch Filter Enable */ 5052 #define GPIO_GFER_P31 (_U_(0x1) << GPIO_GFER_P31_Pos) 5053 #define GPIO_GFER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GFER) MASK Register */ 5054 5055 /* -------- GPIO_GFERS : (GPIO Offset: 0x0C4) ( /W 32) port Glitch Filter Enable Register - Set -------- */ 5056 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5057 typedef union { 5058 struct { 5059 uint32_t P0:1; /*!< bit: 0 Glitch Filter Enable */ 5060 uint32_t P1:1; /*!< bit: 1 Glitch Filter Enable */ 5061 uint32_t P2:1; /*!< bit: 2 Glitch Filter Enable */ 5062 uint32_t P3:1; /*!< bit: 3 Glitch Filter Enable */ 5063 uint32_t P4:1; /*!< bit: 4 Glitch Filter Enable */ 5064 uint32_t P5:1; /*!< bit: 5 Glitch Filter Enable */ 5065 uint32_t P6:1; /*!< bit: 6 Glitch Filter Enable */ 5066 uint32_t P7:1; /*!< bit: 7 Glitch Filter Enable */ 5067 uint32_t P8:1; /*!< bit: 8 Glitch Filter Enable */ 5068 uint32_t P9:1; /*!< bit: 9 Glitch Filter Enable */ 5069 uint32_t P10:1; /*!< bit: 10 Glitch Filter Enable */ 5070 uint32_t P11:1; /*!< bit: 11 Glitch Filter Enable */ 5071 uint32_t P12:1; /*!< bit: 12 Glitch Filter Enable */ 5072 uint32_t P13:1; /*!< bit: 13 Glitch Filter Enable */ 5073 uint32_t P14:1; /*!< bit: 14 Glitch Filter Enable */ 5074 uint32_t P15:1; /*!< bit: 15 Glitch Filter Enable */ 5075 uint32_t P16:1; /*!< bit: 16 Glitch Filter Enable */ 5076 uint32_t P17:1; /*!< bit: 17 Glitch Filter Enable */ 5077 uint32_t P18:1; /*!< bit: 18 Glitch Filter Enable */ 5078 uint32_t P19:1; /*!< bit: 19 Glitch Filter Enable */ 5079 uint32_t P20:1; /*!< bit: 20 Glitch Filter Enable */ 5080 uint32_t P21:1; /*!< bit: 21 Glitch Filter Enable */ 5081 uint32_t P22:1; /*!< bit: 22 Glitch Filter Enable */ 5082 uint32_t P23:1; /*!< bit: 23 Glitch Filter Enable */ 5083 uint32_t P24:1; /*!< bit: 24 Glitch Filter Enable */ 5084 uint32_t P25:1; /*!< bit: 25 Glitch Filter Enable */ 5085 uint32_t P26:1; /*!< bit: 26 Glitch Filter Enable */ 5086 uint32_t P27:1; /*!< bit: 27 Glitch Filter Enable */ 5087 uint32_t P28:1; /*!< bit: 28 Glitch Filter Enable */ 5088 uint32_t P29:1; /*!< bit: 29 Glitch Filter Enable */ 5089 uint32_t P30:1; /*!< bit: 30 Glitch Filter Enable */ 5090 uint32_t P31:1; /*!< bit: 31 Glitch Filter Enable */ 5091 } bit; /*!< Structure used for bit access */ 5092 uint32_t reg; /*!< Type used for register access */ 5093 } GPIO_GFERS_Type; 5094 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5095 5096 #define GPIO_GFERS_OFFSET 0x0C4 /**< \brief (GPIO_GFERS offset) Glitch Filter Enable Register - Set */ 5097 5098 #define GPIO_GFERS_P0_Pos 0 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5099 #define GPIO_GFERS_P0 (_U_(0x1) << GPIO_GFERS_P0_Pos) 5100 #define GPIO_GFERS_P1_Pos 1 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5101 #define GPIO_GFERS_P1 (_U_(0x1) << GPIO_GFERS_P1_Pos) 5102 #define GPIO_GFERS_P2_Pos 2 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5103 #define GPIO_GFERS_P2 (_U_(0x1) << GPIO_GFERS_P2_Pos) 5104 #define GPIO_GFERS_P3_Pos 3 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5105 #define GPIO_GFERS_P3 (_U_(0x1) << GPIO_GFERS_P3_Pos) 5106 #define GPIO_GFERS_P4_Pos 4 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5107 #define GPIO_GFERS_P4 (_U_(0x1) << GPIO_GFERS_P4_Pos) 5108 #define GPIO_GFERS_P5_Pos 5 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5109 #define GPIO_GFERS_P5 (_U_(0x1) << GPIO_GFERS_P5_Pos) 5110 #define GPIO_GFERS_P6_Pos 6 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5111 #define GPIO_GFERS_P6 (_U_(0x1) << GPIO_GFERS_P6_Pos) 5112 #define GPIO_GFERS_P7_Pos 7 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5113 #define GPIO_GFERS_P7 (_U_(0x1) << GPIO_GFERS_P7_Pos) 5114 #define GPIO_GFERS_P8_Pos 8 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5115 #define GPIO_GFERS_P8 (_U_(0x1) << GPIO_GFERS_P8_Pos) 5116 #define GPIO_GFERS_P9_Pos 9 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5117 #define GPIO_GFERS_P9 (_U_(0x1) << GPIO_GFERS_P9_Pos) 5118 #define GPIO_GFERS_P10_Pos 10 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5119 #define GPIO_GFERS_P10 (_U_(0x1) << GPIO_GFERS_P10_Pos) 5120 #define GPIO_GFERS_P11_Pos 11 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5121 #define GPIO_GFERS_P11 (_U_(0x1) << GPIO_GFERS_P11_Pos) 5122 #define GPIO_GFERS_P12_Pos 12 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5123 #define GPIO_GFERS_P12 (_U_(0x1) << GPIO_GFERS_P12_Pos) 5124 #define GPIO_GFERS_P13_Pos 13 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5125 #define GPIO_GFERS_P13 (_U_(0x1) << GPIO_GFERS_P13_Pos) 5126 #define GPIO_GFERS_P14_Pos 14 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5127 #define GPIO_GFERS_P14 (_U_(0x1) << GPIO_GFERS_P14_Pos) 5128 #define GPIO_GFERS_P15_Pos 15 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5129 #define GPIO_GFERS_P15 (_U_(0x1) << GPIO_GFERS_P15_Pos) 5130 #define GPIO_GFERS_P16_Pos 16 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5131 #define GPIO_GFERS_P16 (_U_(0x1) << GPIO_GFERS_P16_Pos) 5132 #define GPIO_GFERS_P17_Pos 17 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5133 #define GPIO_GFERS_P17 (_U_(0x1) << GPIO_GFERS_P17_Pos) 5134 #define GPIO_GFERS_P18_Pos 18 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5135 #define GPIO_GFERS_P18 (_U_(0x1) << GPIO_GFERS_P18_Pos) 5136 #define GPIO_GFERS_P19_Pos 19 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5137 #define GPIO_GFERS_P19 (_U_(0x1) << GPIO_GFERS_P19_Pos) 5138 #define GPIO_GFERS_P20_Pos 20 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5139 #define GPIO_GFERS_P20 (_U_(0x1) << GPIO_GFERS_P20_Pos) 5140 #define GPIO_GFERS_P21_Pos 21 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5141 #define GPIO_GFERS_P21 (_U_(0x1) << GPIO_GFERS_P21_Pos) 5142 #define GPIO_GFERS_P22_Pos 22 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5143 #define GPIO_GFERS_P22 (_U_(0x1) << GPIO_GFERS_P22_Pos) 5144 #define GPIO_GFERS_P23_Pos 23 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5145 #define GPIO_GFERS_P23 (_U_(0x1) << GPIO_GFERS_P23_Pos) 5146 #define GPIO_GFERS_P24_Pos 24 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5147 #define GPIO_GFERS_P24 (_U_(0x1) << GPIO_GFERS_P24_Pos) 5148 #define GPIO_GFERS_P25_Pos 25 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5149 #define GPIO_GFERS_P25 (_U_(0x1) << GPIO_GFERS_P25_Pos) 5150 #define GPIO_GFERS_P26_Pos 26 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5151 #define GPIO_GFERS_P26 (_U_(0x1) << GPIO_GFERS_P26_Pos) 5152 #define GPIO_GFERS_P27_Pos 27 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5153 #define GPIO_GFERS_P27 (_U_(0x1) << GPIO_GFERS_P27_Pos) 5154 #define GPIO_GFERS_P28_Pos 28 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5155 #define GPIO_GFERS_P28 (_U_(0x1) << GPIO_GFERS_P28_Pos) 5156 #define GPIO_GFERS_P29_Pos 29 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5157 #define GPIO_GFERS_P29 (_U_(0x1) << GPIO_GFERS_P29_Pos) 5158 #define GPIO_GFERS_P30_Pos 30 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5159 #define GPIO_GFERS_P30 (_U_(0x1) << GPIO_GFERS_P30_Pos) 5160 #define GPIO_GFERS_P31_Pos 31 /**< \brief (GPIO_GFERS) Glitch Filter Enable */ 5161 #define GPIO_GFERS_P31 (_U_(0x1) << GPIO_GFERS_P31_Pos) 5162 #define GPIO_GFERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GFERS) MASK Register */ 5163 5164 /* -------- GPIO_GFERC : (GPIO Offset: 0x0C8) ( /W 32) port Glitch Filter Enable Register - Clear -------- */ 5165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5166 typedef union { 5167 struct { 5168 uint32_t P0:1; /*!< bit: 0 Glitch Filter Enable */ 5169 uint32_t P1:1; /*!< bit: 1 Glitch Filter Enable */ 5170 uint32_t P2:1; /*!< bit: 2 Glitch Filter Enable */ 5171 uint32_t P3:1; /*!< bit: 3 Glitch Filter Enable */ 5172 uint32_t P4:1; /*!< bit: 4 Glitch Filter Enable */ 5173 uint32_t P5:1; /*!< bit: 5 Glitch Filter Enable */ 5174 uint32_t P6:1; /*!< bit: 6 Glitch Filter Enable */ 5175 uint32_t P7:1; /*!< bit: 7 Glitch Filter Enable */ 5176 uint32_t P8:1; /*!< bit: 8 Glitch Filter Enable */ 5177 uint32_t P9:1; /*!< bit: 9 Glitch Filter Enable */ 5178 uint32_t P10:1; /*!< bit: 10 Glitch Filter Enable */ 5179 uint32_t P11:1; /*!< bit: 11 Glitch Filter Enable */ 5180 uint32_t P12:1; /*!< bit: 12 Glitch Filter Enable */ 5181 uint32_t P13:1; /*!< bit: 13 Glitch Filter Enable */ 5182 uint32_t P14:1; /*!< bit: 14 Glitch Filter Enable */ 5183 uint32_t P15:1; /*!< bit: 15 Glitch Filter Enable */ 5184 uint32_t P16:1; /*!< bit: 16 Glitch Filter Enable */ 5185 uint32_t P17:1; /*!< bit: 17 Glitch Filter Enable */ 5186 uint32_t P18:1; /*!< bit: 18 Glitch Filter Enable */ 5187 uint32_t P19:1; /*!< bit: 19 Glitch Filter Enable */ 5188 uint32_t P20:1; /*!< bit: 20 Glitch Filter Enable */ 5189 uint32_t P21:1; /*!< bit: 21 Glitch Filter Enable */ 5190 uint32_t P22:1; /*!< bit: 22 Glitch Filter Enable */ 5191 uint32_t P23:1; /*!< bit: 23 Glitch Filter Enable */ 5192 uint32_t P24:1; /*!< bit: 24 Glitch Filter Enable */ 5193 uint32_t P25:1; /*!< bit: 25 Glitch Filter Enable */ 5194 uint32_t P26:1; /*!< bit: 26 Glitch Filter Enable */ 5195 uint32_t P27:1; /*!< bit: 27 Glitch Filter Enable */ 5196 uint32_t P28:1; /*!< bit: 28 Glitch Filter Enable */ 5197 uint32_t P29:1; /*!< bit: 29 Glitch Filter Enable */ 5198 uint32_t P30:1; /*!< bit: 30 Glitch Filter Enable */ 5199 uint32_t P31:1; /*!< bit: 31 Glitch Filter Enable */ 5200 } bit; /*!< Structure used for bit access */ 5201 uint32_t reg; /*!< Type used for register access */ 5202 } GPIO_GFERC_Type; 5203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5204 5205 #define GPIO_GFERC_OFFSET 0x0C8 /**< \brief (GPIO_GFERC offset) Glitch Filter Enable Register - Clear */ 5206 5207 #define GPIO_GFERC_P0_Pos 0 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5208 #define GPIO_GFERC_P0 (_U_(0x1) << GPIO_GFERC_P0_Pos) 5209 #define GPIO_GFERC_P1_Pos 1 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5210 #define GPIO_GFERC_P1 (_U_(0x1) << GPIO_GFERC_P1_Pos) 5211 #define GPIO_GFERC_P2_Pos 2 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5212 #define GPIO_GFERC_P2 (_U_(0x1) << GPIO_GFERC_P2_Pos) 5213 #define GPIO_GFERC_P3_Pos 3 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5214 #define GPIO_GFERC_P3 (_U_(0x1) << GPIO_GFERC_P3_Pos) 5215 #define GPIO_GFERC_P4_Pos 4 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5216 #define GPIO_GFERC_P4 (_U_(0x1) << GPIO_GFERC_P4_Pos) 5217 #define GPIO_GFERC_P5_Pos 5 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5218 #define GPIO_GFERC_P5 (_U_(0x1) << GPIO_GFERC_P5_Pos) 5219 #define GPIO_GFERC_P6_Pos 6 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5220 #define GPIO_GFERC_P6 (_U_(0x1) << GPIO_GFERC_P6_Pos) 5221 #define GPIO_GFERC_P7_Pos 7 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5222 #define GPIO_GFERC_P7 (_U_(0x1) << GPIO_GFERC_P7_Pos) 5223 #define GPIO_GFERC_P8_Pos 8 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5224 #define GPIO_GFERC_P8 (_U_(0x1) << GPIO_GFERC_P8_Pos) 5225 #define GPIO_GFERC_P9_Pos 9 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5226 #define GPIO_GFERC_P9 (_U_(0x1) << GPIO_GFERC_P9_Pos) 5227 #define GPIO_GFERC_P10_Pos 10 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5228 #define GPIO_GFERC_P10 (_U_(0x1) << GPIO_GFERC_P10_Pos) 5229 #define GPIO_GFERC_P11_Pos 11 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5230 #define GPIO_GFERC_P11 (_U_(0x1) << GPIO_GFERC_P11_Pos) 5231 #define GPIO_GFERC_P12_Pos 12 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5232 #define GPIO_GFERC_P12 (_U_(0x1) << GPIO_GFERC_P12_Pos) 5233 #define GPIO_GFERC_P13_Pos 13 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5234 #define GPIO_GFERC_P13 (_U_(0x1) << GPIO_GFERC_P13_Pos) 5235 #define GPIO_GFERC_P14_Pos 14 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5236 #define GPIO_GFERC_P14 (_U_(0x1) << GPIO_GFERC_P14_Pos) 5237 #define GPIO_GFERC_P15_Pos 15 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5238 #define GPIO_GFERC_P15 (_U_(0x1) << GPIO_GFERC_P15_Pos) 5239 #define GPIO_GFERC_P16_Pos 16 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5240 #define GPIO_GFERC_P16 (_U_(0x1) << GPIO_GFERC_P16_Pos) 5241 #define GPIO_GFERC_P17_Pos 17 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5242 #define GPIO_GFERC_P17 (_U_(0x1) << GPIO_GFERC_P17_Pos) 5243 #define GPIO_GFERC_P18_Pos 18 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5244 #define GPIO_GFERC_P18 (_U_(0x1) << GPIO_GFERC_P18_Pos) 5245 #define GPIO_GFERC_P19_Pos 19 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5246 #define GPIO_GFERC_P19 (_U_(0x1) << GPIO_GFERC_P19_Pos) 5247 #define GPIO_GFERC_P20_Pos 20 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5248 #define GPIO_GFERC_P20 (_U_(0x1) << GPIO_GFERC_P20_Pos) 5249 #define GPIO_GFERC_P21_Pos 21 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5250 #define GPIO_GFERC_P21 (_U_(0x1) << GPIO_GFERC_P21_Pos) 5251 #define GPIO_GFERC_P22_Pos 22 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5252 #define GPIO_GFERC_P22 (_U_(0x1) << GPIO_GFERC_P22_Pos) 5253 #define GPIO_GFERC_P23_Pos 23 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5254 #define GPIO_GFERC_P23 (_U_(0x1) << GPIO_GFERC_P23_Pos) 5255 #define GPIO_GFERC_P24_Pos 24 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5256 #define GPIO_GFERC_P24 (_U_(0x1) << GPIO_GFERC_P24_Pos) 5257 #define GPIO_GFERC_P25_Pos 25 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5258 #define GPIO_GFERC_P25 (_U_(0x1) << GPIO_GFERC_P25_Pos) 5259 #define GPIO_GFERC_P26_Pos 26 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5260 #define GPIO_GFERC_P26 (_U_(0x1) << GPIO_GFERC_P26_Pos) 5261 #define GPIO_GFERC_P27_Pos 27 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5262 #define GPIO_GFERC_P27 (_U_(0x1) << GPIO_GFERC_P27_Pos) 5263 #define GPIO_GFERC_P28_Pos 28 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5264 #define GPIO_GFERC_P28 (_U_(0x1) << GPIO_GFERC_P28_Pos) 5265 #define GPIO_GFERC_P29_Pos 29 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5266 #define GPIO_GFERC_P29 (_U_(0x1) << GPIO_GFERC_P29_Pos) 5267 #define GPIO_GFERC_P30_Pos 30 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5268 #define GPIO_GFERC_P30 (_U_(0x1) << GPIO_GFERC_P30_Pos) 5269 #define GPIO_GFERC_P31_Pos 31 /**< \brief (GPIO_GFERC) Glitch Filter Enable */ 5270 #define GPIO_GFERC_P31 (_U_(0x1) << GPIO_GFERC_P31_Pos) 5271 #define GPIO_GFERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GFERC) MASK Register */ 5272 5273 /* -------- GPIO_GFERT : (GPIO Offset: 0x0CC) ( /W 32) port Glitch Filter Enable Register - Toggle -------- */ 5274 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5275 typedef union { 5276 struct { 5277 uint32_t P0:1; /*!< bit: 0 Glitch Filter Enable */ 5278 uint32_t P1:1; /*!< bit: 1 Glitch Filter Enable */ 5279 uint32_t P2:1; /*!< bit: 2 Glitch Filter Enable */ 5280 uint32_t P3:1; /*!< bit: 3 Glitch Filter Enable */ 5281 uint32_t P4:1; /*!< bit: 4 Glitch Filter Enable */ 5282 uint32_t P5:1; /*!< bit: 5 Glitch Filter Enable */ 5283 uint32_t P6:1; /*!< bit: 6 Glitch Filter Enable */ 5284 uint32_t P7:1; /*!< bit: 7 Glitch Filter Enable */ 5285 uint32_t P8:1; /*!< bit: 8 Glitch Filter Enable */ 5286 uint32_t P9:1; /*!< bit: 9 Glitch Filter Enable */ 5287 uint32_t P10:1; /*!< bit: 10 Glitch Filter Enable */ 5288 uint32_t P11:1; /*!< bit: 11 Glitch Filter Enable */ 5289 uint32_t P12:1; /*!< bit: 12 Glitch Filter Enable */ 5290 uint32_t P13:1; /*!< bit: 13 Glitch Filter Enable */ 5291 uint32_t P14:1; /*!< bit: 14 Glitch Filter Enable */ 5292 uint32_t P15:1; /*!< bit: 15 Glitch Filter Enable */ 5293 uint32_t P16:1; /*!< bit: 16 Glitch Filter Enable */ 5294 uint32_t P17:1; /*!< bit: 17 Glitch Filter Enable */ 5295 uint32_t P18:1; /*!< bit: 18 Glitch Filter Enable */ 5296 uint32_t P19:1; /*!< bit: 19 Glitch Filter Enable */ 5297 uint32_t P20:1; /*!< bit: 20 Glitch Filter Enable */ 5298 uint32_t P21:1; /*!< bit: 21 Glitch Filter Enable */ 5299 uint32_t P22:1; /*!< bit: 22 Glitch Filter Enable */ 5300 uint32_t P23:1; /*!< bit: 23 Glitch Filter Enable */ 5301 uint32_t P24:1; /*!< bit: 24 Glitch Filter Enable */ 5302 uint32_t P25:1; /*!< bit: 25 Glitch Filter Enable */ 5303 uint32_t P26:1; /*!< bit: 26 Glitch Filter Enable */ 5304 uint32_t P27:1; /*!< bit: 27 Glitch Filter Enable */ 5305 uint32_t P28:1; /*!< bit: 28 Glitch Filter Enable */ 5306 uint32_t P29:1; /*!< bit: 29 Glitch Filter Enable */ 5307 uint32_t P30:1; /*!< bit: 30 Glitch Filter Enable */ 5308 uint32_t P31:1; /*!< bit: 31 Glitch Filter Enable */ 5309 } bit; /*!< Structure used for bit access */ 5310 uint32_t reg; /*!< Type used for register access */ 5311 } GPIO_GFERT_Type; 5312 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5313 5314 #define GPIO_GFERT_OFFSET 0x0CC /**< \brief (GPIO_GFERT offset) Glitch Filter Enable Register - Toggle */ 5315 5316 #define GPIO_GFERT_P0_Pos 0 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5317 #define GPIO_GFERT_P0 (_U_(0x1) << GPIO_GFERT_P0_Pos) 5318 #define GPIO_GFERT_P1_Pos 1 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5319 #define GPIO_GFERT_P1 (_U_(0x1) << GPIO_GFERT_P1_Pos) 5320 #define GPIO_GFERT_P2_Pos 2 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5321 #define GPIO_GFERT_P2 (_U_(0x1) << GPIO_GFERT_P2_Pos) 5322 #define GPIO_GFERT_P3_Pos 3 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5323 #define GPIO_GFERT_P3 (_U_(0x1) << GPIO_GFERT_P3_Pos) 5324 #define GPIO_GFERT_P4_Pos 4 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5325 #define GPIO_GFERT_P4 (_U_(0x1) << GPIO_GFERT_P4_Pos) 5326 #define GPIO_GFERT_P5_Pos 5 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5327 #define GPIO_GFERT_P5 (_U_(0x1) << GPIO_GFERT_P5_Pos) 5328 #define GPIO_GFERT_P6_Pos 6 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5329 #define GPIO_GFERT_P6 (_U_(0x1) << GPIO_GFERT_P6_Pos) 5330 #define GPIO_GFERT_P7_Pos 7 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5331 #define GPIO_GFERT_P7 (_U_(0x1) << GPIO_GFERT_P7_Pos) 5332 #define GPIO_GFERT_P8_Pos 8 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5333 #define GPIO_GFERT_P8 (_U_(0x1) << GPIO_GFERT_P8_Pos) 5334 #define GPIO_GFERT_P9_Pos 9 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5335 #define GPIO_GFERT_P9 (_U_(0x1) << GPIO_GFERT_P9_Pos) 5336 #define GPIO_GFERT_P10_Pos 10 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5337 #define GPIO_GFERT_P10 (_U_(0x1) << GPIO_GFERT_P10_Pos) 5338 #define GPIO_GFERT_P11_Pos 11 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5339 #define GPIO_GFERT_P11 (_U_(0x1) << GPIO_GFERT_P11_Pos) 5340 #define GPIO_GFERT_P12_Pos 12 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5341 #define GPIO_GFERT_P12 (_U_(0x1) << GPIO_GFERT_P12_Pos) 5342 #define GPIO_GFERT_P13_Pos 13 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5343 #define GPIO_GFERT_P13 (_U_(0x1) << GPIO_GFERT_P13_Pos) 5344 #define GPIO_GFERT_P14_Pos 14 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5345 #define GPIO_GFERT_P14 (_U_(0x1) << GPIO_GFERT_P14_Pos) 5346 #define GPIO_GFERT_P15_Pos 15 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5347 #define GPIO_GFERT_P15 (_U_(0x1) << GPIO_GFERT_P15_Pos) 5348 #define GPIO_GFERT_P16_Pos 16 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5349 #define GPIO_GFERT_P16 (_U_(0x1) << GPIO_GFERT_P16_Pos) 5350 #define GPIO_GFERT_P17_Pos 17 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5351 #define GPIO_GFERT_P17 (_U_(0x1) << GPIO_GFERT_P17_Pos) 5352 #define GPIO_GFERT_P18_Pos 18 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5353 #define GPIO_GFERT_P18 (_U_(0x1) << GPIO_GFERT_P18_Pos) 5354 #define GPIO_GFERT_P19_Pos 19 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5355 #define GPIO_GFERT_P19 (_U_(0x1) << GPIO_GFERT_P19_Pos) 5356 #define GPIO_GFERT_P20_Pos 20 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5357 #define GPIO_GFERT_P20 (_U_(0x1) << GPIO_GFERT_P20_Pos) 5358 #define GPIO_GFERT_P21_Pos 21 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5359 #define GPIO_GFERT_P21 (_U_(0x1) << GPIO_GFERT_P21_Pos) 5360 #define GPIO_GFERT_P22_Pos 22 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5361 #define GPIO_GFERT_P22 (_U_(0x1) << GPIO_GFERT_P22_Pos) 5362 #define GPIO_GFERT_P23_Pos 23 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5363 #define GPIO_GFERT_P23 (_U_(0x1) << GPIO_GFERT_P23_Pos) 5364 #define GPIO_GFERT_P24_Pos 24 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5365 #define GPIO_GFERT_P24 (_U_(0x1) << GPIO_GFERT_P24_Pos) 5366 #define GPIO_GFERT_P25_Pos 25 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5367 #define GPIO_GFERT_P25 (_U_(0x1) << GPIO_GFERT_P25_Pos) 5368 #define GPIO_GFERT_P26_Pos 26 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5369 #define GPIO_GFERT_P26 (_U_(0x1) << GPIO_GFERT_P26_Pos) 5370 #define GPIO_GFERT_P27_Pos 27 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5371 #define GPIO_GFERT_P27 (_U_(0x1) << GPIO_GFERT_P27_Pos) 5372 #define GPIO_GFERT_P28_Pos 28 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5373 #define GPIO_GFERT_P28 (_U_(0x1) << GPIO_GFERT_P28_Pos) 5374 #define GPIO_GFERT_P29_Pos 29 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5375 #define GPIO_GFERT_P29 (_U_(0x1) << GPIO_GFERT_P29_Pos) 5376 #define GPIO_GFERT_P30_Pos 30 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5377 #define GPIO_GFERT_P30 (_U_(0x1) << GPIO_GFERT_P30_Pos) 5378 #define GPIO_GFERT_P31_Pos 31 /**< \brief (GPIO_GFERT) Glitch Filter Enable */ 5379 #define GPIO_GFERT_P31 (_U_(0x1) << GPIO_GFERT_P31_Pos) 5380 #define GPIO_GFERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_GFERT) MASK Register */ 5381 5382 /* -------- GPIO_IFR : (GPIO Offset: 0x0D0) (R/ 32) port Interrupt Flag Register -------- */ 5383 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5384 typedef union { 5385 struct { 5386 uint32_t P0:1; /*!< bit: 0 Interrupt Flag */ 5387 uint32_t P1:1; /*!< bit: 1 Interrupt Flag */ 5388 uint32_t P2:1; /*!< bit: 2 Interrupt Flag */ 5389 uint32_t P3:1; /*!< bit: 3 Interrupt Flag */ 5390 uint32_t P4:1; /*!< bit: 4 Interrupt Flag */ 5391 uint32_t P5:1; /*!< bit: 5 Interrupt Flag */ 5392 uint32_t P6:1; /*!< bit: 6 Interrupt Flag */ 5393 uint32_t P7:1; /*!< bit: 7 Interrupt Flag */ 5394 uint32_t P8:1; /*!< bit: 8 Interrupt Flag */ 5395 uint32_t P9:1; /*!< bit: 9 Interrupt Flag */ 5396 uint32_t P10:1; /*!< bit: 10 Interrupt Flag */ 5397 uint32_t P11:1; /*!< bit: 11 Interrupt Flag */ 5398 uint32_t P12:1; /*!< bit: 12 Interrupt Flag */ 5399 uint32_t P13:1; /*!< bit: 13 Interrupt Flag */ 5400 uint32_t P14:1; /*!< bit: 14 Interrupt Flag */ 5401 uint32_t P15:1; /*!< bit: 15 Interrupt Flag */ 5402 uint32_t P16:1; /*!< bit: 16 Interrupt Flag */ 5403 uint32_t P17:1; /*!< bit: 17 Interrupt Flag */ 5404 uint32_t P18:1; /*!< bit: 18 Interrupt Flag */ 5405 uint32_t P19:1; /*!< bit: 19 Interrupt Flag */ 5406 uint32_t P20:1; /*!< bit: 20 Interrupt Flag */ 5407 uint32_t P21:1; /*!< bit: 21 Interrupt Flag */ 5408 uint32_t P22:1; /*!< bit: 22 Interrupt Flag */ 5409 uint32_t P23:1; /*!< bit: 23 Interrupt Flag */ 5410 uint32_t P24:1; /*!< bit: 24 Interrupt Flag */ 5411 uint32_t P25:1; /*!< bit: 25 Interrupt Flag */ 5412 uint32_t P26:1; /*!< bit: 26 Interrupt Flag */ 5413 uint32_t P27:1; /*!< bit: 27 Interrupt Flag */ 5414 uint32_t P28:1; /*!< bit: 28 Interrupt Flag */ 5415 uint32_t P29:1; /*!< bit: 29 Interrupt Flag */ 5416 uint32_t P30:1; /*!< bit: 30 Interrupt Flag */ 5417 uint32_t P31:1; /*!< bit: 31 Interrupt Flag */ 5418 } bit; /*!< Structure used for bit access */ 5419 uint32_t reg; /*!< Type used for register access */ 5420 } GPIO_IFR_Type; 5421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5422 5423 #define GPIO_IFR_OFFSET 0x0D0 /**< \brief (GPIO_IFR offset) Interrupt Flag Register */ 5424 5425 #define GPIO_IFR_P0_Pos 0 /**< \brief (GPIO_IFR) Interrupt Flag */ 5426 #define GPIO_IFR_P0 (_U_(0x1) << GPIO_IFR_P0_Pos) 5427 #define GPIO_IFR_P1_Pos 1 /**< \brief (GPIO_IFR) Interrupt Flag */ 5428 #define GPIO_IFR_P1 (_U_(0x1) << GPIO_IFR_P1_Pos) 5429 #define GPIO_IFR_P2_Pos 2 /**< \brief (GPIO_IFR) Interrupt Flag */ 5430 #define GPIO_IFR_P2 (_U_(0x1) << GPIO_IFR_P2_Pos) 5431 #define GPIO_IFR_P3_Pos 3 /**< \brief (GPIO_IFR) Interrupt Flag */ 5432 #define GPIO_IFR_P3 (_U_(0x1) << GPIO_IFR_P3_Pos) 5433 #define GPIO_IFR_P4_Pos 4 /**< \brief (GPIO_IFR) Interrupt Flag */ 5434 #define GPIO_IFR_P4 (_U_(0x1) << GPIO_IFR_P4_Pos) 5435 #define GPIO_IFR_P5_Pos 5 /**< \brief (GPIO_IFR) Interrupt Flag */ 5436 #define GPIO_IFR_P5 (_U_(0x1) << GPIO_IFR_P5_Pos) 5437 #define GPIO_IFR_P6_Pos 6 /**< \brief (GPIO_IFR) Interrupt Flag */ 5438 #define GPIO_IFR_P6 (_U_(0x1) << GPIO_IFR_P6_Pos) 5439 #define GPIO_IFR_P7_Pos 7 /**< \brief (GPIO_IFR) Interrupt Flag */ 5440 #define GPIO_IFR_P7 (_U_(0x1) << GPIO_IFR_P7_Pos) 5441 #define GPIO_IFR_P8_Pos 8 /**< \brief (GPIO_IFR) Interrupt Flag */ 5442 #define GPIO_IFR_P8 (_U_(0x1) << GPIO_IFR_P8_Pos) 5443 #define GPIO_IFR_P9_Pos 9 /**< \brief (GPIO_IFR) Interrupt Flag */ 5444 #define GPIO_IFR_P9 (_U_(0x1) << GPIO_IFR_P9_Pos) 5445 #define GPIO_IFR_P10_Pos 10 /**< \brief (GPIO_IFR) Interrupt Flag */ 5446 #define GPIO_IFR_P10 (_U_(0x1) << GPIO_IFR_P10_Pos) 5447 #define GPIO_IFR_P11_Pos 11 /**< \brief (GPIO_IFR) Interrupt Flag */ 5448 #define GPIO_IFR_P11 (_U_(0x1) << GPIO_IFR_P11_Pos) 5449 #define GPIO_IFR_P12_Pos 12 /**< \brief (GPIO_IFR) Interrupt Flag */ 5450 #define GPIO_IFR_P12 (_U_(0x1) << GPIO_IFR_P12_Pos) 5451 #define GPIO_IFR_P13_Pos 13 /**< \brief (GPIO_IFR) Interrupt Flag */ 5452 #define GPIO_IFR_P13 (_U_(0x1) << GPIO_IFR_P13_Pos) 5453 #define GPIO_IFR_P14_Pos 14 /**< \brief (GPIO_IFR) Interrupt Flag */ 5454 #define GPIO_IFR_P14 (_U_(0x1) << GPIO_IFR_P14_Pos) 5455 #define GPIO_IFR_P15_Pos 15 /**< \brief (GPIO_IFR) Interrupt Flag */ 5456 #define GPIO_IFR_P15 (_U_(0x1) << GPIO_IFR_P15_Pos) 5457 #define GPIO_IFR_P16_Pos 16 /**< \brief (GPIO_IFR) Interrupt Flag */ 5458 #define GPIO_IFR_P16 (_U_(0x1) << GPIO_IFR_P16_Pos) 5459 #define GPIO_IFR_P17_Pos 17 /**< \brief (GPIO_IFR) Interrupt Flag */ 5460 #define GPIO_IFR_P17 (_U_(0x1) << GPIO_IFR_P17_Pos) 5461 #define GPIO_IFR_P18_Pos 18 /**< \brief (GPIO_IFR) Interrupt Flag */ 5462 #define GPIO_IFR_P18 (_U_(0x1) << GPIO_IFR_P18_Pos) 5463 #define GPIO_IFR_P19_Pos 19 /**< \brief (GPIO_IFR) Interrupt Flag */ 5464 #define GPIO_IFR_P19 (_U_(0x1) << GPIO_IFR_P19_Pos) 5465 #define GPIO_IFR_P20_Pos 20 /**< \brief (GPIO_IFR) Interrupt Flag */ 5466 #define GPIO_IFR_P20 (_U_(0x1) << GPIO_IFR_P20_Pos) 5467 #define GPIO_IFR_P21_Pos 21 /**< \brief (GPIO_IFR) Interrupt Flag */ 5468 #define GPIO_IFR_P21 (_U_(0x1) << GPIO_IFR_P21_Pos) 5469 #define GPIO_IFR_P22_Pos 22 /**< \brief (GPIO_IFR) Interrupt Flag */ 5470 #define GPIO_IFR_P22 (_U_(0x1) << GPIO_IFR_P22_Pos) 5471 #define GPIO_IFR_P23_Pos 23 /**< \brief (GPIO_IFR) Interrupt Flag */ 5472 #define GPIO_IFR_P23 (_U_(0x1) << GPIO_IFR_P23_Pos) 5473 #define GPIO_IFR_P24_Pos 24 /**< \brief (GPIO_IFR) Interrupt Flag */ 5474 #define GPIO_IFR_P24 (_U_(0x1) << GPIO_IFR_P24_Pos) 5475 #define GPIO_IFR_P25_Pos 25 /**< \brief (GPIO_IFR) Interrupt Flag */ 5476 #define GPIO_IFR_P25 (_U_(0x1) << GPIO_IFR_P25_Pos) 5477 #define GPIO_IFR_P26_Pos 26 /**< \brief (GPIO_IFR) Interrupt Flag */ 5478 #define GPIO_IFR_P26 (_U_(0x1) << GPIO_IFR_P26_Pos) 5479 #define GPIO_IFR_P27_Pos 27 /**< \brief (GPIO_IFR) Interrupt Flag */ 5480 #define GPIO_IFR_P27 (_U_(0x1) << GPIO_IFR_P27_Pos) 5481 #define GPIO_IFR_P28_Pos 28 /**< \brief (GPIO_IFR) Interrupt Flag */ 5482 #define GPIO_IFR_P28 (_U_(0x1) << GPIO_IFR_P28_Pos) 5483 #define GPIO_IFR_P29_Pos 29 /**< \brief (GPIO_IFR) Interrupt Flag */ 5484 #define GPIO_IFR_P29 (_U_(0x1) << GPIO_IFR_P29_Pos) 5485 #define GPIO_IFR_P30_Pos 30 /**< \brief (GPIO_IFR) Interrupt Flag */ 5486 #define GPIO_IFR_P30 (_U_(0x1) << GPIO_IFR_P30_Pos) 5487 #define GPIO_IFR_P31_Pos 31 /**< \brief (GPIO_IFR) Interrupt Flag */ 5488 #define GPIO_IFR_P31 (_U_(0x1) << GPIO_IFR_P31_Pos) 5489 #define GPIO_IFR_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IFR) MASK Register */ 5490 5491 /* -------- GPIO_IFRC : (GPIO Offset: 0x0D8) ( /W 32) port Interrupt Flag Register - Clear -------- */ 5492 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5493 typedef union { 5494 struct { 5495 uint32_t P0:1; /*!< bit: 0 Interrupt Flag */ 5496 uint32_t P1:1; /*!< bit: 1 Interrupt Flag */ 5497 uint32_t P2:1; /*!< bit: 2 Interrupt Flag */ 5498 uint32_t P3:1; /*!< bit: 3 Interrupt Flag */ 5499 uint32_t P4:1; /*!< bit: 4 Interrupt Flag */ 5500 uint32_t P5:1; /*!< bit: 5 Interrupt Flag */ 5501 uint32_t P6:1; /*!< bit: 6 Interrupt Flag */ 5502 uint32_t P7:1; /*!< bit: 7 Interrupt Flag */ 5503 uint32_t P8:1; /*!< bit: 8 Interrupt Flag */ 5504 uint32_t P9:1; /*!< bit: 9 Interrupt Flag */ 5505 uint32_t P10:1; /*!< bit: 10 Interrupt Flag */ 5506 uint32_t P11:1; /*!< bit: 11 Interrupt Flag */ 5507 uint32_t P12:1; /*!< bit: 12 Interrupt Flag */ 5508 uint32_t P13:1; /*!< bit: 13 Interrupt Flag */ 5509 uint32_t P14:1; /*!< bit: 14 Interrupt Flag */ 5510 uint32_t P15:1; /*!< bit: 15 Interrupt Flag */ 5511 uint32_t P16:1; /*!< bit: 16 Interrupt Flag */ 5512 uint32_t P17:1; /*!< bit: 17 Interrupt Flag */ 5513 uint32_t P18:1; /*!< bit: 18 Interrupt Flag */ 5514 uint32_t P19:1; /*!< bit: 19 Interrupt Flag */ 5515 uint32_t P20:1; /*!< bit: 20 Interrupt Flag */ 5516 uint32_t P21:1; /*!< bit: 21 Interrupt Flag */ 5517 uint32_t P22:1; /*!< bit: 22 Interrupt Flag */ 5518 uint32_t P23:1; /*!< bit: 23 Interrupt Flag */ 5519 uint32_t P24:1; /*!< bit: 24 Interrupt Flag */ 5520 uint32_t P25:1; /*!< bit: 25 Interrupt Flag */ 5521 uint32_t P26:1; /*!< bit: 26 Interrupt Flag */ 5522 uint32_t P27:1; /*!< bit: 27 Interrupt Flag */ 5523 uint32_t P28:1; /*!< bit: 28 Interrupt Flag */ 5524 uint32_t P29:1; /*!< bit: 29 Interrupt Flag */ 5525 uint32_t P30:1; /*!< bit: 30 Interrupt Flag */ 5526 uint32_t P31:1; /*!< bit: 31 Interrupt Flag */ 5527 } bit; /*!< Structure used for bit access */ 5528 uint32_t reg; /*!< Type used for register access */ 5529 } GPIO_IFRC_Type; 5530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5531 5532 #define GPIO_IFRC_OFFSET 0x0D8 /**< \brief (GPIO_IFRC offset) Interrupt Flag Register - Clear */ 5533 5534 #define GPIO_IFRC_P0_Pos 0 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5535 #define GPIO_IFRC_P0 (_U_(0x1) << GPIO_IFRC_P0_Pos) 5536 #define GPIO_IFRC_P1_Pos 1 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5537 #define GPIO_IFRC_P1 (_U_(0x1) << GPIO_IFRC_P1_Pos) 5538 #define GPIO_IFRC_P2_Pos 2 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5539 #define GPIO_IFRC_P2 (_U_(0x1) << GPIO_IFRC_P2_Pos) 5540 #define GPIO_IFRC_P3_Pos 3 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5541 #define GPIO_IFRC_P3 (_U_(0x1) << GPIO_IFRC_P3_Pos) 5542 #define GPIO_IFRC_P4_Pos 4 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5543 #define GPIO_IFRC_P4 (_U_(0x1) << GPIO_IFRC_P4_Pos) 5544 #define GPIO_IFRC_P5_Pos 5 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5545 #define GPIO_IFRC_P5 (_U_(0x1) << GPIO_IFRC_P5_Pos) 5546 #define GPIO_IFRC_P6_Pos 6 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5547 #define GPIO_IFRC_P6 (_U_(0x1) << GPIO_IFRC_P6_Pos) 5548 #define GPIO_IFRC_P7_Pos 7 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5549 #define GPIO_IFRC_P7 (_U_(0x1) << GPIO_IFRC_P7_Pos) 5550 #define GPIO_IFRC_P8_Pos 8 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5551 #define GPIO_IFRC_P8 (_U_(0x1) << GPIO_IFRC_P8_Pos) 5552 #define GPIO_IFRC_P9_Pos 9 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5553 #define GPIO_IFRC_P9 (_U_(0x1) << GPIO_IFRC_P9_Pos) 5554 #define GPIO_IFRC_P10_Pos 10 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5555 #define GPIO_IFRC_P10 (_U_(0x1) << GPIO_IFRC_P10_Pos) 5556 #define GPIO_IFRC_P11_Pos 11 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5557 #define GPIO_IFRC_P11 (_U_(0x1) << GPIO_IFRC_P11_Pos) 5558 #define GPIO_IFRC_P12_Pos 12 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5559 #define GPIO_IFRC_P12 (_U_(0x1) << GPIO_IFRC_P12_Pos) 5560 #define GPIO_IFRC_P13_Pos 13 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5561 #define GPIO_IFRC_P13 (_U_(0x1) << GPIO_IFRC_P13_Pos) 5562 #define GPIO_IFRC_P14_Pos 14 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5563 #define GPIO_IFRC_P14 (_U_(0x1) << GPIO_IFRC_P14_Pos) 5564 #define GPIO_IFRC_P15_Pos 15 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5565 #define GPIO_IFRC_P15 (_U_(0x1) << GPIO_IFRC_P15_Pos) 5566 #define GPIO_IFRC_P16_Pos 16 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5567 #define GPIO_IFRC_P16 (_U_(0x1) << GPIO_IFRC_P16_Pos) 5568 #define GPIO_IFRC_P17_Pos 17 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5569 #define GPIO_IFRC_P17 (_U_(0x1) << GPIO_IFRC_P17_Pos) 5570 #define GPIO_IFRC_P18_Pos 18 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5571 #define GPIO_IFRC_P18 (_U_(0x1) << GPIO_IFRC_P18_Pos) 5572 #define GPIO_IFRC_P19_Pos 19 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5573 #define GPIO_IFRC_P19 (_U_(0x1) << GPIO_IFRC_P19_Pos) 5574 #define GPIO_IFRC_P20_Pos 20 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5575 #define GPIO_IFRC_P20 (_U_(0x1) << GPIO_IFRC_P20_Pos) 5576 #define GPIO_IFRC_P21_Pos 21 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5577 #define GPIO_IFRC_P21 (_U_(0x1) << GPIO_IFRC_P21_Pos) 5578 #define GPIO_IFRC_P22_Pos 22 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5579 #define GPIO_IFRC_P22 (_U_(0x1) << GPIO_IFRC_P22_Pos) 5580 #define GPIO_IFRC_P23_Pos 23 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5581 #define GPIO_IFRC_P23 (_U_(0x1) << GPIO_IFRC_P23_Pos) 5582 #define GPIO_IFRC_P24_Pos 24 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5583 #define GPIO_IFRC_P24 (_U_(0x1) << GPIO_IFRC_P24_Pos) 5584 #define GPIO_IFRC_P25_Pos 25 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5585 #define GPIO_IFRC_P25 (_U_(0x1) << GPIO_IFRC_P25_Pos) 5586 #define GPIO_IFRC_P26_Pos 26 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5587 #define GPIO_IFRC_P26 (_U_(0x1) << GPIO_IFRC_P26_Pos) 5588 #define GPIO_IFRC_P27_Pos 27 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5589 #define GPIO_IFRC_P27 (_U_(0x1) << GPIO_IFRC_P27_Pos) 5590 #define GPIO_IFRC_P28_Pos 28 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5591 #define GPIO_IFRC_P28 (_U_(0x1) << GPIO_IFRC_P28_Pos) 5592 #define GPIO_IFRC_P29_Pos 29 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5593 #define GPIO_IFRC_P29 (_U_(0x1) << GPIO_IFRC_P29_Pos) 5594 #define GPIO_IFRC_P30_Pos 30 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5595 #define GPIO_IFRC_P30 (_U_(0x1) << GPIO_IFRC_P30_Pos) 5596 #define GPIO_IFRC_P31_Pos 31 /**< \brief (GPIO_IFRC) Interrupt Flag */ 5597 #define GPIO_IFRC_P31 (_U_(0x1) << GPIO_IFRC_P31_Pos) 5598 #define GPIO_IFRC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_IFRC) MASK Register */ 5599 5600 /* -------- GPIO_ODMER : (GPIO Offset: 0x0E0) (R/W 32) port Open Drain Mode Register -------- */ 5601 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5602 typedef union { 5603 struct { 5604 uint32_t P0:1; /*!< bit: 0 Open Drain Mode Enable */ 5605 uint32_t P1:1; /*!< bit: 1 Open Drain Mode Enable */ 5606 uint32_t P2:1; /*!< bit: 2 Open Drain Mode Enable */ 5607 uint32_t P3:1; /*!< bit: 3 Open Drain Mode Enable */ 5608 uint32_t P4:1; /*!< bit: 4 Open Drain Mode Enable */ 5609 uint32_t P5:1; /*!< bit: 5 Open Drain Mode Enable */ 5610 uint32_t P6:1; /*!< bit: 6 Open Drain Mode Enable */ 5611 uint32_t P7:1; /*!< bit: 7 Open Drain Mode Enable */ 5612 uint32_t P8:1; /*!< bit: 8 Open Drain Mode Enable */ 5613 uint32_t P9:1; /*!< bit: 9 Open Drain Mode Enable */ 5614 uint32_t P10:1; /*!< bit: 10 Open Drain Mode Enable */ 5615 uint32_t P11:1; /*!< bit: 11 Open Drain Mode Enable */ 5616 uint32_t P12:1; /*!< bit: 12 Open Drain Mode Enable */ 5617 uint32_t P13:1; /*!< bit: 13 Open Drain Mode Enable */ 5618 uint32_t P14:1; /*!< bit: 14 Open Drain Mode Enable */ 5619 uint32_t P15:1; /*!< bit: 15 Open Drain Mode Enable */ 5620 uint32_t P16:1; /*!< bit: 16 Open Drain Mode Enable */ 5621 uint32_t P17:1; /*!< bit: 17 Open Drain Mode Enable */ 5622 uint32_t P18:1; /*!< bit: 18 Open Drain Mode Enable */ 5623 uint32_t P19:1; /*!< bit: 19 Open Drain Mode Enable */ 5624 uint32_t P20:1; /*!< bit: 20 Open Drain Mode Enable */ 5625 uint32_t P21:1; /*!< bit: 21 Open Drain Mode Enable */ 5626 uint32_t P22:1; /*!< bit: 22 Open Drain Mode Enable */ 5627 uint32_t P23:1; /*!< bit: 23 Open Drain Mode Enable */ 5628 uint32_t P24:1; /*!< bit: 24 Open Drain Mode Enable */ 5629 uint32_t P25:1; /*!< bit: 25 Open Drain Mode Enable */ 5630 uint32_t P26:1; /*!< bit: 26 Open Drain Mode Enable */ 5631 uint32_t P27:1; /*!< bit: 27 Open Drain Mode Enable */ 5632 uint32_t P28:1; /*!< bit: 28 Open Drain Mode Enable */ 5633 uint32_t P29:1; /*!< bit: 29 Open Drain Mode Enable */ 5634 uint32_t P30:1; /*!< bit: 30 Open Drain Mode Enable */ 5635 uint32_t P31:1; /*!< bit: 31 Open Drain Mode Enable */ 5636 } bit; /*!< Structure used for bit access */ 5637 uint32_t reg; /*!< Type used for register access */ 5638 } GPIO_ODMER_Type; 5639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5640 5641 #define GPIO_ODMER_OFFSET 0x0E0 /**< \brief (GPIO_ODMER offset) Open Drain Mode Register */ 5642 5643 #define GPIO_ODMER_P0_Pos 0 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5644 #define GPIO_ODMER_P0 (_U_(0x1) << GPIO_ODMER_P0_Pos) 5645 #define GPIO_ODMER_P1_Pos 1 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5646 #define GPIO_ODMER_P1 (_U_(0x1) << GPIO_ODMER_P1_Pos) 5647 #define GPIO_ODMER_P2_Pos 2 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5648 #define GPIO_ODMER_P2 (_U_(0x1) << GPIO_ODMER_P2_Pos) 5649 #define GPIO_ODMER_P3_Pos 3 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5650 #define GPIO_ODMER_P3 (_U_(0x1) << GPIO_ODMER_P3_Pos) 5651 #define GPIO_ODMER_P4_Pos 4 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5652 #define GPIO_ODMER_P4 (_U_(0x1) << GPIO_ODMER_P4_Pos) 5653 #define GPIO_ODMER_P5_Pos 5 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5654 #define GPIO_ODMER_P5 (_U_(0x1) << GPIO_ODMER_P5_Pos) 5655 #define GPIO_ODMER_P6_Pos 6 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5656 #define GPIO_ODMER_P6 (_U_(0x1) << GPIO_ODMER_P6_Pos) 5657 #define GPIO_ODMER_P7_Pos 7 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5658 #define GPIO_ODMER_P7 (_U_(0x1) << GPIO_ODMER_P7_Pos) 5659 #define GPIO_ODMER_P8_Pos 8 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5660 #define GPIO_ODMER_P8 (_U_(0x1) << GPIO_ODMER_P8_Pos) 5661 #define GPIO_ODMER_P9_Pos 9 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5662 #define GPIO_ODMER_P9 (_U_(0x1) << GPIO_ODMER_P9_Pos) 5663 #define GPIO_ODMER_P10_Pos 10 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5664 #define GPIO_ODMER_P10 (_U_(0x1) << GPIO_ODMER_P10_Pos) 5665 #define GPIO_ODMER_P11_Pos 11 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5666 #define GPIO_ODMER_P11 (_U_(0x1) << GPIO_ODMER_P11_Pos) 5667 #define GPIO_ODMER_P12_Pos 12 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5668 #define GPIO_ODMER_P12 (_U_(0x1) << GPIO_ODMER_P12_Pos) 5669 #define GPIO_ODMER_P13_Pos 13 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5670 #define GPIO_ODMER_P13 (_U_(0x1) << GPIO_ODMER_P13_Pos) 5671 #define GPIO_ODMER_P14_Pos 14 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5672 #define GPIO_ODMER_P14 (_U_(0x1) << GPIO_ODMER_P14_Pos) 5673 #define GPIO_ODMER_P15_Pos 15 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5674 #define GPIO_ODMER_P15 (_U_(0x1) << GPIO_ODMER_P15_Pos) 5675 #define GPIO_ODMER_P16_Pos 16 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5676 #define GPIO_ODMER_P16 (_U_(0x1) << GPIO_ODMER_P16_Pos) 5677 #define GPIO_ODMER_P17_Pos 17 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5678 #define GPIO_ODMER_P17 (_U_(0x1) << GPIO_ODMER_P17_Pos) 5679 #define GPIO_ODMER_P18_Pos 18 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5680 #define GPIO_ODMER_P18 (_U_(0x1) << GPIO_ODMER_P18_Pos) 5681 #define GPIO_ODMER_P19_Pos 19 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5682 #define GPIO_ODMER_P19 (_U_(0x1) << GPIO_ODMER_P19_Pos) 5683 #define GPIO_ODMER_P20_Pos 20 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5684 #define GPIO_ODMER_P20 (_U_(0x1) << GPIO_ODMER_P20_Pos) 5685 #define GPIO_ODMER_P21_Pos 21 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5686 #define GPIO_ODMER_P21 (_U_(0x1) << GPIO_ODMER_P21_Pos) 5687 #define GPIO_ODMER_P22_Pos 22 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5688 #define GPIO_ODMER_P22 (_U_(0x1) << GPIO_ODMER_P22_Pos) 5689 #define GPIO_ODMER_P23_Pos 23 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5690 #define GPIO_ODMER_P23 (_U_(0x1) << GPIO_ODMER_P23_Pos) 5691 #define GPIO_ODMER_P24_Pos 24 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5692 #define GPIO_ODMER_P24 (_U_(0x1) << GPIO_ODMER_P24_Pos) 5693 #define GPIO_ODMER_P25_Pos 25 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5694 #define GPIO_ODMER_P25 (_U_(0x1) << GPIO_ODMER_P25_Pos) 5695 #define GPIO_ODMER_P26_Pos 26 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5696 #define GPIO_ODMER_P26 (_U_(0x1) << GPIO_ODMER_P26_Pos) 5697 #define GPIO_ODMER_P27_Pos 27 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5698 #define GPIO_ODMER_P27 (_U_(0x1) << GPIO_ODMER_P27_Pos) 5699 #define GPIO_ODMER_P28_Pos 28 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5700 #define GPIO_ODMER_P28 (_U_(0x1) << GPIO_ODMER_P28_Pos) 5701 #define GPIO_ODMER_P29_Pos 29 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5702 #define GPIO_ODMER_P29 (_U_(0x1) << GPIO_ODMER_P29_Pos) 5703 #define GPIO_ODMER_P30_Pos 30 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5704 #define GPIO_ODMER_P30 (_U_(0x1) << GPIO_ODMER_P30_Pos) 5705 #define GPIO_ODMER_P31_Pos 31 /**< \brief (GPIO_ODMER) Open Drain Mode Enable */ 5706 #define GPIO_ODMER_P31 (_U_(0x1) << GPIO_ODMER_P31_Pos) 5707 #define GPIO_ODMER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODMER) MASK Register */ 5708 5709 /* -------- GPIO_ODMERS : (GPIO Offset: 0x0E4) ( /W 32) port Open Drain Mode Register - Set -------- */ 5710 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5711 typedef union { 5712 struct { 5713 uint32_t P0:1; /*!< bit: 0 Open Drain Mode Enable */ 5714 uint32_t P1:1; /*!< bit: 1 Open Drain Mode Enable */ 5715 uint32_t P2:1; /*!< bit: 2 Open Drain Mode Enable */ 5716 uint32_t P3:1; /*!< bit: 3 Open Drain Mode Enable */ 5717 uint32_t P4:1; /*!< bit: 4 Open Drain Mode Enable */ 5718 uint32_t P5:1; /*!< bit: 5 Open Drain Mode Enable */ 5719 uint32_t P6:1; /*!< bit: 6 Open Drain Mode Enable */ 5720 uint32_t P7:1; /*!< bit: 7 Open Drain Mode Enable */ 5721 uint32_t P8:1; /*!< bit: 8 Open Drain Mode Enable */ 5722 uint32_t P9:1; /*!< bit: 9 Open Drain Mode Enable */ 5723 uint32_t P10:1; /*!< bit: 10 Open Drain Mode Enable */ 5724 uint32_t P11:1; /*!< bit: 11 Open Drain Mode Enable */ 5725 uint32_t P12:1; /*!< bit: 12 Open Drain Mode Enable */ 5726 uint32_t P13:1; /*!< bit: 13 Open Drain Mode Enable */ 5727 uint32_t P14:1; /*!< bit: 14 Open Drain Mode Enable */ 5728 uint32_t P15:1; /*!< bit: 15 Open Drain Mode Enable */ 5729 uint32_t P16:1; /*!< bit: 16 Open Drain Mode Enable */ 5730 uint32_t P17:1; /*!< bit: 17 Open Drain Mode Enable */ 5731 uint32_t P18:1; /*!< bit: 18 Open Drain Mode Enable */ 5732 uint32_t P19:1; /*!< bit: 19 Open Drain Mode Enable */ 5733 uint32_t P20:1; /*!< bit: 20 Open Drain Mode Enable */ 5734 uint32_t P21:1; /*!< bit: 21 Open Drain Mode Enable */ 5735 uint32_t P22:1; /*!< bit: 22 Open Drain Mode Enable */ 5736 uint32_t P23:1; /*!< bit: 23 Open Drain Mode Enable */ 5737 uint32_t P24:1; /*!< bit: 24 Open Drain Mode Enable */ 5738 uint32_t P25:1; /*!< bit: 25 Open Drain Mode Enable */ 5739 uint32_t P26:1; /*!< bit: 26 Open Drain Mode Enable */ 5740 uint32_t P27:1; /*!< bit: 27 Open Drain Mode Enable */ 5741 uint32_t P28:1; /*!< bit: 28 Open Drain Mode Enable */ 5742 uint32_t P29:1; /*!< bit: 29 Open Drain Mode Enable */ 5743 uint32_t P30:1; /*!< bit: 30 Open Drain Mode Enable */ 5744 uint32_t P31:1; /*!< bit: 31 Open Drain Mode Enable */ 5745 } bit; /*!< Structure used for bit access */ 5746 uint32_t reg; /*!< Type used for register access */ 5747 } GPIO_ODMERS_Type; 5748 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5749 5750 #define GPIO_ODMERS_OFFSET 0x0E4 /**< \brief (GPIO_ODMERS offset) Open Drain Mode Register - Set */ 5751 5752 #define GPIO_ODMERS_P0_Pos 0 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5753 #define GPIO_ODMERS_P0 (_U_(0x1) << GPIO_ODMERS_P0_Pos) 5754 #define GPIO_ODMERS_P1_Pos 1 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5755 #define GPIO_ODMERS_P1 (_U_(0x1) << GPIO_ODMERS_P1_Pos) 5756 #define GPIO_ODMERS_P2_Pos 2 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5757 #define GPIO_ODMERS_P2 (_U_(0x1) << GPIO_ODMERS_P2_Pos) 5758 #define GPIO_ODMERS_P3_Pos 3 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5759 #define GPIO_ODMERS_P3 (_U_(0x1) << GPIO_ODMERS_P3_Pos) 5760 #define GPIO_ODMERS_P4_Pos 4 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5761 #define GPIO_ODMERS_P4 (_U_(0x1) << GPIO_ODMERS_P4_Pos) 5762 #define GPIO_ODMERS_P5_Pos 5 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5763 #define GPIO_ODMERS_P5 (_U_(0x1) << GPIO_ODMERS_P5_Pos) 5764 #define GPIO_ODMERS_P6_Pos 6 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5765 #define GPIO_ODMERS_P6 (_U_(0x1) << GPIO_ODMERS_P6_Pos) 5766 #define GPIO_ODMERS_P7_Pos 7 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5767 #define GPIO_ODMERS_P7 (_U_(0x1) << GPIO_ODMERS_P7_Pos) 5768 #define GPIO_ODMERS_P8_Pos 8 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5769 #define GPIO_ODMERS_P8 (_U_(0x1) << GPIO_ODMERS_P8_Pos) 5770 #define GPIO_ODMERS_P9_Pos 9 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5771 #define GPIO_ODMERS_P9 (_U_(0x1) << GPIO_ODMERS_P9_Pos) 5772 #define GPIO_ODMERS_P10_Pos 10 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5773 #define GPIO_ODMERS_P10 (_U_(0x1) << GPIO_ODMERS_P10_Pos) 5774 #define GPIO_ODMERS_P11_Pos 11 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5775 #define GPIO_ODMERS_P11 (_U_(0x1) << GPIO_ODMERS_P11_Pos) 5776 #define GPIO_ODMERS_P12_Pos 12 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5777 #define GPIO_ODMERS_P12 (_U_(0x1) << GPIO_ODMERS_P12_Pos) 5778 #define GPIO_ODMERS_P13_Pos 13 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5779 #define GPIO_ODMERS_P13 (_U_(0x1) << GPIO_ODMERS_P13_Pos) 5780 #define GPIO_ODMERS_P14_Pos 14 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5781 #define GPIO_ODMERS_P14 (_U_(0x1) << GPIO_ODMERS_P14_Pos) 5782 #define GPIO_ODMERS_P15_Pos 15 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5783 #define GPIO_ODMERS_P15 (_U_(0x1) << GPIO_ODMERS_P15_Pos) 5784 #define GPIO_ODMERS_P16_Pos 16 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5785 #define GPIO_ODMERS_P16 (_U_(0x1) << GPIO_ODMERS_P16_Pos) 5786 #define GPIO_ODMERS_P17_Pos 17 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5787 #define GPIO_ODMERS_P17 (_U_(0x1) << GPIO_ODMERS_P17_Pos) 5788 #define GPIO_ODMERS_P18_Pos 18 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5789 #define GPIO_ODMERS_P18 (_U_(0x1) << GPIO_ODMERS_P18_Pos) 5790 #define GPIO_ODMERS_P19_Pos 19 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5791 #define GPIO_ODMERS_P19 (_U_(0x1) << GPIO_ODMERS_P19_Pos) 5792 #define GPIO_ODMERS_P20_Pos 20 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5793 #define GPIO_ODMERS_P20 (_U_(0x1) << GPIO_ODMERS_P20_Pos) 5794 #define GPIO_ODMERS_P21_Pos 21 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5795 #define GPIO_ODMERS_P21 (_U_(0x1) << GPIO_ODMERS_P21_Pos) 5796 #define GPIO_ODMERS_P22_Pos 22 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5797 #define GPIO_ODMERS_P22 (_U_(0x1) << GPIO_ODMERS_P22_Pos) 5798 #define GPIO_ODMERS_P23_Pos 23 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5799 #define GPIO_ODMERS_P23 (_U_(0x1) << GPIO_ODMERS_P23_Pos) 5800 #define GPIO_ODMERS_P24_Pos 24 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5801 #define GPIO_ODMERS_P24 (_U_(0x1) << GPIO_ODMERS_P24_Pos) 5802 #define GPIO_ODMERS_P25_Pos 25 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5803 #define GPIO_ODMERS_P25 (_U_(0x1) << GPIO_ODMERS_P25_Pos) 5804 #define GPIO_ODMERS_P26_Pos 26 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5805 #define GPIO_ODMERS_P26 (_U_(0x1) << GPIO_ODMERS_P26_Pos) 5806 #define GPIO_ODMERS_P27_Pos 27 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5807 #define GPIO_ODMERS_P27 (_U_(0x1) << GPIO_ODMERS_P27_Pos) 5808 #define GPIO_ODMERS_P28_Pos 28 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5809 #define GPIO_ODMERS_P28 (_U_(0x1) << GPIO_ODMERS_P28_Pos) 5810 #define GPIO_ODMERS_P29_Pos 29 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5811 #define GPIO_ODMERS_P29 (_U_(0x1) << GPIO_ODMERS_P29_Pos) 5812 #define GPIO_ODMERS_P30_Pos 30 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5813 #define GPIO_ODMERS_P30 (_U_(0x1) << GPIO_ODMERS_P30_Pos) 5814 #define GPIO_ODMERS_P31_Pos 31 /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */ 5815 #define GPIO_ODMERS_P31 (_U_(0x1) << GPIO_ODMERS_P31_Pos) 5816 #define GPIO_ODMERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODMERS) MASK Register */ 5817 5818 /* -------- GPIO_ODMERC : (GPIO Offset: 0x0E8) ( /W 32) port Open Drain Mode Register - Clear -------- */ 5819 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5820 typedef union { 5821 struct { 5822 uint32_t P0:1; /*!< bit: 0 Open Drain Mode Enable */ 5823 uint32_t P1:1; /*!< bit: 1 Open Drain Mode Enable */ 5824 uint32_t P2:1; /*!< bit: 2 Open Drain Mode Enable */ 5825 uint32_t P3:1; /*!< bit: 3 Open Drain Mode Enable */ 5826 uint32_t P4:1; /*!< bit: 4 Open Drain Mode Enable */ 5827 uint32_t P5:1; /*!< bit: 5 Open Drain Mode Enable */ 5828 uint32_t P6:1; /*!< bit: 6 Open Drain Mode Enable */ 5829 uint32_t P7:1; /*!< bit: 7 Open Drain Mode Enable */ 5830 uint32_t P8:1; /*!< bit: 8 Open Drain Mode Enable */ 5831 uint32_t P9:1; /*!< bit: 9 Open Drain Mode Enable */ 5832 uint32_t P10:1; /*!< bit: 10 Open Drain Mode Enable */ 5833 uint32_t P11:1; /*!< bit: 11 Open Drain Mode Enable */ 5834 uint32_t P12:1; /*!< bit: 12 Open Drain Mode Enable */ 5835 uint32_t P13:1; /*!< bit: 13 Open Drain Mode Enable */ 5836 uint32_t P14:1; /*!< bit: 14 Open Drain Mode Enable */ 5837 uint32_t P15:1; /*!< bit: 15 Open Drain Mode Enable */ 5838 uint32_t P16:1; /*!< bit: 16 Open Drain Mode Enable */ 5839 uint32_t P17:1; /*!< bit: 17 Open Drain Mode Enable */ 5840 uint32_t P18:1; /*!< bit: 18 Open Drain Mode Enable */ 5841 uint32_t P19:1; /*!< bit: 19 Open Drain Mode Enable */ 5842 uint32_t P20:1; /*!< bit: 20 Open Drain Mode Enable */ 5843 uint32_t P21:1; /*!< bit: 21 Open Drain Mode Enable */ 5844 uint32_t P22:1; /*!< bit: 22 Open Drain Mode Enable */ 5845 uint32_t P23:1; /*!< bit: 23 Open Drain Mode Enable */ 5846 uint32_t P24:1; /*!< bit: 24 Open Drain Mode Enable */ 5847 uint32_t P25:1; /*!< bit: 25 Open Drain Mode Enable */ 5848 uint32_t P26:1; /*!< bit: 26 Open Drain Mode Enable */ 5849 uint32_t P27:1; /*!< bit: 27 Open Drain Mode Enable */ 5850 uint32_t P28:1; /*!< bit: 28 Open Drain Mode Enable */ 5851 uint32_t P29:1; /*!< bit: 29 Open Drain Mode Enable */ 5852 uint32_t P30:1; /*!< bit: 30 Open Drain Mode Enable */ 5853 uint32_t P31:1; /*!< bit: 31 Open Drain Mode Enable */ 5854 } bit; /*!< Structure used for bit access */ 5855 uint32_t reg; /*!< Type used for register access */ 5856 } GPIO_ODMERC_Type; 5857 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5858 5859 #define GPIO_ODMERC_OFFSET 0x0E8 /**< \brief (GPIO_ODMERC offset) Open Drain Mode Register - Clear */ 5860 5861 #define GPIO_ODMERC_P0_Pos 0 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5862 #define GPIO_ODMERC_P0 (_U_(0x1) << GPIO_ODMERC_P0_Pos) 5863 #define GPIO_ODMERC_P1_Pos 1 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5864 #define GPIO_ODMERC_P1 (_U_(0x1) << GPIO_ODMERC_P1_Pos) 5865 #define GPIO_ODMERC_P2_Pos 2 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5866 #define GPIO_ODMERC_P2 (_U_(0x1) << GPIO_ODMERC_P2_Pos) 5867 #define GPIO_ODMERC_P3_Pos 3 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5868 #define GPIO_ODMERC_P3 (_U_(0x1) << GPIO_ODMERC_P3_Pos) 5869 #define GPIO_ODMERC_P4_Pos 4 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5870 #define GPIO_ODMERC_P4 (_U_(0x1) << GPIO_ODMERC_P4_Pos) 5871 #define GPIO_ODMERC_P5_Pos 5 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5872 #define GPIO_ODMERC_P5 (_U_(0x1) << GPIO_ODMERC_P5_Pos) 5873 #define GPIO_ODMERC_P6_Pos 6 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5874 #define GPIO_ODMERC_P6 (_U_(0x1) << GPIO_ODMERC_P6_Pos) 5875 #define GPIO_ODMERC_P7_Pos 7 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5876 #define GPIO_ODMERC_P7 (_U_(0x1) << GPIO_ODMERC_P7_Pos) 5877 #define GPIO_ODMERC_P8_Pos 8 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5878 #define GPIO_ODMERC_P8 (_U_(0x1) << GPIO_ODMERC_P8_Pos) 5879 #define GPIO_ODMERC_P9_Pos 9 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5880 #define GPIO_ODMERC_P9 (_U_(0x1) << GPIO_ODMERC_P9_Pos) 5881 #define GPIO_ODMERC_P10_Pos 10 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5882 #define GPIO_ODMERC_P10 (_U_(0x1) << GPIO_ODMERC_P10_Pos) 5883 #define GPIO_ODMERC_P11_Pos 11 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5884 #define GPIO_ODMERC_P11 (_U_(0x1) << GPIO_ODMERC_P11_Pos) 5885 #define GPIO_ODMERC_P12_Pos 12 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5886 #define GPIO_ODMERC_P12 (_U_(0x1) << GPIO_ODMERC_P12_Pos) 5887 #define GPIO_ODMERC_P13_Pos 13 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5888 #define GPIO_ODMERC_P13 (_U_(0x1) << GPIO_ODMERC_P13_Pos) 5889 #define GPIO_ODMERC_P14_Pos 14 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5890 #define GPIO_ODMERC_P14 (_U_(0x1) << GPIO_ODMERC_P14_Pos) 5891 #define GPIO_ODMERC_P15_Pos 15 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5892 #define GPIO_ODMERC_P15 (_U_(0x1) << GPIO_ODMERC_P15_Pos) 5893 #define GPIO_ODMERC_P16_Pos 16 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5894 #define GPIO_ODMERC_P16 (_U_(0x1) << GPIO_ODMERC_P16_Pos) 5895 #define GPIO_ODMERC_P17_Pos 17 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5896 #define GPIO_ODMERC_P17 (_U_(0x1) << GPIO_ODMERC_P17_Pos) 5897 #define GPIO_ODMERC_P18_Pos 18 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5898 #define GPIO_ODMERC_P18 (_U_(0x1) << GPIO_ODMERC_P18_Pos) 5899 #define GPIO_ODMERC_P19_Pos 19 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5900 #define GPIO_ODMERC_P19 (_U_(0x1) << GPIO_ODMERC_P19_Pos) 5901 #define GPIO_ODMERC_P20_Pos 20 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5902 #define GPIO_ODMERC_P20 (_U_(0x1) << GPIO_ODMERC_P20_Pos) 5903 #define GPIO_ODMERC_P21_Pos 21 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5904 #define GPIO_ODMERC_P21 (_U_(0x1) << GPIO_ODMERC_P21_Pos) 5905 #define GPIO_ODMERC_P22_Pos 22 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5906 #define GPIO_ODMERC_P22 (_U_(0x1) << GPIO_ODMERC_P22_Pos) 5907 #define GPIO_ODMERC_P23_Pos 23 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5908 #define GPIO_ODMERC_P23 (_U_(0x1) << GPIO_ODMERC_P23_Pos) 5909 #define GPIO_ODMERC_P24_Pos 24 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5910 #define GPIO_ODMERC_P24 (_U_(0x1) << GPIO_ODMERC_P24_Pos) 5911 #define GPIO_ODMERC_P25_Pos 25 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5912 #define GPIO_ODMERC_P25 (_U_(0x1) << GPIO_ODMERC_P25_Pos) 5913 #define GPIO_ODMERC_P26_Pos 26 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5914 #define GPIO_ODMERC_P26 (_U_(0x1) << GPIO_ODMERC_P26_Pos) 5915 #define GPIO_ODMERC_P27_Pos 27 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5916 #define GPIO_ODMERC_P27 (_U_(0x1) << GPIO_ODMERC_P27_Pos) 5917 #define GPIO_ODMERC_P28_Pos 28 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5918 #define GPIO_ODMERC_P28 (_U_(0x1) << GPIO_ODMERC_P28_Pos) 5919 #define GPIO_ODMERC_P29_Pos 29 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5920 #define GPIO_ODMERC_P29 (_U_(0x1) << GPIO_ODMERC_P29_Pos) 5921 #define GPIO_ODMERC_P30_Pos 30 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5922 #define GPIO_ODMERC_P30 (_U_(0x1) << GPIO_ODMERC_P30_Pos) 5923 #define GPIO_ODMERC_P31_Pos 31 /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */ 5924 #define GPIO_ODMERC_P31 (_U_(0x1) << GPIO_ODMERC_P31_Pos) 5925 #define GPIO_ODMERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODMERC) MASK Register */ 5926 5927 /* -------- GPIO_ODMERT : (GPIO Offset: 0x0EC) ( /W 32) port Open Drain Mode Register - Toggle -------- */ 5928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5929 typedef union { 5930 struct { 5931 uint32_t P0:1; /*!< bit: 0 Open Drain Mode Enable */ 5932 uint32_t P1:1; /*!< bit: 1 Open Drain Mode Enable */ 5933 uint32_t P2:1; /*!< bit: 2 Open Drain Mode Enable */ 5934 uint32_t P3:1; /*!< bit: 3 Open Drain Mode Enable */ 5935 uint32_t P4:1; /*!< bit: 4 Open Drain Mode Enable */ 5936 uint32_t P5:1; /*!< bit: 5 Open Drain Mode Enable */ 5937 uint32_t P6:1; /*!< bit: 6 Open Drain Mode Enable */ 5938 uint32_t P7:1; /*!< bit: 7 Open Drain Mode Enable */ 5939 uint32_t P8:1; /*!< bit: 8 Open Drain Mode Enable */ 5940 uint32_t P9:1; /*!< bit: 9 Open Drain Mode Enable */ 5941 uint32_t P10:1; /*!< bit: 10 Open Drain Mode Enable */ 5942 uint32_t P11:1; /*!< bit: 11 Open Drain Mode Enable */ 5943 uint32_t P12:1; /*!< bit: 12 Open Drain Mode Enable */ 5944 uint32_t P13:1; /*!< bit: 13 Open Drain Mode Enable */ 5945 uint32_t P14:1; /*!< bit: 14 Open Drain Mode Enable */ 5946 uint32_t P15:1; /*!< bit: 15 Open Drain Mode Enable */ 5947 uint32_t P16:1; /*!< bit: 16 Open Drain Mode Enable */ 5948 uint32_t P17:1; /*!< bit: 17 Open Drain Mode Enable */ 5949 uint32_t P18:1; /*!< bit: 18 Open Drain Mode Enable */ 5950 uint32_t P19:1; /*!< bit: 19 Open Drain Mode Enable */ 5951 uint32_t P20:1; /*!< bit: 20 Open Drain Mode Enable */ 5952 uint32_t P21:1; /*!< bit: 21 Open Drain Mode Enable */ 5953 uint32_t P22:1; /*!< bit: 22 Open Drain Mode Enable */ 5954 uint32_t P23:1; /*!< bit: 23 Open Drain Mode Enable */ 5955 uint32_t P24:1; /*!< bit: 24 Open Drain Mode Enable */ 5956 uint32_t P25:1; /*!< bit: 25 Open Drain Mode Enable */ 5957 uint32_t P26:1; /*!< bit: 26 Open Drain Mode Enable */ 5958 uint32_t P27:1; /*!< bit: 27 Open Drain Mode Enable */ 5959 uint32_t P28:1; /*!< bit: 28 Open Drain Mode Enable */ 5960 uint32_t P29:1; /*!< bit: 29 Open Drain Mode Enable */ 5961 uint32_t P30:1; /*!< bit: 30 Open Drain Mode Enable */ 5962 uint32_t P31:1; /*!< bit: 31 Open Drain Mode Enable */ 5963 } bit; /*!< Structure used for bit access */ 5964 uint32_t reg; /*!< Type used for register access */ 5965 } GPIO_ODMERT_Type; 5966 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5967 5968 #define GPIO_ODMERT_OFFSET 0x0EC /**< \brief (GPIO_ODMERT offset) Open Drain Mode Register - Toggle */ 5969 5970 #define GPIO_ODMERT_P0_Pos 0 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5971 #define GPIO_ODMERT_P0 (_U_(0x1) << GPIO_ODMERT_P0_Pos) 5972 #define GPIO_ODMERT_P1_Pos 1 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5973 #define GPIO_ODMERT_P1 (_U_(0x1) << GPIO_ODMERT_P1_Pos) 5974 #define GPIO_ODMERT_P2_Pos 2 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5975 #define GPIO_ODMERT_P2 (_U_(0x1) << GPIO_ODMERT_P2_Pos) 5976 #define GPIO_ODMERT_P3_Pos 3 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5977 #define GPIO_ODMERT_P3 (_U_(0x1) << GPIO_ODMERT_P3_Pos) 5978 #define GPIO_ODMERT_P4_Pos 4 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5979 #define GPIO_ODMERT_P4 (_U_(0x1) << GPIO_ODMERT_P4_Pos) 5980 #define GPIO_ODMERT_P5_Pos 5 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5981 #define GPIO_ODMERT_P5 (_U_(0x1) << GPIO_ODMERT_P5_Pos) 5982 #define GPIO_ODMERT_P6_Pos 6 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5983 #define GPIO_ODMERT_P6 (_U_(0x1) << GPIO_ODMERT_P6_Pos) 5984 #define GPIO_ODMERT_P7_Pos 7 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5985 #define GPIO_ODMERT_P7 (_U_(0x1) << GPIO_ODMERT_P7_Pos) 5986 #define GPIO_ODMERT_P8_Pos 8 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5987 #define GPIO_ODMERT_P8 (_U_(0x1) << GPIO_ODMERT_P8_Pos) 5988 #define GPIO_ODMERT_P9_Pos 9 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5989 #define GPIO_ODMERT_P9 (_U_(0x1) << GPIO_ODMERT_P9_Pos) 5990 #define GPIO_ODMERT_P10_Pos 10 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5991 #define GPIO_ODMERT_P10 (_U_(0x1) << GPIO_ODMERT_P10_Pos) 5992 #define GPIO_ODMERT_P11_Pos 11 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5993 #define GPIO_ODMERT_P11 (_U_(0x1) << GPIO_ODMERT_P11_Pos) 5994 #define GPIO_ODMERT_P12_Pos 12 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5995 #define GPIO_ODMERT_P12 (_U_(0x1) << GPIO_ODMERT_P12_Pos) 5996 #define GPIO_ODMERT_P13_Pos 13 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5997 #define GPIO_ODMERT_P13 (_U_(0x1) << GPIO_ODMERT_P13_Pos) 5998 #define GPIO_ODMERT_P14_Pos 14 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 5999 #define GPIO_ODMERT_P14 (_U_(0x1) << GPIO_ODMERT_P14_Pos) 6000 #define GPIO_ODMERT_P15_Pos 15 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6001 #define GPIO_ODMERT_P15 (_U_(0x1) << GPIO_ODMERT_P15_Pos) 6002 #define GPIO_ODMERT_P16_Pos 16 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6003 #define GPIO_ODMERT_P16 (_U_(0x1) << GPIO_ODMERT_P16_Pos) 6004 #define GPIO_ODMERT_P17_Pos 17 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6005 #define GPIO_ODMERT_P17 (_U_(0x1) << GPIO_ODMERT_P17_Pos) 6006 #define GPIO_ODMERT_P18_Pos 18 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6007 #define GPIO_ODMERT_P18 (_U_(0x1) << GPIO_ODMERT_P18_Pos) 6008 #define GPIO_ODMERT_P19_Pos 19 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6009 #define GPIO_ODMERT_P19 (_U_(0x1) << GPIO_ODMERT_P19_Pos) 6010 #define GPIO_ODMERT_P20_Pos 20 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6011 #define GPIO_ODMERT_P20 (_U_(0x1) << GPIO_ODMERT_P20_Pos) 6012 #define GPIO_ODMERT_P21_Pos 21 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6013 #define GPIO_ODMERT_P21 (_U_(0x1) << GPIO_ODMERT_P21_Pos) 6014 #define GPIO_ODMERT_P22_Pos 22 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6015 #define GPIO_ODMERT_P22 (_U_(0x1) << GPIO_ODMERT_P22_Pos) 6016 #define GPIO_ODMERT_P23_Pos 23 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6017 #define GPIO_ODMERT_P23 (_U_(0x1) << GPIO_ODMERT_P23_Pos) 6018 #define GPIO_ODMERT_P24_Pos 24 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6019 #define GPIO_ODMERT_P24 (_U_(0x1) << GPIO_ODMERT_P24_Pos) 6020 #define GPIO_ODMERT_P25_Pos 25 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6021 #define GPIO_ODMERT_P25 (_U_(0x1) << GPIO_ODMERT_P25_Pos) 6022 #define GPIO_ODMERT_P26_Pos 26 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6023 #define GPIO_ODMERT_P26 (_U_(0x1) << GPIO_ODMERT_P26_Pos) 6024 #define GPIO_ODMERT_P27_Pos 27 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6025 #define GPIO_ODMERT_P27 (_U_(0x1) << GPIO_ODMERT_P27_Pos) 6026 #define GPIO_ODMERT_P28_Pos 28 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6027 #define GPIO_ODMERT_P28 (_U_(0x1) << GPIO_ODMERT_P28_Pos) 6028 #define GPIO_ODMERT_P29_Pos 29 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6029 #define GPIO_ODMERT_P29 (_U_(0x1) << GPIO_ODMERT_P29_Pos) 6030 #define GPIO_ODMERT_P30_Pos 30 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6031 #define GPIO_ODMERT_P30 (_U_(0x1) << GPIO_ODMERT_P30_Pos) 6032 #define GPIO_ODMERT_P31_Pos 31 /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */ 6033 #define GPIO_ODMERT_P31 (_U_(0x1) << GPIO_ODMERT_P31_Pos) 6034 #define GPIO_ODMERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODMERT) MASK Register */ 6035 6036 /* -------- GPIO_ODCR0 : (GPIO Offset: 0x100) (R/W 32) port Output Driving Capability Register 0 -------- */ 6037 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6038 typedef union { 6039 struct { 6040 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 0 */ 6041 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 0 */ 6042 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 0 */ 6043 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 0 */ 6044 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 0 */ 6045 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 0 */ 6046 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 0 */ 6047 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 0 */ 6048 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 0 */ 6049 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 0 */ 6050 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 0 */ 6051 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 0 */ 6052 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 0 */ 6053 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 0 */ 6054 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 0 */ 6055 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 0 */ 6056 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 0 */ 6057 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 0 */ 6058 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 0 */ 6059 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 0 */ 6060 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 0 */ 6061 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 0 */ 6062 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 0 */ 6063 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 0 */ 6064 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 0 */ 6065 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 0 */ 6066 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 0 */ 6067 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 0 */ 6068 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 0 */ 6069 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 0 */ 6070 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 0 */ 6071 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 0 */ 6072 } bit; /*!< Structure used for bit access */ 6073 uint32_t reg; /*!< Type used for register access */ 6074 } GPIO_ODCR0_Type; 6075 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6076 6077 #define GPIO_ODCR0_OFFSET 0x100 /**< \brief (GPIO_ODCR0 offset) Output Driving Capability Register 0 */ 6078 6079 #define GPIO_ODCR0_P0_Pos 0 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6080 #define GPIO_ODCR0_P0 (_U_(0x1) << GPIO_ODCR0_P0_Pos) 6081 #define GPIO_ODCR0_P1_Pos 1 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6082 #define GPIO_ODCR0_P1 (_U_(0x1) << GPIO_ODCR0_P1_Pos) 6083 #define GPIO_ODCR0_P2_Pos 2 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6084 #define GPIO_ODCR0_P2 (_U_(0x1) << GPIO_ODCR0_P2_Pos) 6085 #define GPIO_ODCR0_P3_Pos 3 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6086 #define GPIO_ODCR0_P3 (_U_(0x1) << GPIO_ODCR0_P3_Pos) 6087 #define GPIO_ODCR0_P4_Pos 4 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6088 #define GPIO_ODCR0_P4 (_U_(0x1) << GPIO_ODCR0_P4_Pos) 6089 #define GPIO_ODCR0_P5_Pos 5 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6090 #define GPIO_ODCR0_P5 (_U_(0x1) << GPIO_ODCR0_P5_Pos) 6091 #define GPIO_ODCR0_P6_Pos 6 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6092 #define GPIO_ODCR0_P6 (_U_(0x1) << GPIO_ODCR0_P6_Pos) 6093 #define GPIO_ODCR0_P7_Pos 7 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6094 #define GPIO_ODCR0_P7 (_U_(0x1) << GPIO_ODCR0_P7_Pos) 6095 #define GPIO_ODCR0_P8_Pos 8 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6096 #define GPIO_ODCR0_P8 (_U_(0x1) << GPIO_ODCR0_P8_Pos) 6097 #define GPIO_ODCR0_P9_Pos 9 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6098 #define GPIO_ODCR0_P9 (_U_(0x1) << GPIO_ODCR0_P9_Pos) 6099 #define GPIO_ODCR0_P10_Pos 10 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6100 #define GPIO_ODCR0_P10 (_U_(0x1) << GPIO_ODCR0_P10_Pos) 6101 #define GPIO_ODCR0_P11_Pos 11 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6102 #define GPIO_ODCR0_P11 (_U_(0x1) << GPIO_ODCR0_P11_Pos) 6103 #define GPIO_ODCR0_P12_Pos 12 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6104 #define GPIO_ODCR0_P12 (_U_(0x1) << GPIO_ODCR0_P12_Pos) 6105 #define GPIO_ODCR0_P13_Pos 13 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6106 #define GPIO_ODCR0_P13 (_U_(0x1) << GPIO_ODCR0_P13_Pos) 6107 #define GPIO_ODCR0_P14_Pos 14 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6108 #define GPIO_ODCR0_P14 (_U_(0x1) << GPIO_ODCR0_P14_Pos) 6109 #define GPIO_ODCR0_P15_Pos 15 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6110 #define GPIO_ODCR0_P15 (_U_(0x1) << GPIO_ODCR0_P15_Pos) 6111 #define GPIO_ODCR0_P16_Pos 16 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6112 #define GPIO_ODCR0_P16 (_U_(0x1) << GPIO_ODCR0_P16_Pos) 6113 #define GPIO_ODCR0_P17_Pos 17 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6114 #define GPIO_ODCR0_P17 (_U_(0x1) << GPIO_ODCR0_P17_Pos) 6115 #define GPIO_ODCR0_P18_Pos 18 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6116 #define GPIO_ODCR0_P18 (_U_(0x1) << GPIO_ODCR0_P18_Pos) 6117 #define GPIO_ODCR0_P19_Pos 19 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6118 #define GPIO_ODCR0_P19 (_U_(0x1) << GPIO_ODCR0_P19_Pos) 6119 #define GPIO_ODCR0_P20_Pos 20 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6120 #define GPIO_ODCR0_P20 (_U_(0x1) << GPIO_ODCR0_P20_Pos) 6121 #define GPIO_ODCR0_P21_Pos 21 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6122 #define GPIO_ODCR0_P21 (_U_(0x1) << GPIO_ODCR0_P21_Pos) 6123 #define GPIO_ODCR0_P22_Pos 22 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6124 #define GPIO_ODCR0_P22 (_U_(0x1) << GPIO_ODCR0_P22_Pos) 6125 #define GPIO_ODCR0_P23_Pos 23 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6126 #define GPIO_ODCR0_P23 (_U_(0x1) << GPIO_ODCR0_P23_Pos) 6127 #define GPIO_ODCR0_P24_Pos 24 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6128 #define GPIO_ODCR0_P24 (_U_(0x1) << GPIO_ODCR0_P24_Pos) 6129 #define GPIO_ODCR0_P25_Pos 25 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6130 #define GPIO_ODCR0_P25 (_U_(0x1) << GPIO_ODCR0_P25_Pos) 6131 #define GPIO_ODCR0_P26_Pos 26 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6132 #define GPIO_ODCR0_P26 (_U_(0x1) << GPIO_ODCR0_P26_Pos) 6133 #define GPIO_ODCR0_P27_Pos 27 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6134 #define GPIO_ODCR0_P27 (_U_(0x1) << GPIO_ODCR0_P27_Pos) 6135 #define GPIO_ODCR0_P28_Pos 28 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6136 #define GPIO_ODCR0_P28 (_U_(0x1) << GPIO_ODCR0_P28_Pos) 6137 #define GPIO_ODCR0_P29_Pos 29 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6138 #define GPIO_ODCR0_P29 (_U_(0x1) << GPIO_ODCR0_P29_Pos) 6139 #define GPIO_ODCR0_P30_Pos 30 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6140 #define GPIO_ODCR0_P30 (_U_(0x1) << GPIO_ODCR0_P30_Pos) 6141 #define GPIO_ODCR0_P31_Pos 31 /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */ 6142 #define GPIO_ODCR0_P31 (_U_(0x1) << GPIO_ODCR0_P31_Pos) 6143 #define GPIO_ODCR0_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR0) MASK Register */ 6144 6145 /* -------- GPIO_ODCR0S : (GPIO Offset: 0x104) (R/W 32) port Output Driving Capability Register 0 - Set -------- */ 6146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6147 typedef union { 6148 struct { 6149 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 0 */ 6150 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 0 */ 6151 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 0 */ 6152 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 0 */ 6153 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 0 */ 6154 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 0 */ 6155 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 0 */ 6156 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 0 */ 6157 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 0 */ 6158 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 0 */ 6159 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 0 */ 6160 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 0 */ 6161 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 0 */ 6162 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 0 */ 6163 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 0 */ 6164 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 0 */ 6165 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 0 */ 6166 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 0 */ 6167 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 0 */ 6168 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 0 */ 6169 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 0 */ 6170 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 0 */ 6171 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 0 */ 6172 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 0 */ 6173 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 0 */ 6174 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 0 */ 6175 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 0 */ 6176 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 0 */ 6177 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 0 */ 6178 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 0 */ 6179 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 0 */ 6180 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 0 */ 6181 } bit; /*!< Structure used for bit access */ 6182 uint32_t reg; /*!< Type used for register access */ 6183 } GPIO_ODCR0S_Type; 6184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6185 6186 #define GPIO_ODCR0S_OFFSET 0x104 /**< \brief (GPIO_ODCR0S offset) Output Driving Capability Register 0 - Set */ 6187 6188 #define GPIO_ODCR0S_P0_Pos 0 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6189 #define GPIO_ODCR0S_P0 (_U_(0x1) << GPIO_ODCR0S_P0_Pos) 6190 #define GPIO_ODCR0S_P1_Pos 1 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6191 #define GPIO_ODCR0S_P1 (_U_(0x1) << GPIO_ODCR0S_P1_Pos) 6192 #define GPIO_ODCR0S_P2_Pos 2 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6193 #define GPIO_ODCR0S_P2 (_U_(0x1) << GPIO_ODCR0S_P2_Pos) 6194 #define GPIO_ODCR0S_P3_Pos 3 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6195 #define GPIO_ODCR0S_P3 (_U_(0x1) << GPIO_ODCR0S_P3_Pos) 6196 #define GPIO_ODCR0S_P4_Pos 4 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6197 #define GPIO_ODCR0S_P4 (_U_(0x1) << GPIO_ODCR0S_P4_Pos) 6198 #define GPIO_ODCR0S_P5_Pos 5 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6199 #define GPIO_ODCR0S_P5 (_U_(0x1) << GPIO_ODCR0S_P5_Pos) 6200 #define GPIO_ODCR0S_P6_Pos 6 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6201 #define GPIO_ODCR0S_P6 (_U_(0x1) << GPIO_ODCR0S_P6_Pos) 6202 #define GPIO_ODCR0S_P7_Pos 7 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6203 #define GPIO_ODCR0S_P7 (_U_(0x1) << GPIO_ODCR0S_P7_Pos) 6204 #define GPIO_ODCR0S_P8_Pos 8 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6205 #define GPIO_ODCR0S_P8 (_U_(0x1) << GPIO_ODCR0S_P8_Pos) 6206 #define GPIO_ODCR0S_P9_Pos 9 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6207 #define GPIO_ODCR0S_P9 (_U_(0x1) << GPIO_ODCR0S_P9_Pos) 6208 #define GPIO_ODCR0S_P10_Pos 10 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6209 #define GPIO_ODCR0S_P10 (_U_(0x1) << GPIO_ODCR0S_P10_Pos) 6210 #define GPIO_ODCR0S_P11_Pos 11 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6211 #define GPIO_ODCR0S_P11 (_U_(0x1) << GPIO_ODCR0S_P11_Pos) 6212 #define GPIO_ODCR0S_P12_Pos 12 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6213 #define GPIO_ODCR0S_P12 (_U_(0x1) << GPIO_ODCR0S_P12_Pos) 6214 #define GPIO_ODCR0S_P13_Pos 13 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6215 #define GPIO_ODCR0S_P13 (_U_(0x1) << GPIO_ODCR0S_P13_Pos) 6216 #define GPIO_ODCR0S_P14_Pos 14 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6217 #define GPIO_ODCR0S_P14 (_U_(0x1) << GPIO_ODCR0S_P14_Pos) 6218 #define GPIO_ODCR0S_P15_Pos 15 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6219 #define GPIO_ODCR0S_P15 (_U_(0x1) << GPIO_ODCR0S_P15_Pos) 6220 #define GPIO_ODCR0S_P16_Pos 16 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6221 #define GPIO_ODCR0S_P16 (_U_(0x1) << GPIO_ODCR0S_P16_Pos) 6222 #define GPIO_ODCR0S_P17_Pos 17 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6223 #define GPIO_ODCR0S_P17 (_U_(0x1) << GPIO_ODCR0S_P17_Pos) 6224 #define GPIO_ODCR0S_P18_Pos 18 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6225 #define GPIO_ODCR0S_P18 (_U_(0x1) << GPIO_ODCR0S_P18_Pos) 6226 #define GPIO_ODCR0S_P19_Pos 19 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6227 #define GPIO_ODCR0S_P19 (_U_(0x1) << GPIO_ODCR0S_P19_Pos) 6228 #define GPIO_ODCR0S_P20_Pos 20 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6229 #define GPIO_ODCR0S_P20 (_U_(0x1) << GPIO_ODCR0S_P20_Pos) 6230 #define GPIO_ODCR0S_P21_Pos 21 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6231 #define GPIO_ODCR0S_P21 (_U_(0x1) << GPIO_ODCR0S_P21_Pos) 6232 #define GPIO_ODCR0S_P22_Pos 22 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6233 #define GPIO_ODCR0S_P22 (_U_(0x1) << GPIO_ODCR0S_P22_Pos) 6234 #define GPIO_ODCR0S_P23_Pos 23 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6235 #define GPIO_ODCR0S_P23 (_U_(0x1) << GPIO_ODCR0S_P23_Pos) 6236 #define GPIO_ODCR0S_P24_Pos 24 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6237 #define GPIO_ODCR0S_P24 (_U_(0x1) << GPIO_ODCR0S_P24_Pos) 6238 #define GPIO_ODCR0S_P25_Pos 25 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6239 #define GPIO_ODCR0S_P25 (_U_(0x1) << GPIO_ODCR0S_P25_Pos) 6240 #define GPIO_ODCR0S_P26_Pos 26 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6241 #define GPIO_ODCR0S_P26 (_U_(0x1) << GPIO_ODCR0S_P26_Pos) 6242 #define GPIO_ODCR0S_P27_Pos 27 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6243 #define GPIO_ODCR0S_P27 (_U_(0x1) << GPIO_ODCR0S_P27_Pos) 6244 #define GPIO_ODCR0S_P28_Pos 28 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6245 #define GPIO_ODCR0S_P28 (_U_(0x1) << GPIO_ODCR0S_P28_Pos) 6246 #define GPIO_ODCR0S_P29_Pos 29 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6247 #define GPIO_ODCR0S_P29 (_U_(0x1) << GPIO_ODCR0S_P29_Pos) 6248 #define GPIO_ODCR0S_P30_Pos 30 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6249 #define GPIO_ODCR0S_P30 (_U_(0x1) << GPIO_ODCR0S_P30_Pos) 6250 #define GPIO_ODCR0S_P31_Pos 31 /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */ 6251 #define GPIO_ODCR0S_P31 (_U_(0x1) << GPIO_ODCR0S_P31_Pos) 6252 #define GPIO_ODCR0S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR0S) MASK Register */ 6253 6254 /* -------- GPIO_ODCR0C : (GPIO Offset: 0x108) (R/W 32) port Output Driving Capability Register 0 - Clear -------- */ 6255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6256 typedef union { 6257 struct { 6258 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 0 */ 6259 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 0 */ 6260 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 0 */ 6261 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 0 */ 6262 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 0 */ 6263 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 0 */ 6264 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 0 */ 6265 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 0 */ 6266 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 0 */ 6267 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 0 */ 6268 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 0 */ 6269 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 0 */ 6270 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 0 */ 6271 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 0 */ 6272 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 0 */ 6273 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 0 */ 6274 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 0 */ 6275 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 0 */ 6276 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 0 */ 6277 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 0 */ 6278 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 0 */ 6279 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 0 */ 6280 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 0 */ 6281 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 0 */ 6282 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 0 */ 6283 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 0 */ 6284 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 0 */ 6285 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 0 */ 6286 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 0 */ 6287 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 0 */ 6288 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 0 */ 6289 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 0 */ 6290 } bit; /*!< Structure used for bit access */ 6291 uint32_t reg; /*!< Type used for register access */ 6292 } GPIO_ODCR0C_Type; 6293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6294 6295 #define GPIO_ODCR0C_OFFSET 0x108 /**< \brief (GPIO_ODCR0C offset) Output Driving Capability Register 0 - Clear */ 6296 6297 #define GPIO_ODCR0C_P0_Pos 0 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6298 #define GPIO_ODCR0C_P0 (_U_(0x1) << GPIO_ODCR0C_P0_Pos) 6299 #define GPIO_ODCR0C_P1_Pos 1 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6300 #define GPIO_ODCR0C_P1 (_U_(0x1) << GPIO_ODCR0C_P1_Pos) 6301 #define GPIO_ODCR0C_P2_Pos 2 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6302 #define GPIO_ODCR0C_P2 (_U_(0x1) << GPIO_ODCR0C_P2_Pos) 6303 #define GPIO_ODCR0C_P3_Pos 3 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6304 #define GPIO_ODCR0C_P3 (_U_(0x1) << GPIO_ODCR0C_P3_Pos) 6305 #define GPIO_ODCR0C_P4_Pos 4 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6306 #define GPIO_ODCR0C_P4 (_U_(0x1) << GPIO_ODCR0C_P4_Pos) 6307 #define GPIO_ODCR0C_P5_Pos 5 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6308 #define GPIO_ODCR0C_P5 (_U_(0x1) << GPIO_ODCR0C_P5_Pos) 6309 #define GPIO_ODCR0C_P6_Pos 6 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6310 #define GPIO_ODCR0C_P6 (_U_(0x1) << GPIO_ODCR0C_P6_Pos) 6311 #define GPIO_ODCR0C_P7_Pos 7 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6312 #define GPIO_ODCR0C_P7 (_U_(0x1) << GPIO_ODCR0C_P7_Pos) 6313 #define GPIO_ODCR0C_P8_Pos 8 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6314 #define GPIO_ODCR0C_P8 (_U_(0x1) << GPIO_ODCR0C_P8_Pos) 6315 #define GPIO_ODCR0C_P9_Pos 9 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6316 #define GPIO_ODCR0C_P9 (_U_(0x1) << GPIO_ODCR0C_P9_Pos) 6317 #define GPIO_ODCR0C_P10_Pos 10 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6318 #define GPIO_ODCR0C_P10 (_U_(0x1) << GPIO_ODCR0C_P10_Pos) 6319 #define GPIO_ODCR0C_P11_Pos 11 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6320 #define GPIO_ODCR0C_P11 (_U_(0x1) << GPIO_ODCR0C_P11_Pos) 6321 #define GPIO_ODCR0C_P12_Pos 12 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6322 #define GPIO_ODCR0C_P12 (_U_(0x1) << GPIO_ODCR0C_P12_Pos) 6323 #define GPIO_ODCR0C_P13_Pos 13 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6324 #define GPIO_ODCR0C_P13 (_U_(0x1) << GPIO_ODCR0C_P13_Pos) 6325 #define GPIO_ODCR0C_P14_Pos 14 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6326 #define GPIO_ODCR0C_P14 (_U_(0x1) << GPIO_ODCR0C_P14_Pos) 6327 #define GPIO_ODCR0C_P15_Pos 15 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6328 #define GPIO_ODCR0C_P15 (_U_(0x1) << GPIO_ODCR0C_P15_Pos) 6329 #define GPIO_ODCR0C_P16_Pos 16 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6330 #define GPIO_ODCR0C_P16 (_U_(0x1) << GPIO_ODCR0C_P16_Pos) 6331 #define GPIO_ODCR0C_P17_Pos 17 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6332 #define GPIO_ODCR0C_P17 (_U_(0x1) << GPIO_ODCR0C_P17_Pos) 6333 #define GPIO_ODCR0C_P18_Pos 18 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6334 #define GPIO_ODCR0C_P18 (_U_(0x1) << GPIO_ODCR0C_P18_Pos) 6335 #define GPIO_ODCR0C_P19_Pos 19 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6336 #define GPIO_ODCR0C_P19 (_U_(0x1) << GPIO_ODCR0C_P19_Pos) 6337 #define GPIO_ODCR0C_P20_Pos 20 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6338 #define GPIO_ODCR0C_P20 (_U_(0x1) << GPIO_ODCR0C_P20_Pos) 6339 #define GPIO_ODCR0C_P21_Pos 21 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6340 #define GPIO_ODCR0C_P21 (_U_(0x1) << GPIO_ODCR0C_P21_Pos) 6341 #define GPIO_ODCR0C_P22_Pos 22 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6342 #define GPIO_ODCR0C_P22 (_U_(0x1) << GPIO_ODCR0C_P22_Pos) 6343 #define GPIO_ODCR0C_P23_Pos 23 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6344 #define GPIO_ODCR0C_P23 (_U_(0x1) << GPIO_ODCR0C_P23_Pos) 6345 #define GPIO_ODCR0C_P24_Pos 24 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6346 #define GPIO_ODCR0C_P24 (_U_(0x1) << GPIO_ODCR0C_P24_Pos) 6347 #define GPIO_ODCR0C_P25_Pos 25 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6348 #define GPIO_ODCR0C_P25 (_U_(0x1) << GPIO_ODCR0C_P25_Pos) 6349 #define GPIO_ODCR0C_P26_Pos 26 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6350 #define GPIO_ODCR0C_P26 (_U_(0x1) << GPIO_ODCR0C_P26_Pos) 6351 #define GPIO_ODCR0C_P27_Pos 27 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6352 #define GPIO_ODCR0C_P27 (_U_(0x1) << GPIO_ODCR0C_P27_Pos) 6353 #define GPIO_ODCR0C_P28_Pos 28 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6354 #define GPIO_ODCR0C_P28 (_U_(0x1) << GPIO_ODCR0C_P28_Pos) 6355 #define GPIO_ODCR0C_P29_Pos 29 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6356 #define GPIO_ODCR0C_P29 (_U_(0x1) << GPIO_ODCR0C_P29_Pos) 6357 #define GPIO_ODCR0C_P30_Pos 30 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6358 #define GPIO_ODCR0C_P30 (_U_(0x1) << GPIO_ODCR0C_P30_Pos) 6359 #define GPIO_ODCR0C_P31_Pos 31 /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */ 6360 #define GPIO_ODCR0C_P31 (_U_(0x1) << GPIO_ODCR0C_P31_Pos) 6361 #define GPIO_ODCR0C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR0C) MASK Register */ 6362 6363 /* -------- GPIO_ODCR0T : (GPIO Offset: 0x10C) (R/W 32) port Output Driving Capability Register 0 - Toggle -------- */ 6364 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6365 typedef union { 6366 struct { 6367 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 0 */ 6368 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 0 */ 6369 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 0 */ 6370 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 0 */ 6371 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 0 */ 6372 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 0 */ 6373 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 0 */ 6374 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 0 */ 6375 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 0 */ 6376 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 0 */ 6377 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 0 */ 6378 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 0 */ 6379 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 0 */ 6380 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 0 */ 6381 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 0 */ 6382 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 0 */ 6383 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 0 */ 6384 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 0 */ 6385 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 0 */ 6386 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 0 */ 6387 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 0 */ 6388 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 0 */ 6389 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 0 */ 6390 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 0 */ 6391 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 0 */ 6392 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 0 */ 6393 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 0 */ 6394 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 0 */ 6395 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 0 */ 6396 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 0 */ 6397 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 0 */ 6398 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 0 */ 6399 } bit; /*!< Structure used for bit access */ 6400 uint32_t reg; /*!< Type used for register access */ 6401 } GPIO_ODCR0T_Type; 6402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6403 6404 #define GPIO_ODCR0T_OFFSET 0x10C /**< \brief (GPIO_ODCR0T offset) Output Driving Capability Register 0 - Toggle */ 6405 6406 #define GPIO_ODCR0T_P0_Pos 0 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6407 #define GPIO_ODCR0T_P0 (_U_(0x1) << GPIO_ODCR0T_P0_Pos) 6408 #define GPIO_ODCR0T_P1_Pos 1 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6409 #define GPIO_ODCR0T_P1 (_U_(0x1) << GPIO_ODCR0T_P1_Pos) 6410 #define GPIO_ODCR0T_P2_Pos 2 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6411 #define GPIO_ODCR0T_P2 (_U_(0x1) << GPIO_ODCR0T_P2_Pos) 6412 #define GPIO_ODCR0T_P3_Pos 3 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6413 #define GPIO_ODCR0T_P3 (_U_(0x1) << GPIO_ODCR0T_P3_Pos) 6414 #define GPIO_ODCR0T_P4_Pos 4 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6415 #define GPIO_ODCR0T_P4 (_U_(0x1) << GPIO_ODCR0T_P4_Pos) 6416 #define GPIO_ODCR0T_P5_Pos 5 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6417 #define GPIO_ODCR0T_P5 (_U_(0x1) << GPIO_ODCR0T_P5_Pos) 6418 #define GPIO_ODCR0T_P6_Pos 6 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6419 #define GPIO_ODCR0T_P6 (_U_(0x1) << GPIO_ODCR0T_P6_Pos) 6420 #define GPIO_ODCR0T_P7_Pos 7 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6421 #define GPIO_ODCR0T_P7 (_U_(0x1) << GPIO_ODCR0T_P7_Pos) 6422 #define GPIO_ODCR0T_P8_Pos 8 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6423 #define GPIO_ODCR0T_P8 (_U_(0x1) << GPIO_ODCR0T_P8_Pos) 6424 #define GPIO_ODCR0T_P9_Pos 9 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6425 #define GPIO_ODCR0T_P9 (_U_(0x1) << GPIO_ODCR0T_P9_Pos) 6426 #define GPIO_ODCR0T_P10_Pos 10 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6427 #define GPIO_ODCR0T_P10 (_U_(0x1) << GPIO_ODCR0T_P10_Pos) 6428 #define GPIO_ODCR0T_P11_Pos 11 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6429 #define GPIO_ODCR0T_P11 (_U_(0x1) << GPIO_ODCR0T_P11_Pos) 6430 #define GPIO_ODCR0T_P12_Pos 12 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6431 #define GPIO_ODCR0T_P12 (_U_(0x1) << GPIO_ODCR0T_P12_Pos) 6432 #define GPIO_ODCR0T_P13_Pos 13 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6433 #define GPIO_ODCR0T_P13 (_U_(0x1) << GPIO_ODCR0T_P13_Pos) 6434 #define GPIO_ODCR0T_P14_Pos 14 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6435 #define GPIO_ODCR0T_P14 (_U_(0x1) << GPIO_ODCR0T_P14_Pos) 6436 #define GPIO_ODCR0T_P15_Pos 15 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6437 #define GPIO_ODCR0T_P15 (_U_(0x1) << GPIO_ODCR0T_P15_Pos) 6438 #define GPIO_ODCR0T_P16_Pos 16 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6439 #define GPIO_ODCR0T_P16 (_U_(0x1) << GPIO_ODCR0T_P16_Pos) 6440 #define GPIO_ODCR0T_P17_Pos 17 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6441 #define GPIO_ODCR0T_P17 (_U_(0x1) << GPIO_ODCR0T_P17_Pos) 6442 #define GPIO_ODCR0T_P18_Pos 18 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6443 #define GPIO_ODCR0T_P18 (_U_(0x1) << GPIO_ODCR0T_P18_Pos) 6444 #define GPIO_ODCR0T_P19_Pos 19 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6445 #define GPIO_ODCR0T_P19 (_U_(0x1) << GPIO_ODCR0T_P19_Pos) 6446 #define GPIO_ODCR0T_P20_Pos 20 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6447 #define GPIO_ODCR0T_P20 (_U_(0x1) << GPIO_ODCR0T_P20_Pos) 6448 #define GPIO_ODCR0T_P21_Pos 21 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6449 #define GPIO_ODCR0T_P21 (_U_(0x1) << GPIO_ODCR0T_P21_Pos) 6450 #define GPIO_ODCR0T_P22_Pos 22 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6451 #define GPIO_ODCR0T_P22 (_U_(0x1) << GPIO_ODCR0T_P22_Pos) 6452 #define GPIO_ODCR0T_P23_Pos 23 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6453 #define GPIO_ODCR0T_P23 (_U_(0x1) << GPIO_ODCR0T_P23_Pos) 6454 #define GPIO_ODCR0T_P24_Pos 24 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6455 #define GPIO_ODCR0T_P24 (_U_(0x1) << GPIO_ODCR0T_P24_Pos) 6456 #define GPIO_ODCR0T_P25_Pos 25 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6457 #define GPIO_ODCR0T_P25 (_U_(0x1) << GPIO_ODCR0T_P25_Pos) 6458 #define GPIO_ODCR0T_P26_Pos 26 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6459 #define GPIO_ODCR0T_P26 (_U_(0x1) << GPIO_ODCR0T_P26_Pos) 6460 #define GPIO_ODCR0T_P27_Pos 27 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6461 #define GPIO_ODCR0T_P27 (_U_(0x1) << GPIO_ODCR0T_P27_Pos) 6462 #define GPIO_ODCR0T_P28_Pos 28 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6463 #define GPIO_ODCR0T_P28 (_U_(0x1) << GPIO_ODCR0T_P28_Pos) 6464 #define GPIO_ODCR0T_P29_Pos 29 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6465 #define GPIO_ODCR0T_P29 (_U_(0x1) << GPIO_ODCR0T_P29_Pos) 6466 #define GPIO_ODCR0T_P30_Pos 30 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6467 #define GPIO_ODCR0T_P30 (_U_(0x1) << GPIO_ODCR0T_P30_Pos) 6468 #define GPIO_ODCR0T_P31_Pos 31 /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */ 6469 #define GPIO_ODCR0T_P31 (_U_(0x1) << GPIO_ODCR0T_P31_Pos) 6470 #define GPIO_ODCR0T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR0T) MASK Register */ 6471 6472 /* -------- GPIO_ODCR1 : (GPIO Offset: 0x110) (R/W 32) port Output Driving Capability Register 1 -------- */ 6473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6474 typedef union { 6475 struct { 6476 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 1 */ 6477 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 1 */ 6478 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 1 */ 6479 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 1 */ 6480 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 1 */ 6481 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 1 */ 6482 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 1 */ 6483 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 1 */ 6484 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 1 */ 6485 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 1 */ 6486 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 1 */ 6487 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 1 */ 6488 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 1 */ 6489 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 1 */ 6490 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 1 */ 6491 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 1 */ 6492 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 1 */ 6493 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 1 */ 6494 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 1 */ 6495 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 1 */ 6496 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 1 */ 6497 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 1 */ 6498 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 1 */ 6499 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 1 */ 6500 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 1 */ 6501 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 1 */ 6502 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 1 */ 6503 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 1 */ 6504 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 1 */ 6505 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 1 */ 6506 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 1 */ 6507 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 1 */ 6508 } bit; /*!< Structure used for bit access */ 6509 uint32_t reg; /*!< Type used for register access */ 6510 } GPIO_ODCR1_Type; 6511 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6512 6513 #define GPIO_ODCR1_OFFSET 0x110 /**< \brief (GPIO_ODCR1 offset) Output Driving Capability Register 1 */ 6514 6515 #define GPIO_ODCR1_P0_Pos 0 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6516 #define GPIO_ODCR1_P0 (_U_(0x1) << GPIO_ODCR1_P0_Pos) 6517 #define GPIO_ODCR1_P1_Pos 1 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6518 #define GPIO_ODCR1_P1 (_U_(0x1) << GPIO_ODCR1_P1_Pos) 6519 #define GPIO_ODCR1_P2_Pos 2 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6520 #define GPIO_ODCR1_P2 (_U_(0x1) << GPIO_ODCR1_P2_Pos) 6521 #define GPIO_ODCR1_P3_Pos 3 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6522 #define GPIO_ODCR1_P3 (_U_(0x1) << GPIO_ODCR1_P3_Pos) 6523 #define GPIO_ODCR1_P4_Pos 4 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6524 #define GPIO_ODCR1_P4 (_U_(0x1) << GPIO_ODCR1_P4_Pos) 6525 #define GPIO_ODCR1_P5_Pos 5 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6526 #define GPIO_ODCR1_P5 (_U_(0x1) << GPIO_ODCR1_P5_Pos) 6527 #define GPIO_ODCR1_P6_Pos 6 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6528 #define GPIO_ODCR1_P6 (_U_(0x1) << GPIO_ODCR1_P6_Pos) 6529 #define GPIO_ODCR1_P7_Pos 7 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6530 #define GPIO_ODCR1_P7 (_U_(0x1) << GPIO_ODCR1_P7_Pos) 6531 #define GPIO_ODCR1_P8_Pos 8 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6532 #define GPIO_ODCR1_P8 (_U_(0x1) << GPIO_ODCR1_P8_Pos) 6533 #define GPIO_ODCR1_P9_Pos 9 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6534 #define GPIO_ODCR1_P9 (_U_(0x1) << GPIO_ODCR1_P9_Pos) 6535 #define GPIO_ODCR1_P10_Pos 10 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6536 #define GPIO_ODCR1_P10 (_U_(0x1) << GPIO_ODCR1_P10_Pos) 6537 #define GPIO_ODCR1_P11_Pos 11 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6538 #define GPIO_ODCR1_P11 (_U_(0x1) << GPIO_ODCR1_P11_Pos) 6539 #define GPIO_ODCR1_P12_Pos 12 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6540 #define GPIO_ODCR1_P12 (_U_(0x1) << GPIO_ODCR1_P12_Pos) 6541 #define GPIO_ODCR1_P13_Pos 13 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6542 #define GPIO_ODCR1_P13 (_U_(0x1) << GPIO_ODCR1_P13_Pos) 6543 #define GPIO_ODCR1_P14_Pos 14 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6544 #define GPIO_ODCR1_P14 (_U_(0x1) << GPIO_ODCR1_P14_Pos) 6545 #define GPIO_ODCR1_P15_Pos 15 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6546 #define GPIO_ODCR1_P15 (_U_(0x1) << GPIO_ODCR1_P15_Pos) 6547 #define GPIO_ODCR1_P16_Pos 16 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6548 #define GPIO_ODCR1_P16 (_U_(0x1) << GPIO_ODCR1_P16_Pos) 6549 #define GPIO_ODCR1_P17_Pos 17 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6550 #define GPIO_ODCR1_P17 (_U_(0x1) << GPIO_ODCR1_P17_Pos) 6551 #define GPIO_ODCR1_P18_Pos 18 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6552 #define GPIO_ODCR1_P18 (_U_(0x1) << GPIO_ODCR1_P18_Pos) 6553 #define GPIO_ODCR1_P19_Pos 19 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6554 #define GPIO_ODCR1_P19 (_U_(0x1) << GPIO_ODCR1_P19_Pos) 6555 #define GPIO_ODCR1_P20_Pos 20 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6556 #define GPIO_ODCR1_P20 (_U_(0x1) << GPIO_ODCR1_P20_Pos) 6557 #define GPIO_ODCR1_P21_Pos 21 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6558 #define GPIO_ODCR1_P21 (_U_(0x1) << GPIO_ODCR1_P21_Pos) 6559 #define GPIO_ODCR1_P22_Pos 22 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6560 #define GPIO_ODCR1_P22 (_U_(0x1) << GPIO_ODCR1_P22_Pos) 6561 #define GPIO_ODCR1_P23_Pos 23 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6562 #define GPIO_ODCR1_P23 (_U_(0x1) << GPIO_ODCR1_P23_Pos) 6563 #define GPIO_ODCR1_P24_Pos 24 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6564 #define GPIO_ODCR1_P24 (_U_(0x1) << GPIO_ODCR1_P24_Pos) 6565 #define GPIO_ODCR1_P25_Pos 25 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6566 #define GPIO_ODCR1_P25 (_U_(0x1) << GPIO_ODCR1_P25_Pos) 6567 #define GPIO_ODCR1_P26_Pos 26 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6568 #define GPIO_ODCR1_P26 (_U_(0x1) << GPIO_ODCR1_P26_Pos) 6569 #define GPIO_ODCR1_P27_Pos 27 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6570 #define GPIO_ODCR1_P27 (_U_(0x1) << GPIO_ODCR1_P27_Pos) 6571 #define GPIO_ODCR1_P28_Pos 28 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6572 #define GPIO_ODCR1_P28 (_U_(0x1) << GPIO_ODCR1_P28_Pos) 6573 #define GPIO_ODCR1_P29_Pos 29 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6574 #define GPIO_ODCR1_P29 (_U_(0x1) << GPIO_ODCR1_P29_Pos) 6575 #define GPIO_ODCR1_P30_Pos 30 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6576 #define GPIO_ODCR1_P30 (_U_(0x1) << GPIO_ODCR1_P30_Pos) 6577 #define GPIO_ODCR1_P31_Pos 31 /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */ 6578 #define GPIO_ODCR1_P31 (_U_(0x1) << GPIO_ODCR1_P31_Pos) 6579 #define GPIO_ODCR1_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR1) MASK Register */ 6580 6581 /* -------- GPIO_ODCR1S : (GPIO Offset: 0x114) (R/W 32) port Output Driving Capability Register 1 - Set -------- */ 6582 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6583 typedef union { 6584 struct { 6585 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 1 */ 6586 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 1 */ 6587 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 1 */ 6588 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 1 */ 6589 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 1 */ 6590 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 1 */ 6591 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 1 */ 6592 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 1 */ 6593 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 1 */ 6594 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 1 */ 6595 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 1 */ 6596 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 1 */ 6597 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 1 */ 6598 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 1 */ 6599 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 1 */ 6600 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 1 */ 6601 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 1 */ 6602 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 1 */ 6603 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 1 */ 6604 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 1 */ 6605 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 1 */ 6606 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 1 */ 6607 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 1 */ 6608 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 1 */ 6609 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 1 */ 6610 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 1 */ 6611 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 1 */ 6612 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 1 */ 6613 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 1 */ 6614 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 1 */ 6615 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 1 */ 6616 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 1 */ 6617 } bit; /*!< Structure used for bit access */ 6618 uint32_t reg; /*!< Type used for register access */ 6619 } GPIO_ODCR1S_Type; 6620 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6621 6622 #define GPIO_ODCR1S_OFFSET 0x114 /**< \brief (GPIO_ODCR1S offset) Output Driving Capability Register 1 - Set */ 6623 6624 #define GPIO_ODCR1S_P0_Pos 0 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6625 #define GPIO_ODCR1S_P0 (_U_(0x1) << GPIO_ODCR1S_P0_Pos) 6626 #define GPIO_ODCR1S_P1_Pos 1 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6627 #define GPIO_ODCR1S_P1 (_U_(0x1) << GPIO_ODCR1S_P1_Pos) 6628 #define GPIO_ODCR1S_P2_Pos 2 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6629 #define GPIO_ODCR1S_P2 (_U_(0x1) << GPIO_ODCR1S_P2_Pos) 6630 #define GPIO_ODCR1S_P3_Pos 3 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6631 #define GPIO_ODCR1S_P3 (_U_(0x1) << GPIO_ODCR1S_P3_Pos) 6632 #define GPIO_ODCR1S_P4_Pos 4 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6633 #define GPIO_ODCR1S_P4 (_U_(0x1) << GPIO_ODCR1S_P4_Pos) 6634 #define GPIO_ODCR1S_P5_Pos 5 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6635 #define GPIO_ODCR1S_P5 (_U_(0x1) << GPIO_ODCR1S_P5_Pos) 6636 #define GPIO_ODCR1S_P6_Pos 6 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6637 #define GPIO_ODCR1S_P6 (_U_(0x1) << GPIO_ODCR1S_P6_Pos) 6638 #define GPIO_ODCR1S_P7_Pos 7 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6639 #define GPIO_ODCR1S_P7 (_U_(0x1) << GPIO_ODCR1S_P7_Pos) 6640 #define GPIO_ODCR1S_P8_Pos 8 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6641 #define GPIO_ODCR1S_P8 (_U_(0x1) << GPIO_ODCR1S_P8_Pos) 6642 #define GPIO_ODCR1S_P9_Pos 9 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6643 #define GPIO_ODCR1S_P9 (_U_(0x1) << GPIO_ODCR1S_P9_Pos) 6644 #define GPIO_ODCR1S_P10_Pos 10 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6645 #define GPIO_ODCR1S_P10 (_U_(0x1) << GPIO_ODCR1S_P10_Pos) 6646 #define GPIO_ODCR1S_P11_Pos 11 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6647 #define GPIO_ODCR1S_P11 (_U_(0x1) << GPIO_ODCR1S_P11_Pos) 6648 #define GPIO_ODCR1S_P12_Pos 12 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6649 #define GPIO_ODCR1S_P12 (_U_(0x1) << GPIO_ODCR1S_P12_Pos) 6650 #define GPIO_ODCR1S_P13_Pos 13 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6651 #define GPIO_ODCR1S_P13 (_U_(0x1) << GPIO_ODCR1S_P13_Pos) 6652 #define GPIO_ODCR1S_P14_Pos 14 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6653 #define GPIO_ODCR1S_P14 (_U_(0x1) << GPIO_ODCR1S_P14_Pos) 6654 #define GPIO_ODCR1S_P15_Pos 15 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6655 #define GPIO_ODCR1S_P15 (_U_(0x1) << GPIO_ODCR1S_P15_Pos) 6656 #define GPIO_ODCR1S_P16_Pos 16 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6657 #define GPIO_ODCR1S_P16 (_U_(0x1) << GPIO_ODCR1S_P16_Pos) 6658 #define GPIO_ODCR1S_P17_Pos 17 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6659 #define GPIO_ODCR1S_P17 (_U_(0x1) << GPIO_ODCR1S_P17_Pos) 6660 #define GPIO_ODCR1S_P18_Pos 18 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6661 #define GPIO_ODCR1S_P18 (_U_(0x1) << GPIO_ODCR1S_P18_Pos) 6662 #define GPIO_ODCR1S_P19_Pos 19 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6663 #define GPIO_ODCR1S_P19 (_U_(0x1) << GPIO_ODCR1S_P19_Pos) 6664 #define GPIO_ODCR1S_P20_Pos 20 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6665 #define GPIO_ODCR1S_P20 (_U_(0x1) << GPIO_ODCR1S_P20_Pos) 6666 #define GPIO_ODCR1S_P21_Pos 21 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6667 #define GPIO_ODCR1S_P21 (_U_(0x1) << GPIO_ODCR1S_P21_Pos) 6668 #define GPIO_ODCR1S_P22_Pos 22 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6669 #define GPIO_ODCR1S_P22 (_U_(0x1) << GPIO_ODCR1S_P22_Pos) 6670 #define GPIO_ODCR1S_P23_Pos 23 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6671 #define GPIO_ODCR1S_P23 (_U_(0x1) << GPIO_ODCR1S_P23_Pos) 6672 #define GPIO_ODCR1S_P24_Pos 24 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6673 #define GPIO_ODCR1S_P24 (_U_(0x1) << GPIO_ODCR1S_P24_Pos) 6674 #define GPIO_ODCR1S_P25_Pos 25 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6675 #define GPIO_ODCR1S_P25 (_U_(0x1) << GPIO_ODCR1S_P25_Pos) 6676 #define GPIO_ODCR1S_P26_Pos 26 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6677 #define GPIO_ODCR1S_P26 (_U_(0x1) << GPIO_ODCR1S_P26_Pos) 6678 #define GPIO_ODCR1S_P27_Pos 27 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6679 #define GPIO_ODCR1S_P27 (_U_(0x1) << GPIO_ODCR1S_P27_Pos) 6680 #define GPIO_ODCR1S_P28_Pos 28 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6681 #define GPIO_ODCR1S_P28 (_U_(0x1) << GPIO_ODCR1S_P28_Pos) 6682 #define GPIO_ODCR1S_P29_Pos 29 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6683 #define GPIO_ODCR1S_P29 (_U_(0x1) << GPIO_ODCR1S_P29_Pos) 6684 #define GPIO_ODCR1S_P30_Pos 30 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6685 #define GPIO_ODCR1S_P30 (_U_(0x1) << GPIO_ODCR1S_P30_Pos) 6686 #define GPIO_ODCR1S_P31_Pos 31 /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */ 6687 #define GPIO_ODCR1S_P31 (_U_(0x1) << GPIO_ODCR1S_P31_Pos) 6688 #define GPIO_ODCR1S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR1S) MASK Register */ 6689 6690 /* -------- GPIO_ODCR1C : (GPIO Offset: 0x118) (R/W 32) port Output Driving Capability Register 1 - Clear -------- */ 6691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6692 typedef union { 6693 struct { 6694 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 1 */ 6695 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 1 */ 6696 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 1 */ 6697 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 1 */ 6698 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 1 */ 6699 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 1 */ 6700 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 1 */ 6701 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 1 */ 6702 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 1 */ 6703 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 1 */ 6704 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 1 */ 6705 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 1 */ 6706 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 1 */ 6707 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 1 */ 6708 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 1 */ 6709 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 1 */ 6710 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 1 */ 6711 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 1 */ 6712 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 1 */ 6713 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 1 */ 6714 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 1 */ 6715 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 1 */ 6716 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 1 */ 6717 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 1 */ 6718 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 1 */ 6719 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 1 */ 6720 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 1 */ 6721 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 1 */ 6722 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 1 */ 6723 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 1 */ 6724 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 1 */ 6725 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 1 */ 6726 } bit; /*!< Structure used for bit access */ 6727 uint32_t reg; /*!< Type used for register access */ 6728 } GPIO_ODCR1C_Type; 6729 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6730 6731 #define GPIO_ODCR1C_OFFSET 0x118 /**< \brief (GPIO_ODCR1C offset) Output Driving Capability Register 1 - Clear */ 6732 6733 #define GPIO_ODCR1C_P0_Pos 0 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6734 #define GPIO_ODCR1C_P0 (_U_(0x1) << GPIO_ODCR1C_P0_Pos) 6735 #define GPIO_ODCR1C_P1_Pos 1 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6736 #define GPIO_ODCR1C_P1 (_U_(0x1) << GPIO_ODCR1C_P1_Pos) 6737 #define GPIO_ODCR1C_P2_Pos 2 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6738 #define GPIO_ODCR1C_P2 (_U_(0x1) << GPIO_ODCR1C_P2_Pos) 6739 #define GPIO_ODCR1C_P3_Pos 3 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6740 #define GPIO_ODCR1C_P3 (_U_(0x1) << GPIO_ODCR1C_P3_Pos) 6741 #define GPIO_ODCR1C_P4_Pos 4 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6742 #define GPIO_ODCR1C_P4 (_U_(0x1) << GPIO_ODCR1C_P4_Pos) 6743 #define GPIO_ODCR1C_P5_Pos 5 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6744 #define GPIO_ODCR1C_P5 (_U_(0x1) << GPIO_ODCR1C_P5_Pos) 6745 #define GPIO_ODCR1C_P6_Pos 6 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6746 #define GPIO_ODCR1C_P6 (_U_(0x1) << GPIO_ODCR1C_P6_Pos) 6747 #define GPIO_ODCR1C_P7_Pos 7 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6748 #define GPIO_ODCR1C_P7 (_U_(0x1) << GPIO_ODCR1C_P7_Pos) 6749 #define GPIO_ODCR1C_P8_Pos 8 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6750 #define GPIO_ODCR1C_P8 (_U_(0x1) << GPIO_ODCR1C_P8_Pos) 6751 #define GPIO_ODCR1C_P9_Pos 9 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6752 #define GPIO_ODCR1C_P9 (_U_(0x1) << GPIO_ODCR1C_P9_Pos) 6753 #define GPIO_ODCR1C_P10_Pos 10 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6754 #define GPIO_ODCR1C_P10 (_U_(0x1) << GPIO_ODCR1C_P10_Pos) 6755 #define GPIO_ODCR1C_P11_Pos 11 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6756 #define GPIO_ODCR1C_P11 (_U_(0x1) << GPIO_ODCR1C_P11_Pos) 6757 #define GPIO_ODCR1C_P12_Pos 12 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6758 #define GPIO_ODCR1C_P12 (_U_(0x1) << GPIO_ODCR1C_P12_Pos) 6759 #define GPIO_ODCR1C_P13_Pos 13 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6760 #define GPIO_ODCR1C_P13 (_U_(0x1) << GPIO_ODCR1C_P13_Pos) 6761 #define GPIO_ODCR1C_P14_Pos 14 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6762 #define GPIO_ODCR1C_P14 (_U_(0x1) << GPIO_ODCR1C_P14_Pos) 6763 #define GPIO_ODCR1C_P15_Pos 15 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6764 #define GPIO_ODCR1C_P15 (_U_(0x1) << GPIO_ODCR1C_P15_Pos) 6765 #define GPIO_ODCR1C_P16_Pos 16 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6766 #define GPIO_ODCR1C_P16 (_U_(0x1) << GPIO_ODCR1C_P16_Pos) 6767 #define GPIO_ODCR1C_P17_Pos 17 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6768 #define GPIO_ODCR1C_P17 (_U_(0x1) << GPIO_ODCR1C_P17_Pos) 6769 #define GPIO_ODCR1C_P18_Pos 18 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6770 #define GPIO_ODCR1C_P18 (_U_(0x1) << GPIO_ODCR1C_P18_Pos) 6771 #define GPIO_ODCR1C_P19_Pos 19 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6772 #define GPIO_ODCR1C_P19 (_U_(0x1) << GPIO_ODCR1C_P19_Pos) 6773 #define GPIO_ODCR1C_P20_Pos 20 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6774 #define GPIO_ODCR1C_P20 (_U_(0x1) << GPIO_ODCR1C_P20_Pos) 6775 #define GPIO_ODCR1C_P21_Pos 21 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6776 #define GPIO_ODCR1C_P21 (_U_(0x1) << GPIO_ODCR1C_P21_Pos) 6777 #define GPIO_ODCR1C_P22_Pos 22 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6778 #define GPIO_ODCR1C_P22 (_U_(0x1) << GPIO_ODCR1C_P22_Pos) 6779 #define GPIO_ODCR1C_P23_Pos 23 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6780 #define GPIO_ODCR1C_P23 (_U_(0x1) << GPIO_ODCR1C_P23_Pos) 6781 #define GPIO_ODCR1C_P24_Pos 24 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6782 #define GPIO_ODCR1C_P24 (_U_(0x1) << GPIO_ODCR1C_P24_Pos) 6783 #define GPIO_ODCR1C_P25_Pos 25 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6784 #define GPIO_ODCR1C_P25 (_U_(0x1) << GPIO_ODCR1C_P25_Pos) 6785 #define GPIO_ODCR1C_P26_Pos 26 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6786 #define GPIO_ODCR1C_P26 (_U_(0x1) << GPIO_ODCR1C_P26_Pos) 6787 #define GPIO_ODCR1C_P27_Pos 27 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6788 #define GPIO_ODCR1C_P27 (_U_(0x1) << GPIO_ODCR1C_P27_Pos) 6789 #define GPIO_ODCR1C_P28_Pos 28 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6790 #define GPIO_ODCR1C_P28 (_U_(0x1) << GPIO_ODCR1C_P28_Pos) 6791 #define GPIO_ODCR1C_P29_Pos 29 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6792 #define GPIO_ODCR1C_P29 (_U_(0x1) << GPIO_ODCR1C_P29_Pos) 6793 #define GPIO_ODCR1C_P30_Pos 30 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6794 #define GPIO_ODCR1C_P30 (_U_(0x1) << GPIO_ODCR1C_P30_Pos) 6795 #define GPIO_ODCR1C_P31_Pos 31 /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */ 6796 #define GPIO_ODCR1C_P31 (_U_(0x1) << GPIO_ODCR1C_P31_Pos) 6797 #define GPIO_ODCR1C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR1C) MASK Register */ 6798 6799 /* -------- GPIO_ODCR1T : (GPIO Offset: 0x11C) (R/W 32) port Output Driving Capability Register 1 - Toggle -------- */ 6800 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6801 typedef union { 6802 struct { 6803 uint32_t P0:1; /*!< bit: 0 Output Driving Capability Register Bit 1 */ 6804 uint32_t P1:1; /*!< bit: 1 Output Driving Capability Register Bit 1 */ 6805 uint32_t P2:1; /*!< bit: 2 Output Driving Capability Register Bit 1 */ 6806 uint32_t P3:1; /*!< bit: 3 Output Driving Capability Register Bit 1 */ 6807 uint32_t P4:1; /*!< bit: 4 Output Driving Capability Register Bit 1 */ 6808 uint32_t P5:1; /*!< bit: 5 Output Driving Capability Register Bit 1 */ 6809 uint32_t P6:1; /*!< bit: 6 Output Driving Capability Register Bit 1 */ 6810 uint32_t P7:1; /*!< bit: 7 Output Driving Capability Register Bit 1 */ 6811 uint32_t P8:1; /*!< bit: 8 Output Driving Capability Register Bit 1 */ 6812 uint32_t P9:1; /*!< bit: 9 Output Driving Capability Register Bit 1 */ 6813 uint32_t P10:1; /*!< bit: 10 Output Driving Capability Register Bit 1 */ 6814 uint32_t P11:1; /*!< bit: 11 Output Driving Capability Register Bit 1 */ 6815 uint32_t P12:1; /*!< bit: 12 Output Driving Capability Register Bit 1 */ 6816 uint32_t P13:1; /*!< bit: 13 Output Driving Capability Register Bit 1 */ 6817 uint32_t P14:1; /*!< bit: 14 Output Driving Capability Register Bit 1 */ 6818 uint32_t P15:1; /*!< bit: 15 Output Driving Capability Register Bit 1 */ 6819 uint32_t P16:1; /*!< bit: 16 Output Driving Capability Register Bit 1 */ 6820 uint32_t P17:1; /*!< bit: 17 Output Driving Capability Register Bit 1 */ 6821 uint32_t P18:1; /*!< bit: 18 Output Driving Capability Register Bit 1 */ 6822 uint32_t P19:1; /*!< bit: 19 Output Driving Capability Register Bit 1 */ 6823 uint32_t P20:1; /*!< bit: 20 Output Driving Capability Register Bit 1 */ 6824 uint32_t P21:1; /*!< bit: 21 Output Driving Capability Register Bit 1 */ 6825 uint32_t P22:1; /*!< bit: 22 Output Driving Capability Register Bit 1 */ 6826 uint32_t P23:1; /*!< bit: 23 Output Driving Capability Register Bit 1 */ 6827 uint32_t P24:1; /*!< bit: 24 Output Driving Capability Register Bit 1 */ 6828 uint32_t P25:1; /*!< bit: 25 Output Driving Capability Register Bit 1 */ 6829 uint32_t P26:1; /*!< bit: 26 Output Driving Capability Register Bit 1 */ 6830 uint32_t P27:1; /*!< bit: 27 Output Driving Capability Register Bit 1 */ 6831 uint32_t P28:1; /*!< bit: 28 Output Driving Capability Register Bit 1 */ 6832 uint32_t P29:1; /*!< bit: 29 Output Driving Capability Register Bit 1 */ 6833 uint32_t P30:1; /*!< bit: 30 Output Driving Capability Register Bit 1 */ 6834 uint32_t P31:1; /*!< bit: 31 Output Driving Capability Register Bit 1 */ 6835 } bit; /*!< Structure used for bit access */ 6836 uint32_t reg; /*!< Type used for register access */ 6837 } GPIO_ODCR1T_Type; 6838 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6839 6840 #define GPIO_ODCR1T_OFFSET 0x11C /**< \brief (GPIO_ODCR1T offset) Output Driving Capability Register 1 - Toggle */ 6841 6842 #define GPIO_ODCR1T_P0_Pos 0 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6843 #define GPIO_ODCR1T_P0 (_U_(0x1) << GPIO_ODCR1T_P0_Pos) 6844 #define GPIO_ODCR1T_P1_Pos 1 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6845 #define GPIO_ODCR1T_P1 (_U_(0x1) << GPIO_ODCR1T_P1_Pos) 6846 #define GPIO_ODCR1T_P2_Pos 2 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6847 #define GPIO_ODCR1T_P2 (_U_(0x1) << GPIO_ODCR1T_P2_Pos) 6848 #define GPIO_ODCR1T_P3_Pos 3 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6849 #define GPIO_ODCR1T_P3 (_U_(0x1) << GPIO_ODCR1T_P3_Pos) 6850 #define GPIO_ODCR1T_P4_Pos 4 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6851 #define GPIO_ODCR1T_P4 (_U_(0x1) << GPIO_ODCR1T_P4_Pos) 6852 #define GPIO_ODCR1T_P5_Pos 5 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6853 #define GPIO_ODCR1T_P5 (_U_(0x1) << GPIO_ODCR1T_P5_Pos) 6854 #define GPIO_ODCR1T_P6_Pos 6 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6855 #define GPIO_ODCR1T_P6 (_U_(0x1) << GPIO_ODCR1T_P6_Pos) 6856 #define GPIO_ODCR1T_P7_Pos 7 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6857 #define GPIO_ODCR1T_P7 (_U_(0x1) << GPIO_ODCR1T_P7_Pos) 6858 #define GPIO_ODCR1T_P8_Pos 8 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6859 #define GPIO_ODCR1T_P8 (_U_(0x1) << GPIO_ODCR1T_P8_Pos) 6860 #define GPIO_ODCR1T_P9_Pos 9 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6861 #define GPIO_ODCR1T_P9 (_U_(0x1) << GPIO_ODCR1T_P9_Pos) 6862 #define GPIO_ODCR1T_P10_Pos 10 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6863 #define GPIO_ODCR1T_P10 (_U_(0x1) << GPIO_ODCR1T_P10_Pos) 6864 #define GPIO_ODCR1T_P11_Pos 11 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6865 #define GPIO_ODCR1T_P11 (_U_(0x1) << GPIO_ODCR1T_P11_Pos) 6866 #define GPIO_ODCR1T_P12_Pos 12 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6867 #define GPIO_ODCR1T_P12 (_U_(0x1) << GPIO_ODCR1T_P12_Pos) 6868 #define GPIO_ODCR1T_P13_Pos 13 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6869 #define GPIO_ODCR1T_P13 (_U_(0x1) << GPIO_ODCR1T_P13_Pos) 6870 #define GPIO_ODCR1T_P14_Pos 14 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6871 #define GPIO_ODCR1T_P14 (_U_(0x1) << GPIO_ODCR1T_P14_Pos) 6872 #define GPIO_ODCR1T_P15_Pos 15 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6873 #define GPIO_ODCR1T_P15 (_U_(0x1) << GPIO_ODCR1T_P15_Pos) 6874 #define GPIO_ODCR1T_P16_Pos 16 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6875 #define GPIO_ODCR1T_P16 (_U_(0x1) << GPIO_ODCR1T_P16_Pos) 6876 #define GPIO_ODCR1T_P17_Pos 17 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6877 #define GPIO_ODCR1T_P17 (_U_(0x1) << GPIO_ODCR1T_P17_Pos) 6878 #define GPIO_ODCR1T_P18_Pos 18 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6879 #define GPIO_ODCR1T_P18 (_U_(0x1) << GPIO_ODCR1T_P18_Pos) 6880 #define GPIO_ODCR1T_P19_Pos 19 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6881 #define GPIO_ODCR1T_P19 (_U_(0x1) << GPIO_ODCR1T_P19_Pos) 6882 #define GPIO_ODCR1T_P20_Pos 20 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6883 #define GPIO_ODCR1T_P20 (_U_(0x1) << GPIO_ODCR1T_P20_Pos) 6884 #define GPIO_ODCR1T_P21_Pos 21 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6885 #define GPIO_ODCR1T_P21 (_U_(0x1) << GPIO_ODCR1T_P21_Pos) 6886 #define GPIO_ODCR1T_P22_Pos 22 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6887 #define GPIO_ODCR1T_P22 (_U_(0x1) << GPIO_ODCR1T_P22_Pos) 6888 #define GPIO_ODCR1T_P23_Pos 23 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6889 #define GPIO_ODCR1T_P23 (_U_(0x1) << GPIO_ODCR1T_P23_Pos) 6890 #define GPIO_ODCR1T_P24_Pos 24 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6891 #define GPIO_ODCR1T_P24 (_U_(0x1) << GPIO_ODCR1T_P24_Pos) 6892 #define GPIO_ODCR1T_P25_Pos 25 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6893 #define GPIO_ODCR1T_P25 (_U_(0x1) << GPIO_ODCR1T_P25_Pos) 6894 #define GPIO_ODCR1T_P26_Pos 26 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6895 #define GPIO_ODCR1T_P26 (_U_(0x1) << GPIO_ODCR1T_P26_Pos) 6896 #define GPIO_ODCR1T_P27_Pos 27 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6897 #define GPIO_ODCR1T_P27 (_U_(0x1) << GPIO_ODCR1T_P27_Pos) 6898 #define GPIO_ODCR1T_P28_Pos 28 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6899 #define GPIO_ODCR1T_P28 (_U_(0x1) << GPIO_ODCR1T_P28_Pos) 6900 #define GPIO_ODCR1T_P29_Pos 29 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6901 #define GPIO_ODCR1T_P29 (_U_(0x1) << GPIO_ODCR1T_P29_Pos) 6902 #define GPIO_ODCR1T_P30_Pos 30 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6903 #define GPIO_ODCR1T_P30 (_U_(0x1) << GPIO_ODCR1T_P30_Pos) 6904 #define GPIO_ODCR1T_P31_Pos 31 /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */ 6905 #define GPIO_ODCR1T_P31 (_U_(0x1) << GPIO_ODCR1T_P31_Pos) 6906 #define GPIO_ODCR1T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_ODCR1T) MASK Register */ 6907 6908 /* -------- GPIO_OSRR0 : (GPIO Offset: 0x130) (R/W 32) port Output Slew Rate Register 0 -------- */ 6909 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6910 typedef union { 6911 struct { 6912 uint32_t P0:1; /*!< bit: 0 Output Slew Rate Control Enable */ 6913 uint32_t P1:1; /*!< bit: 1 Output Slew Rate Control Enable */ 6914 uint32_t P2:1; /*!< bit: 2 Output Slew Rate Control Enable */ 6915 uint32_t P3:1; /*!< bit: 3 Output Slew Rate Control Enable */ 6916 uint32_t P4:1; /*!< bit: 4 Output Slew Rate Control Enable */ 6917 uint32_t P5:1; /*!< bit: 5 Output Slew Rate Control Enable */ 6918 uint32_t P6:1; /*!< bit: 6 Output Slew Rate Control Enable */ 6919 uint32_t P7:1; /*!< bit: 7 Output Slew Rate Control Enable */ 6920 uint32_t P8:1; /*!< bit: 8 Output Slew Rate Control Enable */ 6921 uint32_t P9:1; /*!< bit: 9 Output Slew Rate Control Enable */ 6922 uint32_t P10:1; /*!< bit: 10 Output Slew Rate Control Enable */ 6923 uint32_t P11:1; /*!< bit: 11 Output Slew Rate Control Enable */ 6924 uint32_t P12:1; /*!< bit: 12 Output Slew Rate Control Enable */ 6925 uint32_t P13:1; /*!< bit: 13 Output Slew Rate Control Enable */ 6926 uint32_t P14:1; /*!< bit: 14 Output Slew Rate Control Enable */ 6927 uint32_t P15:1; /*!< bit: 15 Output Slew Rate Control Enable */ 6928 uint32_t P16:1; /*!< bit: 16 Output Slew Rate Control Enable */ 6929 uint32_t P17:1; /*!< bit: 17 Output Slew Rate Control Enable */ 6930 uint32_t P18:1; /*!< bit: 18 Output Slew Rate Control Enable */ 6931 uint32_t P19:1; /*!< bit: 19 Output Slew Rate Control Enable */ 6932 uint32_t P20:1; /*!< bit: 20 Output Slew Rate Control Enable */ 6933 uint32_t P21:1; /*!< bit: 21 Output Slew Rate Control Enable */ 6934 uint32_t P22:1; /*!< bit: 22 Output Slew Rate Control Enable */ 6935 uint32_t P23:1; /*!< bit: 23 Output Slew Rate Control Enable */ 6936 uint32_t P24:1; /*!< bit: 24 Output Slew Rate Control Enable */ 6937 uint32_t P25:1; /*!< bit: 25 Output Slew Rate Control Enable */ 6938 uint32_t P26:1; /*!< bit: 26 Output Slew Rate Control Enable */ 6939 uint32_t P27:1; /*!< bit: 27 Output Slew Rate Control Enable */ 6940 uint32_t P28:1; /*!< bit: 28 Output Slew Rate Control Enable */ 6941 uint32_t P29:1; /*!< bit: 29 Output Slew Rate Control Enable */ 6942 uint32_t P30:1; /*!< bit: 30 Output Slew Rate Control Enable */ 6943 uint32_t P31:1; /*!< bit: 31 Output Slew Rate Control Enable */ 6944 } bit; /*!< Structure used for bit access */ 6945 uint32_t reg; /*!< Type used for register access */ 6946 } GPIO_OSRR0_Type; 6947 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6948 6949 #define GPIO_OSRR0_OFFSET 0x130 /**< \brief (GPIO_OSRR0 offset) Output Slew Rate Register 0 */ 6950 6951 #define GPIO_OSRR0_P0_Pos 0 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6952 #define GPIO_OSRR0_P0 (_U_(0x1) << GPIO_OSRR0_P0_Pos) 6953 #define GPIO_OSRR0_P1_Pos 1 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6954 #define GPIO_OSRR0_P1 (_U_(0x1) << GPIO_OSRR0_P1_Pos) 6955 #define GPIO_OSRR0_P2_Pos 2 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6956 #define GPIO_OSRR0_P2 (_U_(0x1) << GPIO_OSRR0_P2_Pos) 6957 #define GPIO_OSRR0_P3_Pos 3 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6958 #define GPIO_OSRR0_P3 (_U_(0x1) << GPIO_OSRR0_P3_Pos) 6959 #define GPIO_OSRR0_P4_Pos 4 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6960 #define GPIO_OSRR0_P4 (_U_(0x1) << GPIO_OSRR0_P4_Pos) 6961 #define GPIO_OSRR0_P5_Pos 5 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6962 #define GPIO_OSRR0_P5 (_U_(0x1) << GPIO_OSRR0_P5_Pos) 6963 #define GPIO_OSRR0_P6_Pos 6 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6964 #define GPIO_OSRR0_P6 (_U_(0x1) << GPIO_OSRR0_P6_Pos) 6965 #define GPIO_OSRR0_P7_Pos 7 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6966 #define GPIO_OSRR0_P7 (_U_(0x1) << GPIO_OSRR0_P7_Pos) 6967 #define GPIO_OSRR0_P8_Pos 8 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6968 #define GPIO_OSRR0_P8 (_U_(0x1) << GPIO_OSRR0_P8_Pos) 6969 #define GPIO_OSRR0_P9_Pos 9 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6970 #define GPIO_OSRR0_P9 (_U_(0x1) << GPIO_OSRR0_P9_Pos) 6971 #define GPIO_OSRR0_P10_Pos 10 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6972 #define GPIO_OSRR0_P10 (_U_(0x1) << GPIO_OSRR0_P10_Pos) 6973 #define GPIO_OSRR0_P11_Pos 11 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6974 #define GPIO_OSRR0_P11 (_U_(0x1) << GPIO_OSRR0_P11_Pos) 6975 #define GPIO_OSRR0_P12_Pos 12 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6976 #define GPIO_OSRR0_P12 (_U_(0x1) << GPIO_OSRR0_P12_Pos) 6977 #define GPIO_OSRR0_P13_Pos 13 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6978 #define GPIO_OSRR0_P13 (_U_(0x1) << GPIO_OSRR0_P13_Pos) 6979 #define GPIO_OSRR0_P14_Pos 14 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6980 #define GPIO_OSRR0_P14 (_U_(0x1) << GPIO_OSRR0_P14_Pos) 6981 #define GPIO_OSRR0_P15_Pos 15 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6982 #define GPIO_OSRR0_P15 (_U_(0x1) << GPIO_OSRR0_P15_Pos) 6983 #define GPIO_OSRR0_P16_Pos 16 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6984 #define GPIO_OSRR0_P16 (_U_(0x1) << GPIO_OSRR0_P16_Pos) 6985 #define GPIO_OSRR0_P17_Pos 17 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6986 #define GPIO_OSRR0_P17 (_U_(0x1) << GPIO_OSRR0_P17_Pos) 6987 #define GPIO_OSRR0_P18_Pos 18 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6988 #define GPIO_OSRR0_P18 (_U_(0x1) << GPIO_OSRR0_P18_Pos) 6989 #define GPIO_OSRR0_P19_Pos 19 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6990 #define GPIO_OSRR0_P19 (_U_(0x1) << GPIO_OSRR0_P19_Pos) 6991 #define GPIO_OSRR0_P20_Pos 20 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6992 #define GPIO_OSRR0_P20 (_U_(0x1) << GPIO_OSRR0_P20_Pos) 6993 #define GPIO_OSRR0_P21_Pos 21 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6994 #define GPIO_OSRR0_P21 (_U_(0x1) << GPIO_OSRR0_P21_Pos) 6995 #define GPIO_OSRR0_P22_Pos 22 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6996 #define GPIO_OSRR0_P22 (_U_(0x1) << GPIO_OSRR0_P22_Pos) 6997 #define GPIO_OSRR0_P23_Pos 23 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 6998 #define GPIO_OSRR0_P23 (_U_(0x1) << GPIO_OSRR0_P23_Pos) 6999 #define GPIO_OSRR0_P24_Pos 24 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7000 #define GPIO_OSRR0_P24 (_U_(0x1) << GPIO_OSRR0_P24_Pos) 7001 #define GPIO_OSRR0_P25_Pos 25 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7002 #define GPIO_OSRR0_P25 (_U_(0x1) << GPIO_OSRR0_P25_Pos) 7003 #define GPIO_OSRR0_P26_Pos 26 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7004 #define GPIO_OSRR0_P26 (_U_(0x1) << GPIO_OSRR0_P26_Pos) 7005 #define GPIO_OSRR0_P27_Pos 27 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7006 #define GPIO_OSRR0_P27 (_U_(0x1) << GPIO_OSRR0_P27_Pos) 7007 #define GPIO_OSRR0_P28_Pos 28 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7008 #define GPIO_OSRR0_P28 (_U_(0x1) << GPIO_OSRR0_P28_Pos) 7009 #define GPIO_OSRR0_P29_Pos 29 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7010 #define GPIO_OSRR0_P29 (_U_(0x1) << GPIO_OSRR0_P29_Pos) 7011 #define GPIO_OSRR0_P30_Pos 30 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7012 #define GPIO_OSRR0_P30 (_U_(0x1) << GPIO_OSRR0_P30_Pos) 7013 #define GPIO_OSRR0_P31_Pos 31 /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */ 7014 #define GPIO_OSRR0_P31 (_U_(0x1) << GPIO_OSRR0_P31_Pos) 7015 #define GPIO_OSRR0_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OSRR0) MASK Register */ 7016 7017 /* -------- GPIO_OSRR0S : (GPIO Offset: 0x134) (R/W 32) port Output Slew Rate Register 0 - Set -------- */ 7018 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7019 typedef union { 7020 struct { 7021 uint32_t P0:1; /*!< bit: 0 Output Slew Rate Control Enable */ 7022 uint32_t P1:1; /*!< bit: 1 Output Slew Rate Control Enable */ 7023 uint32_t P2:1; /*!< bit: 2 Output Slew Rate Control Enable */ 7024 uint32_t P3:1; /*!< bit: 3 Output Slew Rate Control Enable */ 7025 uint32_t P4:1; /*!< bit: 4 Output Slew Rate Control Enable */ 7026 uint32_t P5:1; /*!< bit: 5 Output Slew Rate Control Enable */ 7027 uint32_t P6:1; /*!< bit: 6 Output Slew Rate Control Enable */ 7028 uint32_t P7:1; /*!< bit: 7 Output Slew Rate Control Enable */ 7029 uint32_t P8:1; /*!< bit: 8 Output Slew Rate Control Enable */ 7030 uint32_t P9:1; /*!< bit: 9 Output Slew Rate Control Enable */ 7031 uint32_t P10:1; /*!< bit: 10 Output Slew Rate Control Enable */ 7032 uint32_t P11:1; /*!< bit: 11 Output Slew Rate Control Enable */ 7033 uint32_t P12:1; /*!< bit: 12 Output Slew Rate Control Enable */ 7034 uint32_t P13:1; /*!< bit: 13 Output Slew Rate Control Enable */ 7035 uint32_t P14:1; /*!< bit: 14 Output Slew Rate Control Enable */ 7036 uint32_t P15:1; /*!< bit: 15 Output Slew Rate Control Enable */ 7037 uint32_t P16:1; /*!< bit: 16 Output Slew Rate Control Enable */ 7038 uint32_t P17:1; /*!< bit: 17 Output Slew Rate Control Enable */ 7039 uint32_t P18:1; /*!< bit: 18 Output Slew Rate Control Enable */ 7040 uint32_t P19:1; /*!< bit: 19 Output Slew Rate Control Enable */ 7041 uint32_t P20:1; /*!< bit: 20 Output Slew Rate Control Enable */ 7042 uint32_t P21:1; /*!< bit: 21 Output Slew Rate Control Enable */ 7043 uint32_t P22:1; /*!< bit: 22 Output Slew Rate Control Enable */ 7044 uint32_t P23:1; /*!< bit: 23 Output Slew Rate Control Enable */ 7045 uint32_t P24:1; /*!< bit: 24 Output Slew Rate Control Enable */ 7046 uint32_t P25:1; /*!< bit: 25 Output Slew Rate Control Enable */ 7047 uint32_t P26:1; /*!< bit: 26 Output Slew Rate Control Enable */ 7048 uint32_t P27:1; /*!< bit: 27 Output Slew Rate Control Enable */ 7049 uint32_t P28:1; /*!< bit: 28 Output Slew Rate Control Enable */ 7050 uint32_t P29:1; /*!< bit: 29 Output Slew Rate Control Enable */ 7051 uint32_t P30:1; /*!< bit: 30 Output Slew Rate Control Enable */ 7052 uint32_t P31:1; /*!< bit: 31 Output Slew Rate Control Enable */ 7053 } bit; /*!< Structure used for bit access */ 7054 uint32_t reg; /*!< Type used for register access */ 7055 } GPIO_OSRR0S_Type; 7056 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7057 7058 #define GPIO_OSRR0S_OFFSET 0x134 /**< \brief (GPIO_OSRR0S offset) Output Slew Rate Register 0 - Set */ 7059 7060 #define GPIO_OSRR0S_P0_Pos 0 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7061 #define GPIO_OSRR0S_P0 (_U_(0x1) << GPIO_OSRR0S_P0_Pos) 7062 #define GPIO_OSRR0S_P1_Pos 1 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7063 #define GPIO_OSRR0S_P1 (_U_(0x1) << GPIO_OSRR0S_P1_Pos) 7064 #define GPIO_OSRR0S_P2_Pos 2 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7065 #define GPIO_OSRR0S_P2 (_U_(0x1) << GPIO_OSRR0S_P2_Pos) 7066 #define GPIO_OSRR0S_P3_Pos 3 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7067 #define GPIO_OSRR0S_P3 (_U_(0x1) << GPIO_OSRR0S_P3_Pos) 7068 #define GPIO_OSRR0S_P4_Pos 4 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7069 #define GPIO_OSRR0S_P4 (_U_(0x1) << GPIO_OSRR0S_P4_Pos) 7070 #define GPIO_OSRR0S_P5_Pos 5 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7071 #define GPIO_OSRR0S_P5 (_U_(0x1) << GPIO_OSRR0S_P5_Pos) 7072 #define GPIO_OSRR0S_P6_Pos 6 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7073 #define GPIO_OSRR0S_P6 (_U_(0x1) << GPIO_OSRR0S_P6_Pos) 7074 #define GPIO_OSRR0S_P7_Pos 7 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7075 #define GPIO_OSRR0S_P7 (_U_(0x1) << GPIO_OSRR0S_P7_Pos) 7076 #define GPIO_OSRR0S_P8_Pos 8 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7077 #define GPIO_OSRR0S_P8 (_U_(0x1) << GPIO_OSRR0S_P8_Pos) 7078 #define GPIO_OSRR0S_P9_Pos 9 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7079 #define GPIO_OSRR0S_P9 (_U_(0x1) << GPIO_OSRR0S_P9_Pos) 7080 #define GPIO_OSRR0S_P10_Pos 10 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7081 #define GPIO_OSRR0S_P10 (_U_(0x1) << GPIO_OSRR0S_P10_Pos) 7082 #define GPIO_OSRR0S_P11_Pos 11 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7083 #define GPIO_OSRR0S_P11 (_U_(0x1) << GPIO_OSRR0S_P11_Pos) 7084 #define GPIO_OSRR0S_P12_Pos 12 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7085 #define GPIO_OSRR0S_P12 (_U_(0x1) << GPIO_OSRR0S_P12_Pos) 7086 #define GPIO_OSRR0S_P13_Pos 13 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7087 #define GPIO_OSRR0S_P13 (_U_(0x1) << GPIO_OSRR0S_P13_Pos) 7088 #define GPIO_OSRR0S_P14_Pos 14 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7089 #define GPIO_OSRR0S_P14 (_U_(0x1) << GPIO_OSRR0S_P14_Pos) 7090 #define GPIO_OSRR0S_P15_Pos 15 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7091 #define GPIO_OSRR0S_P15 (_U_(0x1) << GPIO_OSRR0S_P15_Pos) 7092 #define GPIO_OSRR0S_P16_Pos 16 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7093 #define GPIO_OSRR0S_P16 (_U_(0x1) << GPIO_OSRR0S_P16_Pos) 7094 #define GPIO_OSRR0S_P17_Pos 17 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7095 #define GPIO_OSRR0S_P17 (_U_(0x1) << GPIO_OSRR0S_P17_Pos) 7096 #define GPIO_OSRR0S_P18_Pos 18 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7097 #define GPIO_OSRR0S_P18 (_U_(0x1) << GPIO_OSRR0S_P18_Pos) 7098 #define GPIO_OSRR0S_P19_Pos 19 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7099 #define GPIO_OSRR0S_P19 (_U_(0x1) << GPIO_OSRR0S_P19_Pos) 7100 #define GPIO_OSRR0S_P20_Pos 20 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7101 #define GPIO_OSRR0S_P20 (_U_(0x1) << GPIO_OSRR0S_P20_Pos) 7102 #define GPIO_OSRR0S_P21_Pos 21 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7103 #define GPIO_OSRR0S_P21 (_U_(0x1) << GPIO_OSRR0S_P21_Pos) 7104 #define GPIO_OSRR0S_P22_Pos 22 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7105 #define GPIO_OSRR0S_P22 (_U_(0x1) << GPIO_OSRR0S_P22_Pos) 7106 #define GPIO_OSRR0S_P23_Pos 23 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7107 #define GPIO_OSRR0S_P23 (_U_(0x1) << GPIO_OSRR0S_P23_Pos) 7108 #define GPIO_OSRR0S_P24_Pos 24 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7109 #define GPIO_OSRR0S_P24 (_U_(0x1) << GPIO_OSRR0S_P24_Pos) 7110 #define GPIO_OSRR0S_P25_Pos 25 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7111 #define GPIO_OSRR0S_P25 (_U_(0x1) << GPIO_OSRR0S_P25_Pos) 7112 #define GPIO_OSRR0S_P26_Pos 26 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7113 #define GPIO_OSRR0S_P26 (_U_(0x1) << GPIO_OSRR0S_P26_Pos) 7114 #define GPIO_OSRR0S_P27_Pos 27 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7115 #define GPIO_OSRR0S_P27 (_U_(0x1) << GPIO_OSRR0S_P27_Pos) 7116 #define GPIO_OSRR0S_P28_Pos 28 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7117 #define GPIO_OSRR0S_P28 (_U_(0x1) << GPIO_OSRR0S_P28_Pos) 7118 #define GPIO_OSRR0S_P29_Pos 29 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7119 #define GPIO_OSRR0S_P29 (_U_(0x1) << GPIO_OSRR0S_P29_Pos) 7120 #define GPIO_OSRR0S_P30_Pos 30 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7121 #define GPIO_OSRR0S_P30 (_U_(0x1) << GPIO_OSRR0S_P30_Pos) 7122 #define GPIO_OSRR0S_P31_Pos 31 /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */ 7123 #define GPIO_OSRR0S_P31 (_U_(0x1) << GPIO_OSRR0S_P31_Pos) 7124 #define GPIO_OSRR0S_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OSRR0S) MASK Register */ 7125 7126 /* -------- GPIO_OSRR0C : (GPIO Offset: 0x138) (R/W 32) port Output Slew Rate Register 0 - Clear -------- */ 7127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7128 typedef union { 7129 struct { 7130 uint32_t P0:1; /*!< bit: 0 Output Slew Rate Control Enable */ 7131 uint32_t P1:1; /*!< bit: 1 Output Slew Rate Control Enable */ 7132 uint32_t P2:1; /*!< bit: 2 Output Slew Rate Control Enable */ 7133 uint32_t P3:1; /*!< bit: 3 Output Slew Rate Control Enable */ 7134 uint32_t P4:1; /*!< bit: 4 Output Slew Rate Control Enable */ 7135 uint32_t P5:1; /*!< bit: 5 Output Slew Rate Control Enable */ 7136 uint32_t P6:1; /*!< bit: 6 Output Slew Rate Control Enable */ 7137 uint32_t P7:1; /*!< bit: 7 Output Slew Rate Control Enable */ 7138 uint32_t P8:1; /*!< bit: 8 Output Slew Rate Control Enable */ 7139 uint32_t P9:1; /*!< bit: 9 Output Slew Rate Control Enable */ 7140 uint32_t P10:1; /*!< bit: 10 Output Slew Rate Control Enable */ 7141 uint32_t P11:1; /*!< bit: 11 Output Slew Rate Control Enable */ 7142 uint32_t P12:1; /*!< bit: 12 Output Slew Rate Control Enable */ 7143 uint32_t P13:1; /*!< bit: 13 Output Slew Rate Control Enable */ 7144 uint32_t P14:1; /*!< bit: 14 Output Slew Rate Control Enable */ 7145 uint32_t P15:1; /*!< bit: 15 Output Slew Rate Control Enable */ 7146 uint32_t P16:1; /*!< bit: 16 Output Slew Rate Control Enable */ 7147 uint32_t P17:1; /*!< bit: 17 Output Slew Rate Control Enable */ 7148 uint32_t P18:1; /*!< bit: 18 Output Slew Rate Control Enable */ 7149 uint32_t P19:1; /*!< bit: 19 Output Slew Rate Control Enable */ 7150 uint32_t P20:1; /*!< bit: 20 Output Slew Rate Control Enable */ 7151 uint32_t P21:1; /*!< bit: 21 Output Slew Rate Control Enable */ 7152 uint32_t P22:1; /*!< bit: 22 Output Slew Rate Control Enable */ 7153 uint32_t P23:1; /*!< bit: 23 Output Slew Rate Control Enable */ 7154 uint32_t P24:1; /*!< bit: 24 Output Slew Rate Control Enable */ 7155 uint32_t P25:1; /*!< bit: 25 Output Slew Rate Control Enable */ 7156 uint32_t P26:1; /*!< bit: 26 Output Slew Rate Control Enable */ 7157 uint32_t P27:1; /*!< bit: 27 Output Slew Rate Control Enable */ 7158 uint32_t P28:1; /*!< bit: 28 Output Slew Rate Control Enable */ 7159 uint32_t P29:1; /*!< bit: 29 Output Slew Rate Control Enable */ 7160 uint32_t P30:1; /*!< bit: 30 Output Slew Rate Control Enable */ 7161 uint32_t P31:1; /*!< bit: 31 Output Slew Rate Control Enable */ 7162 } bit; /*!< Structure used for bit access */ 7163 uint32_t reg; /*!< Type used for register access */ 7164 } GPIO_OSRR0C_Type; 7165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7166 7167 #define GPIO_OSRR0C_OFFSET 0x138 /**< \brief (GPIO_OSRR0C offset) Output Slew Rate Register 0 - Clear */ 7168 7169 #define GPIO_OSRR0C_P0_Pos 0 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7170 #define GPIO_OSRR0C_P0 (_U_(0x1) << GPIO_OSRR0C_P0_Pos) 7171 #define GPIO_OSRR0C_P1_Pos 1 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7172 #define GPIO_OSRR0C_P1 (_U_(0x1) << GPIO_OSRR0C_P1_Pos) 7173 #define GPIO_OSRR0C_P2_Pos 2 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7174 #define GPIO_OSRR0C_P2 (_U_(0x1) << GPIO_OSRR0C_P2_Pos) 7175 #define GPIO_OSRR0C_P3_Pos 3 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7176 #define GPIO_OSRR0C_P3 (_U_(0x1) << GPIO_OSRR0C_P3_Pos) 7177 #define GPIO_OSRR0C_P4_Pos 4 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7178 #define GPIO_OSRR0C_P4 (_U_(0x1) << GPIO_OSRR0C_P4_Pos) 7179 #define GPIO_OSRR0C_P5_Pos 5 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7180 #define GPIO_OSRR0C_P5 (_U_(0x1) << GPIO_OSRR0C_P5_Pos) 7181 #define GPIO_OSRR0C_P6_Pos 6 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7182 #define GPIO_OSRR0C_P6 (_U_(0x1) << GPIO_OSRR0C_P6_Pos) 7183 #define GPIO_OSRR0C_P7_Pos 7 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7184 #define GPIO_OSRR0C_P7 (_U_(0x1) << GPIO_OSRR0C_P7_Pos) 7185 #define GPIO_OSRR0C_P8_Pos 8 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7186 #define GPIO_OSRR0C_P8 (_U_(0x1) << GPIO_OSRR0C_P8_Pos) 7187 #define GPIO_OSRR0C_P9_Pos 9 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7188 #define GPIO_OSRR0C_P9 (_U_(0x1) << GPIO_OSRR0C_P9_Pos) 7189 #define GPIO_OSRR0C_P10_Pos 10 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7190 #define GPIO_OSRR0C_P10 (_U_(0x1) << GPIO_OSRR0C_P10_Pos) 7191 #define GPIO_OSRR0C_P11_Pos 11 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7192 #define GPIO_OSRR0C_P11 (_U_(0x1) << GPIO_OSRR0C_P11_Pos) 7193 #define GPIO_OSRR0C_P12_Pos 12 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7194 #define GPIO_OSRR0C_P12 (_U_(0x1) << GPIO_OSRR0C_P12_Pos) 7195 #define GPIO_OSRR0C_P13_Pos 13 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7196 #define GPIO_OSRR0C_P13 (_U_(0x1) << GPIO_OSRR0C_P13_Pos) 7197 #define GPIO_OSRR0C_P14_Pos 14 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7198 #define GPIO_OSRR0C_P14 (_U_(0x1) << GPIO_OSRR0C_P14_Pos) 7199 #define GPIO_OSRR0C_P15_Pos 15 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7200 #define GPIO_OSRR0C_P15 (_U_(0x1) << GPIO_OSRR0C_P15_Pos) 7201 #define GPIO_OSRR0C_P16_Pos 16 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7202 #define GPIO_OSRR0C_P16 (_U_(0x1) << GPIO_OSRR0C_P16_Pos) 7203 #define GPIO_OSRR0C_P17_Pos 17 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7204 #define GPIO_OSRR0C_P17 (_U_(0x1) << GPIO_OSRR0C_P17_Pos) 7205 #define GPIO_OSRR0C_P18_Pos 18 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7206 #define GPIO_OSRR0C_P18 (_U_(0x1) << GPIO_OSRR0C_P18_Pos) 7207 #define GPIO_OSRR0C_P19_Pos 19 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7208 #define GPIO_OSRR0C_P19 (_U_(0x1) << GPIO_OSRR0C_P19_Pos) 7209 #define GPIO_OSRR0C_P20_Pos 20 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7210 #define GPIO_OSRR0C_P20 (_U_(0x1) << GPIO_OSRR0C_P20_Pos) 7211 #define GPIO_OSRR0C_P21_Pos 21 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7212 #define GPIO_OSRR0C_P21 (_U_(0x1) << GPIO_OSRR0C_P21_Pos) 7213 #define GPIO_OSRR0C_P22_Pos 22 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7214 #define GPIO_OSRR0C_P22 (_U_(0x1) << GPIO_OSRR0C_P22_Pos) 7215 #define GPIO_OSRR0C_P23_Pos 23 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7216 #define GPIO_OSRR0C_P23 (_U_(0x1) << GPIO_OSRR0C_P23_Pos) 7217 #define GPIO_OSRR0C_P24_Pos 24 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7218 #define GPIO_OSRR0C_P24 (_U_(0x1) << GPIO_OSRR0C_P24_Pos) 7219 #define GPIO_OSRR0C_P25_Pos 25 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7220 #define GPIO_OSRR0C_P25 (_U_(0x1) << GPIO_OSRR0C_P25_Pos) 7221 #define GPIO_OSRR0C_P26_Pos 26 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7222 #define GPIO_OSRR0C_P26 (_U_(0x1) << GPIO_OSRR0C_P26_Pos) 7223 #define GPIO_OSRR0C_P27_Pos 27 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7224 #define GPIO_OSRR0C_P27 (_U_(0x1) << GPIO_OSRR0C_P27_Pos) 7225 #define GPIO_OSRR0C_P28_Pos 28 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7226 #define GPIO_OSRR0C_P28 (_U_(0x1) << GPIO_OSRR0C_P28_Pos) 7227 #define GPIO_OSRR0C_P29_Pos 29 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7228 #define GPIO_OSRR0C_P29 (_U_(0x1) << GPIO_OSRR0C_P29_Pos) 7229 #define GPIO_OSRR0C_P30_Pos 30 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7230 #define GPIO_OSRR0C_P30 (_U_(0x1) << GPIO_OSRR0C_P30_Pos) 7231 #define GPIO_OSRR0C_P31_Pos 31 /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */ 7232 #define GPIO_OSRR0C_P31 (_U_(0x1) << GPIO_OSRR0C_P31_Pos) 7233 #define GPIO_OSRR0C_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OSRR0C) MASK Register */ 7234 7235 /* -------- GPIO_OSRR0T : (GPIO Offset: 0x13C) (R/W 32) port Output Slew Rate Register 0 - Toggle -------- */ 7236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7237 typedef union { 7238 struct { 7239 uint32_t P0:1; /*!< bit: 0 Output Slew Rate Control Enable */ 7240 uint32_t P1:1; /*!< bit: 1 Output Slew Rate Control Enable */ 7241 uint32_t P2:1; /*!< bit: 2 Output Slew Rate Control Enable */ 7242 uint32_t P3:1; /*!< bit: 3 Output Slew Rate Control Enable */ 7243 uint32_t P4:1; /*!< bit: 4 Output Slew Rate Control Enable */ 7244 uint32_t P5:1; /*!< bit: 5 Output Slew Rate Control Enable */ 7245 uint32_t P6:1; /*!< bit: 6 Output Slew Rate Control Enable */ 7246 uint32_t P7:1; /*!< bit: 7 Output Slew Rate Control Enable */ 7247 uint32_t P8:1; /*!< bit: 8 Output Slew Rate Control Enable */ 7248 uint32_t P9:1; /*!< bit: 9 Output Slew Rate Control Enable */ 7249 uint32_t P10:1; /*!< bit: 10 Output Slew Rate Control Enable */ 7250 uint32_t P11:1; /*!< bit: 11 Output Slew Rate Control Enable */ 7251 uint32_t P12:1; /*!< bit: 12 Output Slew Rate Control Enable */ 7252 uint32_t P13:1; /*!< bit: 13 Output Slew Rate Control Enable */ 7253 uint32_t P14:1; /*!< bit: 14 Output Slew Rate Control Enable */ 7254 uint32_t P15:1; /*!< bit: 15 Output Slew Rate Control Enable */ 7255 uint32_t P16:1; /*!< bit: 16 Output Slew Rate Control Enable */ 7256 uint32_t P17:1; /*!< bit: 17 Output Slew Rate Control Enable */ 7257 uint32_t P18:1; /*!< bit: 18 Output Slew Rate Control Enable */ 7258 uint32_t P19:1; /*!< bit: 19 Output Slew Rate Control Enable */ 7259 uint32_t P20:1; /*!< bit: 20 Output Slew Rate Control Enable */ 7260 uint32_t P21:1; /*!< bit: 21 Output Slew Rate Control Enable */ 7261 uint32_t P22:1; /*!< bit: 22 Output Slew Rate Control Enable */ 7262 uint32_t P23:1; /*!< bit: 23 Output Slew Rate Control Enable */ 7263 uint32_t P24:1; /*!< bit: 24 Output Slew Rate Control Enable */ 7264 uint32_t P25:1; /*!< bit: 25 Output Slew Rate Control Enable */ 7265 uint32_t P26:1; /*!< bit: 26 Output Slew Rate Control Enable */ 7266 uint32_t P27:1; /*!< bit: 27 Output Slew Rate Control Enable */ 7267 uint32_t P28:1; /*!< bit: 28 Output Slew Rate Control Enable */ 7268 uint32_t P29:1; /*!< bit: 29 Output Slew Rate Control Enable */ 7269 uint32_t P30:1; /*!< bit: 30 Output Slew Rate Control Enable */ 7270 uint32_t P31:1; /*!< bit: 31 Output Slew Rate Control Enable */ 7271 } bit; /*!< Structure used for bit access */ 7272 uint32_t reg; /*!< Type used for register access */ 7273 } GPIO_OSRR0T_Type; 7274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7275 7276 #define GPIO_OSRR0T_OFFSET 0x13C /**< \brief (GPIO_OSRR0T offset) Output Slew Rate Register 0 - Toggle */ 7277 7278 #define GPIO_OSRR0T_P0_Pos 0 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7279 #define GPIO_OSRR0T_P0 (_U_(0x1) << GPIO_OSRR0T_P0_Pos) 7280 #define GPIO_OSRR0T_P1_Pos 1 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7281 #define GPIO_OSRR0T_P1 (_U_(0x1) << GPIO_OSRR0T_P1_Pos) 7282 #define GPIO_OSRR0T_P2_Pos 2 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7283 #define GPIO_OSRR0T_P2 (_U_(0x1) << GPIO_OSRR0T_P2_Pos) 7284 #define GPIO_OSRR0T_P3_Pos 3 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7285 #define GPIO_OSRR0T_P3 (_U_(0x1) << GPIO_OSRR0T_P3_Pos) 7286 #define GPIO_OSRR0T_P4_Pos 4 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7287 #define GPIO_OSRR0T_P4 (_U_(0x1) << GPIO_OSRR0T_P4_Pos) 7288 #define GPIO_OSRR0T_P5_Pos 5 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7289 #define GPIO_OSRR0T_P5 (_U_(0x1) << GPIO_OSRR0T_P5_Pos) 7290 #define GPIO_OSRR0T_P6_Pos 6 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7291 #define GPIO_OSRR0T_P6 (_U_(0x1) << GPIO_OSRR0T_P6_Pos) 7292 #define GPIO_OSRR0T_P7_Pos 7 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7293 #define GPIO_OSRR0T_P7 (_U_(0x1) << GPIO_OSRR0T_P7_Pos) 7294 #define GPIO_OSRR0T_P8_Pos 8 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7295 #define GPIO_OSRR0T_P8 (_U_(0x1) << GPIO_OSRR0T_P8_Pos) 7296 #define GPIO_OSRR0T_P9_Pos 9 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7297 #define GPIO_OSRR0T_P9 (_U_(0x1) << GPIO_OSRR0T_P9_Pos) 7298 #define GPIO_OSRR0T_P10_Pos 10 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7299 #define GPIO_OSRR0T_P10 (_U_(0x1) << GPIO_OSRR0T_P10_Pos) 7300 #define GPIO_OSRR0T_P11_Pos 11 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7301 #define GPIO_OSRR0T_P11 (_U_(0x1) << GPIO_OSRR0T_P11_Pos) 7302 #define GPIO_OSRR0T_P12_Pos 12 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7303 #define GPIO_OSRR0T_P12 (_U_(0x1) << GPIO_OSRR0T_P12_Pos) 7304 #define GPIO_OSRR0T_P13_Pos 13 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7305 #define GPIO_OSRR0T_P13 (_U_(0x1) << GPIO_OSRR0T_P13_Pos) 7306 #define GPIO_OSRR0T_P14_Pos 14 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7307 #define GPIO_OSRR0T_P14 (_U_(0x1) << GPIO_OSRR0T_P14_Pos) 7308 #define GPIO_OSRR0T_P15_Pos 15 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7309 #define GPIO_OSRR0T_P15 (_U_(0x1) << GPIO_OSRR0T_P15_Pos) 7310 #define GPIO_OSRR0T_P16_Pos 16 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7311 #define GPIO_OSRR0T_P16 (_U_(0x1) << GPIO_OSRR0T_P16_Pos) 7312 #define GPIO_OSRR0T_P17_Pos 17 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7313 #define GPIO_OSRR0T_P17 (_U_(0x1) << GPIO_OSRR0T_P17_Pos) 7314 #define GPIO_OSRR0T_P18_Pos 18 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7315 #define GPIO_OSRR0T_P18 (_U_(0x1) << GPIO_OSRR0T_P18_Pos) 7316 #define GPIO_OSRR0T_P19_Pos 19 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7317 #define GPIO_OSRR0T_P19 (_U_(0x1) << GPIO_OSRR0T_P19_Pos) 7318 #define GPIO_OSRR0T_P20_Pos 20 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7319 #define GPIO_OSRR0T_P20 (_U_(0x1) << GPIO_OSRR0T_P20_Pos) 7320 #define GPIO_OSRR0T_P21_Pos 21 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7321 #define GPIO_OSRR0T_P21 (_U_(0x1) << GPIO_OSRR0T_P21_Pos) 7322 #define GPIO_OSRR0T_P22_Pos 22 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7323 #define GPIO_OSRR0T_P22 (_U_(0x1) << GPIO_OSRR0T_P22_Pos) 7324 #define GPIO_OSRR0T_P23_Pos 23 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7325 #define GPIO_OSRR0T_P23 (_U_(0x1) << GPIO_OSRR0T_P23_Pos) 7326 #define GPIO_OSRR0T_P24_Pos 24 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7327 #define GPIO_OSRR0T_P24 (_U_(0x1) << GPIO_OSRR0T_P24_Pos) 7328 #define GPIO_OSRR0T_P25_Pos 25 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7329 #define GPIO_OSRR0T_P25 (_U_(0x1) << GPIO_OSRR0T_P25_Pos) 7330 #define GPIO_OSRR0T_P26_Pos 26 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7331 #define GPIO_OSRR0T_P26 (_U_(0x1) << GPIO_OSRR0T_P26_Pos) 7332 #define GPIO_OSRR0T_P27_Pos 27 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7333 #define GPIO_OSRR0T_P27 (_U_(0x1) << GPIO_OSRR0T_P27_Pos) 7334 #define GPIO_OSRR0T_P28_Pos 28 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7335 #define GPIO_OSRR0T_P28 (_U_(0x1) << GPIO_OSRR0T_P28_Pos) 7336 #define GPIO_OSRR0T_P29_Pos 29 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7337 #define GPIO_OSRR0T_P29 (_U_(0x1) << GPIO_OSRR0T_P29_Pos) 7338 #define GPIO_OSRR0T_P30_Pos 30 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7339 #define GPIO_OSRR0T_P30 (_U_(0x1) << GPIO_OSRR0T_P30_Pos) 7340 #define GPIO_OSRR0T_P31_Pos 31 /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */ 7341 #define GPIO_OSRR0T_P31 (_U_(0x1) << GPIO_OSRR0T_P31_Pos) 7342 #define GPIO_OSRR0T_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_OSRR0T) MASK Register */ 7343 7344 /* -------- GPIO_STER : (GPIO Offset: 0x160) (R/W 32) port Schmitt Trigger Enable Register -------- */ 7345 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7346 typedef union { 7347 struct { 7348 uint32_t P0:1; /*!< bit: 0 Schmitt Trigger Enable */ 7349 uint32_t P1:1; /*!< bit: 1 Schmitt Trigger Enable */ 7350 uint32_t P2:1; /*!< bit: 2 Schmitt Trigger Enable */ 7351 uint32_t P3:1; /*!< bit: 3 Schmitt Trigger Enable */ 7352 uint32_t P4:1; /*!< bit: 4 Schmitt Trigger Enable */ 7353 uint32_t P5:1; /*!< bit: 5 Schmitt Trigger Enable */ 7354 uint32_t P6:1; /*!< bit: 6 Schmitt Trigger Enable */ 7355 uint32_t P7:1; /*!< bit: 7 Schmitt Trigger Enable */ 7356 uint32_t P8:1; /*!< bit: 8 Schmitt Trigger Enable */ 7357 uint32_t P9:1; /*!< bit: 9 Schmitt Trigger Enable */ 7358 uint32_t P10:1; /*!< bit: 10 Schmitt Trigger Enable */ 7359 uint32_t P11:1; /*!< bit: 11 Schmitt Trigger Enable */ 7360 uint32_t P12:1; /*!< bit: 12 Schmitt Trigger Enable */ 7361 uint32_t P13:1; /*!< bit: 13 Schmitt Trigger Enable */ 7362 uint32_t P14:1; /*!< bit: 14 Schmitt Trigger Enable */ 7363 uint32_t P15:1; /*!< bit: 15 Schmitt Trigger Enable */ 7364 uint32_t P16:1; /*!< bit: 16 Schmitt Trigger Enable */ 7365 uint32_t P17:1; /*!< bit: 17 Schmitt Trigger Enable */ 7366 uint32_t P18:1; /*!< bit: 18 Schmitt Trigger Enable */ 7367 uint32_t P19:1; /*!< bit: 19 Schmitt Trigger Enable */ 7368 uint32_t P20:1; /*!< bit: 20 Schmitt Trigger Enable */ 7369 uint32_t P21:1; /*!< bit: 21 Schmitt Trigger Enable */ 7370 uint32_t P22:1; /*!< bit: 22 Schmitt Trigger Enable */ 7371 uint32_t P23:1; /*!< bit: 23 Schmitt Trigger Enable */ 7372 uint32_t P24:1; /*!< bit: 24 Schmitt Trigger Enable */ 7373 uint32_t P25:1; /*!< bit: 25 Schmitt Trigger Enable */ 7374 uint32_t P26:1; /*!< bit: 26 Schmitt Trigger Enable */ 7375 uint32_t P27:1; /*!< bit: 27 Schmitt Trigger Enable */ 7376 uint32_t P28:1; /*!< bit: 28 Schmitt Trigger Enable */ 7377 uint32_t P29:1; /*!< bit: 29 Schmitt Trigger Enable */ 7378 uint32_t P30:1; /*!< bit: 30 Schmitt Trigger Enable */ 7379 uint32_t P31:1; /*!< bit: 31 Schmitt Trigger Enable */ 7380 } bit; /*!< Structure used for bit access */ 7381 uint32_t reg; /*!< Type used for register access */ 7382 } GPIO_STER_Type; 7383 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7384 7385 #define GPIO_STER_OFFSET 0x160 /**< \brief (GPIO_STER offset) Schmitt Trigger Enable Register */ 7386 7387 #define GPIO_STER_P0_Pos 0 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7388 #define GPIO_STER_P0 (_U_(0x1) << GPIO_STER_P0_Pos) 7389 #define GPIO_STER_P1_Pos 1 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7390 #define GPIO_STER_P1 (_U_(0x1) << GPIO_STER_P1_Pos) 7391 #define GPIO_STER_P2_Pos 2 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7392 #define GPIO_STER_P2 (_U_(0x1) << GPIO_STER_P2_Pos) 7393 #define GPIO_STER_P3_Pos 3 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7394 #define GPIO_STER_P3 (_U_(0x1) << GPIO_STER_P3_Pos) 7395 #define GPIO_STER_P4_Pos 4 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7396 #define GPIO_STER_P4 (_U_(0x1) << GPIO_STER_P4_Pos) 7397 #define GPIO_STER_P5_Pos 5 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7398 #define GPIO_STER_P5 (_U_(0x1) << GPIO_STER_P5_Pos) 7399 #define GPIO_STER_P6_Pos 6 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7400 #define GPIO_STER_P6 (_U_(0x1) << GPIO_STER_P6_Pos) 7401 #define GPIO_STER_P7_Pos 7 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7402 #define GPIO_STER_P7 (_U_(0x1) << GPIO_STER_P7_Pos) 7403 #define GPIO_STER_P8_Pos 8 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7404 #define GPIO_STER_P8 (_U_(0x1) << GPIO_STER_P8_Pos) 7405 #define GPIO_STER_P9_Pos 9 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7406 #define GPIO_STER_P9 (_U_(0x1) << GPIO_STER_P9_Pos) 7407 #define GPIO_STER_P10_Pos 10 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7408 #define GPIO_STER_P10 (_U_(0x1) << GPIO_STER_P10_Pos) 7409 #define GPIO_STER_P11_Pos 11 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7410 #define GPIO_STER_P11 (_U_(0x1) << GPIO_STER_P11_Pos) 7411 #define GPIO_STER_P12_Pos 12 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7412 #define GPIO_STER_P12 (_U_(0x1) << GPIO_STER_P12_Pos) 7413 #define GPIO_STER_P13_Pos 13 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7414 #define GPIO_STER_P13 (_U_(0x1) << GPIO_STER_P13_Pos) 7415 #define GPIO_STER_P14_Pos 14 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7416 #define GPIO_STER_P14 (_U_(0x1) << GPIO_STER_P14_Pos) 7417 #define GPIO_STER_P15_Pos 15 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7418 #define GPIO_STER_P15 (_U_(0x1) << GPIO_STER_P15_Pos) 7419 #define GPIO_STER_P16_Pos 16 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7420 #define GPIO_STER_P16 (_U_(0x1) << GPIO_STER_P16_Pos) 7421 #define GPIO_STER_P17_Pos 17 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7422 #define GPIO_STER_P17 (_U_(0x1) << GPIO_STER_P17_Pos) 7423 #define GPIO_STER_P18_Pos 18 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7424 #define GPIO_STER_P18 (_U_(0x1) << GPIO_STER_P18_Pos) 7425 #define GPIO_STER_P19_Pos 19 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7426 #define GPIO_STER_P19 (_U_(0x1) << GPIO_STER_P19_Pos) 7427 #define GPIO_STER_P20_Pos 20 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7428 #define GPIO_STER_P20 (_U_(0x1) << GPIO_STER_P20_Pos) 7429 #define GPIO_STER_P21_Pos 21 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7430 #define GPIO_STER_P21 (_U_(0x1) << GPIO_STER_P21_Pos) 7431 #define GPIO_STER_P22_Pos 22 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7432 #define GPIO_STER_P22 (_U_(0x1) << GPIO_STER_P22_Pos) 7433 #define GPIO_STER_P23_Pos 23 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7434 #define GPIO_STER_P23 (_U_(0x1) << GPIO_STER_P23_Pos) 7435 #define GPIO_STER_P24_Pos 24 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7436 #define GPIO_STER_P24 (_U_(0x1) << GPIO_STER_P24_Pos) 7437 #define GPIO_STER_P25_Pos 25 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7438 #define GPIO_STER_P25 (_U_(0x1) << GPIO_STER_P25_Pos) 7439 #define GPIO_STER_P26_Pos 26 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7440 #define GPIO_STER_P26 (_U_(0x1) << GPIO_STER_P26_Pos) 7441 #define GPIO_STER_P27_Pos 27 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7442 #define GPIO_STER_P27 (_U_(0x1) << GPIO_STER_P27_Pos) 7443 #define GPIO_STER_P28_Pos 28 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7444 #define GPIO_STER_P28 (_U_(0x1) << GPIO_STER_P28_Pos) 7445 #define GPIO_STER_P29_Pos 29 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7446 #define GPIO_STER_P29 (_U_(0x1) << GPIO_STER_P29_Pos) 7447 #define GPIO_STER_P30_Pos 30 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7448 #define GPIO_STER_P30 (_U_(0x1) << GPIO_STER_P30_Pos) 7449 #define GPIO_STER_P31_Pos 31 /**< \brief (GPIO_STER) Schmitt Trigger Enable */ 7450 #define GPIO_STER_P31 (_U_(0x1) << GPIO_STER_P31_Pos) 7451 #define GPIO_STER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_STER) MASK Register */ 7452 7453 /* -------- GPIO_STERS : (GPIO Offset: 0x164) (R/W 32) port Schmitt Trigger Enable Register - Set -------- */ 7454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7455 typedef union { 7456 struct { 7457 uint32_t P0:1; /*!< bit: 0 Schmitt Trigger Enable */ 7458 uint32_t P1:1; /*!< bit: 1 Schmitt Trigger Enable */ 7459 uint32_t P2:1; /*!< bit: 2 Schmitt Trigger Enable */ 7460 uint32_t P3:1; /*!< bit: 3 Schmitt Trigger Enable */ 7461 uint32_t P4:1; /*!< bit: 4 Schmitt Trigger Enable */ 7462 uint32_t P5:1; /*!< bit: 5 Schmitt Trigger Enable */ 7463 uint32_t P6:1; /*!< bit: 6 Schmitt Trigger Enable */ 7464 uint32_t P7:1; /*!< bit: 7 Schmitt Trigger Enable */ 7465 uint32_t P8:1; /*!< bit: 8 Schmitt Trigger Enable */ 7466 uint32_t P9:1; /*!< bit: 9 Schmitt Trigger Enable */ 7467 uint32_t P10:1; /*!< bit: 10 Schmitt Trigger Enable */ 7468 uint32_t P11:1; /*!< bit: 11 Schmitt Trigger Enable */ 7469 uint32_t P12:1; /*!< bit: 12 Schmitt Trigger Enable */ 7470 uint32_t P13:1; /*!< bit: 13 Schmitt Trigger Enable */ 7471 uint32_t P14:1; /*!< bit: 14 Schmitt Trigger Enable */ 7472 uint32_t P15:1; /*!< bit: 15 Schmitt Trigger Enable */ 7473 uint32_t P16:1; /*!< bit: 16 Schmitt Trigger Enable */ 7474 uint32_t P17:1; /*!< bit: 17 Schmitt Trigger Enable */ 7475 uint32_t P18:1; /*!< bit: 18 Schmitt Trigger Enable */ 7476 uint32_t P19:1; /*!< bit: 19 Schmitt Trigger Enable */ 7477 uint32_t P20:1; /*!< bit: 20 Schmitt Trigger Enable */ 7478 uint32_t P21:1; /*!< bit: 21 Schmitt Trigger Enable */ 7479 uint32_t P22:1; /*!< bit: 22 Schmitt Trigger Enable */ 7480 uint32_t P23:1; /*!< bit: 23 Schmitt Trigger Enable */ 7481 uint32_t P24:1; /*!< bit: 24 Schmitt Trigger Enable */ 7482 uint32_t P25:1; /*!< bit: 25 Schmitt Trigger Enable */ 7483 uint32_t P26:1; /*!< bit: 26 Schmitt Trigger Enable */ 7484 uint32_t P27:1; /*!< bit: 27 Schmitt Trigger Enable */ 7485 uint32_t P28:1; /*!< bit: 28 Schmitt Trigger Enable */ 7486 uint32_t P29:1; /*!< bit: 29 Schmitt Trigger Enable */ 7487 uint32_t P30:1; /*!< bit: 30 Schmitt Trigger Enable */ 7488 uint32_t P31:1; /*!< bit: 31 Schmitt Trigger Enable */ 7489 } bit; /*!< Structure used for bit access */ 7490 uint32_t reg; /*!< Type used for register access */ 7491 } GPIO_STERS_Type; 7492 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7493 7494 #define GPIO_STERS_OFFSET 0x164 /**< \brief (GPIO_STERS offset) Schmitt Trigger Enable Register - Set */ 7495 7496 #define GPIO_STERS_P0_Pos 0 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7497 #define GPIO_STERS_P0 (_U_(0x1) << GPIO_STERS_P0_Pos) 7498 #define GPIO_STERS_P1_Pos 1 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7499 #define GPIO_STERS_P1 (_U_(0x1) << GPIO_STERS_P1_Pos) 7500 #define GPIO_STERS_P2_Pos 2 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7501 #define GPIO_STERS_P2 (_U_(0x1) << GPIO_STERS_P2_Pos) 7502 #define GPIO_STERS_P3_Pos 3 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7503 #define GPIO_STERS_P3 (_U_(0x1) << GPIO_STERS_P3_Pos) 7504 #define GPIO_STERS_P4_Pos 4 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7505 #define GPIO_STERS_P4 (_U_(0x1) << GPIO_STERS_P4_Pos) 7506 #define GPIO_STERS_P5_Pos 5 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7507 #define GPIO_STERS_P5 (_U_(0x1) << GPIO_STERS_P5_Pos) 7508 #define GPIO_STERS_P6_Pos 6 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7509 #define GPIO_STERS_P6 (_U_(0x1) << GPIO_STERS_P6_Pos) 7510 #define GPIO_STERS_P7_Pos 7 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7511 #define GPIO_STERS_P7 (_U_(0x1) << GPIO_STERS_P7_Pos) 7512 #define GPIO_STERS_P8_Pos 8 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7513 #define GPIO_STERS_P8 (_U_(0x1) << GPIO_STERS_P8_Pos) 7514 #define GPIO_STERS_P9_Pos 9 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7515 #define GPIO_STERS_P9 (_U_(0x1) << GPIO_STERS_P9_Pos) 7516 #define GPIO_STERS_P10_Pos 10 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7517 #define GPIO_STERS_P10 (_U_(0x1) << GPIO_STERS_P10_Pos) 7518 #define GPIO_STERS_P11_Pos 11 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7519 #define GPIO_STERS_P11 (_U_(0x1) << GPIO_STERS_P11_Pos) 7520 #define GPIO_STERS_P12_Pos 12 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7521 #define GPIO_STERS_P12 (_U_(0x1) << GPIO_STERS_P12_Pos) 7522 #define GPIO_STERS_P13_Pos 13 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7523 #define GPIO_STERS_P13 (_U_(0x1) << GPIO_STERS_P13_Pos) 7524 #define GPIO_STERS_P14_Pos 14 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7525 #define GPIO_STERS_P14 (_U_(0x1) << GPIO_STERS_P14_Pos) 7526 #define GPIO_STERS_P15_Pos 15 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7527 #define GPIO_STERS_P15 (_U_(0x1) << GPIO_STERS_P15_Pos) 7528 #define GPIO_STERS_P16_Pos 16 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7529 #define GPIO_STERS_P16 (_U_(0x1) << GPIO_STERS_P16_Pos) 7530 #define GPIO_STERS_P17_Pos 17 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7531 #define GPIO_STERS_P17 (_U_(0x1) << GPIO_STERS_P17_Pos) 7532 #define GPIO_STERS_P18_Pos 18 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7533 #define GPIO_STERS_P18 (_U_(0x1) << GPIO_STERS_P18_Pos) 7534 #define GPIO_STERS_P19_Pos 19 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7535 #define GPIO_STERS_P19 (_U_(0x1) << GPIO_STERS_P19_Pos) 7536 #define GPIO_STERS_P20_Pos 20 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7537 #define GPIO_STERS_P20 (_U_(0x1) << GPIO_STERS_P20_Pos) 7538 #define GPIO_STERS_P21_Pos 21 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7539 #define GPIO_STERS_P21 (_U_(0x1) << GPIO_STERS_P21_Pos) 7540 #define GPIO_STERS_P22_Pos 22 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7541 #define GPIO_STERS_P22 (_U_(0x1) << GPIO_STERS_P22_Pos) 7542 #define GPIO_STERS_P23_Pos 23 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7543 #define GPIO_STERS_P23 (_U_(0x1) << GPIO_STERS_P23_Pos) 7544 #define GPIO_STERS_P24_Pos 24 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7545 #define GPIO_STERS_P24 (_U_(0x1) << GPIO_STERS_P24_Pos) 7546 #define GPIO_STERS_P25_Pos 25 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7547 #define GPIO_STERS_P25 (_U_(0x1) << GPIO_STERS_P25_Pos) 7548 #define GPIO_STERS_P26_Pos 26 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7549 #define GPIO_STERS_P26 (_U_(0x1) << GPIO_STERS_P26_Pos) 7550 #define GPIO_STERS_P27_Pos 27 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7551 #define GPIO_STERS_P27 (_U_(0x1) << GPIO_STERS_P27_Pos) 7552 #define GPIO_STERS_P28_Pos 28 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7553 #define GPIO_STERS_P28 (_U_(0x1) << GPIO_STERS_P28_Pos) 7554 #define GPIO_STERS_P29_Pos 29 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7555 #define GPIO_STERS_P29 (_U_(0x1) << GPIO_STERS_P29_Pos) 7556 #define GPIO_STERS_P30_Pos 30 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7557 #define GPIO_STERS_P30 (_U_(0x1) << GPIO_STERS_P30_Pos) 7558 #define GPIO_STERS_P31_Pos 31 /**< \brief (GPIO_STERS) Schmitt Trigger Enable */ 7559 #define GPIO_STERS_P31 (_U_(0x1) << GPIO_STERS_P31_Pos) 7560 #define GPIO_STERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_STERS) MASK Register */ 7561 7562 /* -------- GPIO_STERC : (GPIO Offset: 0x168) (R/W 32) port Schmitt Trigger Enable Register - Clear -------- */ 7563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7564 typedef union { 7565 struct { 7566 uint32_t P0:1; /*!< bit: 0 Schmitt Trigger Enable */ 7567 uint32_t P1:1; /*!< bit: 1 Schmitt Trigger Enable */ 7568 uint32_t P2:1; /*!< bit: 2 Schmitt Trigger Enable */ 7569 uint32_t P3:1; /*!< bit: 3 Schmitt Trigger Enable */ 7570 uint32_t P4:1; /*!< bit: 4 Schmitt Trigger Enable */ 7571 uint32_t P5:1; /*!< bit: 5 Schmitt Trigger Enable */ 7572 uint32_t P6:1; /*!< bit: 6 Schmitt Trigger Enable */ 7573 uint32_t P7:1; /*!< bit: 7 Schmitt Trigger Enable */ 7574 uint32_t P8:1; /*!< bit: 8 Schmitt Trigger Enable */ 7575 uint32_t P9:1; /*!< bit: 9 Schmitt Trigger Enable */ 7576 uint32_t P10:1; /*!< bit: 10 Schmitt Trigger Enable */ 7577 uint32_t P11:1; /*!< bit: 11 Schmitt Trigger Enable */ 7578 uint32_t P12:1; /*!< bit: 12 Schmitt Trigger Enable */ 7579 uint32_t P13:1; /*!< bit: 13 Schmitt Trigger Enable */ 7580 uint32_t P14:1; /*!< bit: 14 Schmitt Trigger Enable */ 7581 uint32_t P15:1; /*!< bit: 15 Schmitt Trigger Enable */ 7582 uint32_t P16:1; /*!< bit: 16 Schmitt Trigger Enable */ 7583 uint32_t P17:1; /*!< bit: 17 Schmitt Trigger Enable */ 7584 uint32_t P18:1; /*!< bit: 18 Schmitt Trigger Enable */ 7585 uint32_t P19:1; /*!< bit: 19 Schmitt Trigger Enable */ 7586 uint32_t P20:1; /*!< bit: 20 Schmitt Trigger Enable */ 7587 uint32_t P21:1; /*!< bit: 21 Schmitt Trigger Enable */ 7588 uint32_t P22:1; /*!< bit: 22 Schmitt Trigger Enable */ 7589 uint32_t P23:1; /*!< bit: 23 Schmitt Trigger Enable */ 7590 uint32_t P24:1; /*!< bit: 24 Schmitt Trigger Enable */ 7591 uint32_t P25:1; /*!< bit: 25 Schmitt Trigger Enable */ 7592 uint32_t P26:1; /*!< bit: 26 Schmitt Trigger Enable */ 7593 uint32_t P27:1; /*!< bit: 27 Schmitt Trigger Enable */ 7594 uint32_t P28:1; /*!< bit: 28 Schmitt Trigger Enable */ 7595 uint32_t P29:1; /*!< bit: 29 Schmitt Trigger Enable */ 7596 uint32_t P30:1; /*!< bit: 30 Schmitt Trigger Enable */ 7597 uint32_t P31:1; /*!< bit: 31 Schmitt Trigger Enable */ 7598 } bit; /*!< Structure used for bit access */ 7599 uint32_t reg; /*!< Type used for register access */ 7600 } GPIO_STERC_Type; 7601 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7602 7603 #define GPIO_STERC_OFFSET 0x168 /**< \brief (GPIO_STERC offset) Schmitt Trigger Enable Register - Clear */ 7604 7605 #define GPIO_STERC_P0_Pos 0 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7606 #define GPIO_STERC_P0 (_U_(0x1) << GPIO_STERC_P0_Pos) 7607 #define GPIO_STERC_P1_Pos 1 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7608 #define GPIO_STERC_P1 (_U_(0x1) << GPIO_STERC_P1_Pos) 7609 #define GPIO_STERC_P2_Pos 2 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7610 #define GPIO_STERC_P2 (_U_(0x1) << GPIO_STERC_P2_Pos) 7611 #define GPIO_STERC_P3_Pos 3 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7612 #define GPIO_STERC_P3 (_U_(0x1) << GPIO_STERC_P3_Pos) 7613 #define GPIO_STERC_P4_Pos 4 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7614 #define GPIO_STERC_P4 (_U_(0x1) << GPIO_STERC_P4_Pos) 7615 #define GPIO_STERC_P5_Pos 5 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7616 #define GPIO_STERC_P5 (_U_(0x1) << GPIO_STERC_P5_Pos) 7617 #define GPIO_STERC_P6_Pos 6 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7618 #define GPIO_STERC_P6 (_U_(0x1) << GPIO_STERC_P6_Pos) 7619 #define GPIO_STERC_P7_Pos 7 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7620 #define GPIO_STERC_P7 (_U_(0x1) << GPIO_STERC_P7_Pos) 7621 #define GPIO_STERC_P8_Pos 8 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7622 #define GPIO_STERC_P8 (_U_(0x1) << GPIO_STERC_P8_Pos) 7623 #define GPIO_STERC_P9_Pos 9 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7624 #define GPIO_STERC_P9 (_U_(0x1) << GPIO_STERC_P9_Pos) 7625 #define GPIO_STERC_P10_Pos 10 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7626 #define GPIO_STERC_P10 (_U_(0x1) << GPIO_STERC_P10_Pos) 7627 #define GPIO_STERC_P11_Pos 11 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7628 #define GPIO_STERC_P11 (_U_(0x1) << GPIO_STERC_P11_Pos) 7629 #define GPIO_STERC_P12_Pos 12 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7630 #define GPIO_STERC_P12 (_U_(0x1) << GPIO_STERC_P12_Pos) 7631 #define GPIO_STERC_P13_Pos 13 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7632 #define GPIO_STERC_P13 (_U_(0x1) << GPIO_STERC_P13_Pos) 7633 #define GPIO_STERC_P14_Pos 14 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7634 #define GPIO_STERC_P14 (_U_(0x1) << GPIO_STERC_P14_Pos) 7635 #define GPIO_STERC_P15_Pos 15 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7636 #define GPIO_STERC_P15 (_U_(0x1) << GPIO_STERC_P15_Pos) 7637 #define GPIO_STERC_P16_Pos 16 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7638 #define GPIO_STERC_P16 (_U_(0x1) << GPIO_STERC_P16_Pos) 7639 #define GPIO_STERC_P17_Pos 17 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7640 #define GPIO_STERC_P17 (_U_(0x1) << GPIO_STERC_P17_Pos) 7641 #define GPIO_STERC_P18_Pos 18 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7642 #define GPIO_STERC_P18 (_U_(0x1) << GPIO_STERC_P18_Pos) 7643 #define GPIO_STERC_P19_Pos 19 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7644 #define GPIO_STERC_P19 (_U_(0x1) << GPIO_STERC_P19_Pos) 7645 #define GPIO_STERC_P20_Pos 20 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7646 #define GPIO_STERC_P20 (_U_(0x1) << GPIO_STERC_P20_Pos) 7647 #define GPIO_STERC_P21_Pos 21 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7648 #define GPIO_STERC_P21 (_U_(0x1) << GPIO_STERC_P21_Pos) 7649 #define GPIO_STERC_P22_Pos 22 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7650 #define GPIO_STERC_P22 (_U_(0x1) << GPIO_STERC_P22_Pos) 7651 #define GPIO_STERC_P23_Pos 23 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7652 #define GPIO_STERC_P23 (_U_(0x1) << GPIO_STERC_P23_Pos) 7653 #define GPIO_STERC_P24_Pos 24 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7654 #define GPIO_STERC_P24 (_U_(0x1) << GPIO_STERC_P24_Pos) 7655 #define GPIO_STERC_P25_Pos 25 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7656 #define GPIO_STERC_P25 (_U_(0x1) << GPIO_STERC_P25_Pos) 7657 #define GPIO_STERC_P26_Pos 26 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7658 #define GPIO_STERC_P26 (_U_(0x1) << GPIO_STERC_P26_Pos) 7659 #define GPIO_STERC_P27_Pos 27 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7660 #define GPIO_STERC_P27 (_U_(0x1) << GPIO_STERC_P27_Pos) 7661 #define GPIO_STERC_P28_Pos 28 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7662 #define GPIO_STERC_P28 (_U_(0x1) << GPIO_STERC_P28_Pos) 7663 #define GPIO_STERC_P29_Pos 29 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7664 #define GPIO_STERC_P29 (_U_(0x1) << GPIO_STERC_P29_Pos) 7665 #define GPIO_STERC_P30_Pos 30 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7666 #define GPIO_STERC_P30 (_U_(0x1) << GPIO_STERC_P30_Pos) 7667 #define GPIO_STERC_P31_Pos 31 /**< \brief (GPIO_STERC) Schmitt Trigger Enable */ 7668 #define GPIO_STERC_P31 (_U_(0x1) << GPIO_STERC_P31_Pos) 7669 #define GPIO_STERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_STERC) MASK Register */ 7670 7671 /* -------- GPIO_STERT : (GPIO Offset: 0x16C) (R/W 32) port Schmitt Trigger Enable Register - Toggle -------- */ 7672 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7673 typedef union { 7674 struct { 7675 uint32_t P0:1; /*!< bit: 0 Schmitt Trigger Enable */ 7676 uint32_t P1:1; /*!< bit: 1 Schmitt Trigger Enable */ 7677 uint32_t P2:1; /*!< bit: 2 Schmitt Trigger Enable */ 7678 uint32_t P3:1; /*!< bit: 3 Schmitt Trigger Enable */ 7679 uint32_t P4:1; /*!< bit: 4 Schmitt Trigger Enable */ 7680 uint32_t P5:1; /*!< bit: 5 Schmitt Trigger Enable */ 7681 uint32_t P6:1; /*!< bit: 6 Schmitt Trigger Enable */ 7682 uint32_t P7:1; /*!< bit: 7 Schmitt Trigger Enable */ 7683 uint32_t P8:1; /*!< bit: 8 Schmitt Trigger Enable */ 7684 uint32_t P9:1; /*!< bit: 9 Schmitt Trigger Enable */ 7685 uint32_t P10:1; /*!< bit: 10 Schmitt Trigger Enable */ 7686 uint32_t P11:1; /*!< bit: 11 Schmitt Trigger Enable */ 7687 uint32_t P12:1; /*!< bit: 12 Schmitt Trigger Enable */ 7688 uint32_t P13:1; /*!< bit: 13 Schmitt Trigger Enable */ 7689 uint32_t P14:1; /*!< bit: 14 Schmitt Trigger Enable */ 7690 uint32_t P15:1; /*!< bit: 15 Schmitt Trigger Enable */ 7691 uint32_t P16:1; /*!< bit: 16 Schmitt Trigger Enable */ 7692 uint32_t P17:1; /*!< bit: 17 Schmitt Trigger Enable */ 7693 uint32_t P18:1; /*!< bit: 18 Schmitt Trigger Enable */ 7694 uint32_t P19:1; /*!< bit: 19 Schmitt Trigger Enable */ 7695 uint32_t P20:1; /*!< bit: 20 Schmitt Trigger Enable */ 7696 uint32_t P21:1; /*!< bit: 21 Schmitt Trigger Enable */ 7697 uint32_t P22:1; /*!< bit: 22 Schmitt Trigger Enable */ 7698 uint32_t P23:1; /*!< bit: 23 Schmitt Trigger Enable */ 7699 uint32_t P24:1; /*!< bit: 24 Schmitt Trigger Enable */ 7700 uint32_t P25:1; /*!< bit: 25 Schmitt Trigger Enable */ 7701 uint32_t P26:1; /*!< bit: 26 Schmitt Trigger Enable */ 7702 uint32_t P27:1; /*!< bit: 27 Schmitt Trigger Enable */ 7703 uint32_t P28:1; /*!< bit: 28 Schmitt Trigger Enable */ 7704 uint32_t P29:1; /*!< bit: 29 Schmitt Trigger Enable */ 7705 uint32_t P30:1; /*!< bit: 30 Schmitt Trigger Enable */ 7706 uint32_t P31:1; /*!< bit: 31 Schmitt Trigger Enable */ 7707 } bit; /*!< Structure used for bit access */ 7708 uint32_t reg; /*!< Type used for register access */ 7709 } GPIO_STERT_Type; 7710 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7711 7712 #define GPIO_STERT_OFFSET 0x16C /**< \brief (GPIO_STERT offset) Schmitt Trigger Enable Register - Toggle */ 7713 7714 #define GPIO_STERT_P0_Pos 0 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7715 #define GPIO_STERT_P0 (_U_(0x1) << GPIO_STERT_P0_Pos) 7716 #define GPIO_STERT_P1_Pos 1 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7717 #define GPIO_STERT_P1 (_U_(0x1) << GPIO_STERT_P1_Pos) 7718 #define GPIO_STERT_P2_Pos 2 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7719 #define GPIO_STERT_P2 (_U_(0x1) << GPIO_STERT_P2_Pos) 7720 #define GPIO_STERT_P3_Pos 3 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7721 #define GPIO_STERT_P3 (_U_(0x1) << GPIO_STERT_P3_Pos) 7722 #define GPIO_STERT_P4_Pos 4 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7723 #define GPIO_STERT_P4 (_U_(0x1) << GPIO_STERT_P4_Pos) 7724 #define GPIO_STERT_P5_Pos 5 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7725 #define GPIO_STERT_P5 (_U_(0x1) << GPIO_STERT_P5_Pos) 7726 #define GPIO_STERT_P6_Pos 6 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7727 #define GPIO_STERT_P6 (_U_(0x1) << GPIO_STERT_P6_Pos) 7728 #define GPIO_STERT_P7_Pos 7 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7729 #define GPIO_STERT_P7 (_U_(0x1) << GPIO_STERT_P7_Pos) 7730 #define GPIO_STERT_P8_Pos 8 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7731 #define GPIO_STERT_P8 (_U_(0x1) << GPIO_STERT_P8_Pos) 7732 #define GPIO_STERT_P9_Pos 9 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7733 #define GPIO_STERT_P9 (_U_(0x1) << GPIO_STERT_P9_Pos) 7734 #define GPIO_STERT_P10_Pos 10 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7735 #define GPIO_STERT_P10 (_U_(0x1) << GPIO_STERT_P10_Pos) 7736 #define GPIO_STERT_P11_Pos 11 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7737 #define GPIO_STERT_P11 (_U_(0x1) << GPIO_STERT_P11_Pos) 7738 #define GPIO_STERT_P12_Pos 12 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7739 #define GPIO_STERT_P12 (_U_(0x1) << GPIO_STERT_P12_Pos) 7740 #define GPIO_STERT_P13_Pos 13 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7741 #define GPIO_STERT_P13 (_U_(0x1) << GPIO_STERT_P13_Pos) 7742 #define GPIO_STERT_P14_Pos 14 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7743 #define GPIO_STERT_P14 (_U_(0x1) << GPIO_STERT_P14_Pos) 7744 #define GPIO_STERT_P15_Pos 15 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7745 #define GPIO_STERT_P15 (_U_(0x1) << GPIO_STERT_P15_Pos) 7746 #define GPIO_STERT_P16_Pos 16 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7747 #define GPIO_STERT_P16 (_U_(0x1) << GPIO_STERT_P16_Pos) 7748 #define GPIO_STERT_P17_Pos 17 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7749 #define GPIO_STERT_P17 (_U_(0x1) << GPIO_STERT_P17_Pos) 7750 #define GPIO_STERT_P18_Pos 18 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7751 #define GPIO_STERT_P18 (_U_(0x1) << GPIO_STERT_P18_Pos) 7752 #define GPIO_STERT_P19_Pos 19 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7753 #define GPIO_STERT_P19 (_U_(0x1) << GPIO_STERT_P19_Pos) 7754 #define GPIO_STERT_P20_Pos 20 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7755 #define GPIO_STERT_P20 (_U_(0x1) << GPIO_STERT_P20_Pos) 7756 #define GPIO_STERT_P21_Pos 21 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7757 #define GPIO_STERT_P21 (_U_(0x1) << GPIO_STERT_P21_Pos) 7758 #define GPIO_STERT_P22_Pos 22 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7759 #define GPIO_STERT_P22 (_U_(0x1) << GPIO_STERT_P22_Pos) 7760 #define GPIO_STERT_P23_Pos 23 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7761 #define GPIO_STERT_P23 (_U_(0x1) << GPIO_STERT_P23_Pos) 7762 #define GPIO_STERT_P24_Pos 24 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7763 #define GPIO_STERT_P24 (_U_(0x1) << GPIO_STERT_P24_Pos) 7764 #define GPIO_STERT_P25_Pos 25 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7765 #define GPIO_STERT_P25 (_U_(0x1) << GPIO_STERT_P25_Pos) 7766 #define GPIO_STERT_P26_Pos 26 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7767 #define GPIO_STERT_P26 (_U_(0x1) << GPIO_STERT_P26_Pos) 7768 #define GPIO_STERT_P27_Pos 27 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7769 #define GPIO_STERT_P27 (_U_(0x1) << GPIO_STERT_P27_Pos) 7770 #define GPIO_STERT_P28_Pos 28 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7771 #define GPIO_STERT_P28 (_U_(0x1) << GPIO_STERT_P28_Pos) 7772 #define GPIO_STERT_P29_Pos 29 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7773 #define GPIO_STERT_P29 (_U_(0x1) << GPIO_STERT_P29_Pos) 7774 #define GPIO_STERT_P30_Pos 30 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7775 #define GPIO_STERT_P30 (_U_(0x1) << GPIO_STERT_P30_Pos) 7776 #define GPIO_STERT_P31_Pos 31 /**< \brief (GPIO_STERT) Schmitt Trigger Enable */ 7777 #define GPIO_STERT_P31 (_U_(0x1) << GPIO_STERT_P31_Pos) 7778 #define GPIO_STERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_STERT) MASK Register */ 7779 7780 /* -------- GPIO_EVER : (GPIO Offset: 0x180) (R/W 32) port Event Enable Register -------- */ 7781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7782 typedef union { 7783 struct { 7784 uint32_t P0:1; /*!< bit: 0 Event Enable */ 7785 uint32_t P1:1; /*!< bit: 1 Event Enable */ 7786 uint32_t P2:1; /*!< bit: 2 Event Enable */ 7787 uint32_t P3:1; /*!< bit: 3 Event Enable */ 7788 uint32_t P4:1; /*!< bit: 4 Event Enable */ 7789 uint32_t P5:1; /*!< bit: 5 Event Enable */ 7790 uint32_t P6:1; /*!< bit: 6 Event Enable */ 7791 uint32_t P7:1; /*!< bit: 7 Event Enable */ 7792 uint32_t P8:1; /*!< bit: 8 Event Enable */ 7793 uint32_t P9:1; /*!< bit: 9 Event Enable */ 7794 uint32_t P10:1; /*!< bit: 10 Event Enable */ 7795 uint32_t P11:1; /*!< bit: 11 Event Enable */ 7796 uint32_t P12:1; /*!< bit: 12 Event Enable */ 7797 uint32_t P13:1; /*!< bit: 13 Event Enable */ 7798 uint32_t P14:1; /*!< bit: 14 Event Enable */ 7799 uint32_t P15:1; /*!< bit: 15 Event Enable */ 7800 uint32_t P16:1; /*!< bit: 16 Event Enable */ 7801 uint32_t P17:1; /*!< bit: 17 Event Enable */ 7802 uint32_t P18:1; /*!< bit: 18 Event Enable */ 7803 uint32_t P19:1; /*!< bit: 19 Event Enable */ 7804 uint32_t P20:1; /*!< bit: 20 Event Enable */ 7805 uint32_t P21:1; /*!< bit: 21 Event Enable */ 7806 uint32_t P22:1; /*!< bit: 22 Event Enable */ 7807 uint32_t P23:1; /*!< bit: 23 Event Enable */ 7808 uint32_t P24:1; /*!< bit: 24 Event Enable */ 7809 uint32_t P25:1; /*!< bit: 25 Event Enable */ 7810 uint32_t P26:1; /*!< bit: 26 Event Enable */ 7811 uint32_t P27:1; /*!< bit: 27 Event Enable */ 7812 uint32_t P28:1; /*!< bit: 28 Event Enable */ 7813 uint32_t P29:1; /*!< bit: 29 Event Enable */ 7814 uint32_t P30:1; /*!< bit: 30 Event Enable */ 7815 uint32_t P31:1; /*!< bit: 31 Event Enable */ 7816 } bit; /*!< Structure used for bit access */ 7817 uint32_t reg; /*!< Type used for register access */ 7818 } GPIO_EVER_Type; 7819 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7820 7821 #define GPIO_EVER_OFFSET 0x180 /**< \brief (GPIO_EVER offset) Event Enable Register */ 7822 7823 #define GPIO_EVER_P0_Pos 0 /**< \brief (GPIO_EVER) Event Enable */ 7824 #define GPIO_EVER_P0 (_U_(0x1) << GPIO_EVER_P0_Pos) 7825 #define GPIO_EVER_P1_Pos 1 /**< \brief (GPIO_EVER) Event Enable */ 7826 #define GPIO_EVER_P1 (_U_(0x1) << GPIO_EVER_P1_Pos) 7827 #define GPIO_EVER_P2_Pos 2 /**< \brief (GPIO_EVER) Event Enable */ 7828 #define GPIO_EVER_P2 (_U_(0x1) << GPIO_EVER_P2_Pos) 7829 #define GPIO_EVER_P3_Pos 3 /**< \brief (GPIO_EVER) Event Enable */ 7830 #define GPIO_EVER_P3 (_U_(0x1) << GPIO_EVER_P3_Pos) 7831 #define GPIO_EVER_P4_Pos 4 /**< \brief (GPIO_EVER) Event Enable */ 7832 #define GPIO_EVER_P4 (_U_(0x1) << GPIO_EVER_P4_Pos) 7833 #define GPIO_EVER_P5_Pos 5 /**< \brief (GPIO_EVER) Event Enable */ 7834 #define GPIO_EVER_P5 (_U_(0x1) << GPIO_EVER_P5_Pos) 7835 #define GPIO_EVER_P6_Pos 6 /**< \brief (GPIO_EVER) Event Enable */ 7836 #define GPIO_EVER_P6 (_U_(0x1) << GPIO_EVER_P6_Pos) 7837 #define GPIO_EVER_P7_Pos 7 /**< \brief (GPIO_EVER) Event Enable */ 7838 #define GPIO_EVER_P7 (_U_(0x1) << GPIO_EVER_P7_Pos) 7839 #define GPIO_EVER_P8_Pos 8 /**< \brief (GPIO_EVER) Event Enable */ 7840 #define GPIO_EVER_P8 (_U_(0x1) << GPIO_EVER_P8_Pos) 7841 #define GPIO_EVER_P9_Pos 9 /**< \brief (GPIO_EVER) Event Enable */ 7842 #define GPIO_EVER_P9 (_U_(0x1) << GPIO_EVER_P9_Pos) 7843 #define GPIO_EVER_P10_Pos 10 /**< \brief (GPIO_EVER) Event Enable */ 7844 #define GPIO_EVER_P10 (_U_(0x1) << GPIO_EVER_P10_Pos) 7845 #define GPIO_EVER_P11_Pos 11 /**< \brief (GPIO_EVER) Event Enable */ 7846 #define GPIO_EVER_P11 (_U_(0x1) << GPIO_EVER_P11_Pos) 7847 #define GPIO_EVER_P12_Pos 12 /**< \brief (GPIO_EVER) Event Enable */ 7848 #define GPIO_EVER_P12 (_U_(0x1) << GPIO_EVER_P12_Pos) 7849 #define GPIO_EVER_P13_Pos 13 /**< \brief (GPIO_EVER) Event Enable */ 7850 #define GPIO_EVER_P13 (_U_(0x1) << GPIO_EVER_P13_Pos) 7851 #define GPIO_EVER_P14_Pos 14 /**< \brief (GPIO_EVER) Event Enable */ 7852 #define GPIO_EVER_P14 (_U_(0x1) << GPIO_EVER_P14_Pos) 7853 #define GPIO_EVER_P15_Pos 15 /**< \brief (GPIO_EVER) Event Enable */ 7854 #define GPIO_EVER_P15 (_U_(0x1) << GPIO_EVER_P15_Pos) 7855 #define GPIO_EVER_P16_Pos 16 /**< \brief (GPIO_EVER) Event Enable */ 7856 #define GPIO_EVER_P16 (_U_(0x1) << GPIO_EVER_P16_Pos) 7857 #define GPIO_EVER_P17_Pos 17 /**< \brief (GPIO_EVER) Event Enable */ 7858 #define GPIO_EVER_P17 (_U_(0x1) << GPIO_EVER_P17_Pos) 7859 #define GPIO_EVER_P18_Pos 18 /**< \brief (GPIO_EVER) Event Enable */ 7860 #define GPIO_EVER_P18 (_U_(0x1) << GPIO_EVER_P18_Pos) 7861 #define GPIO_EVER_P19_Pos 19 /**< \brief (GPIO_EVER) Event Enable */ 7862 #define GPIO_EVER_P19 (_U_(0x1) << GPIO_EVER_P19_Pos) 7863 #define GPIO_EVER_P20_Pos 20 /**< \brief (GPIO_EVER) Event Enable */ 7864 #define GPIO_EVER_P20 (_U_(0x1) << GPIO_EVER_P20_Pos) 7865 #define GPIO_EVER_P21_Pos 21 /**< \brief (GPIO_EVER) Event Enable */ 7866 #define GPIO_EVER_P21 (_U_(0x1) << GPIO_EVER_P21_Pos) 7867 #define GPIO_EVER_P22_Pos 22 /**< \brief (GPIO_EVER) Event Enable */ 7868 #define GPIO_EVER_P22 (_U_(0x1) << GPIO_EVER_P22_Pos) 7869 #define GPIO_EVER_P23_Pos 23 /**< \brief (GPIO_EVER) Event Enable */ 7870 #define GPIO_EVER_P23 (_U_(0x1) << GPIO_EVER_P23_Pos) 7871 #define GPIO_EVER_P24_Pos 24 /**< \brief (GPIO_EVER) Event Enable */ 7872 #define GPIO_EVER_P24 (_U_(0x1) << GPIO_EVER_P24_Pos) 7873 #define GPIO_EVER_P25_Pos 25 /**< \brief (GPIO_EVER) Event Enable */ 7874 #define GPIO_EVER_P25 (_U_(0x1) << GPIO_EVER_P25_Pos) 7875 #define GPIO_EVER_P26_Pos 26 /**< \brief (GPIO_EVER) Event Enable */ 7876 #define GPIO_EVER_P26 (_U_(0x1) << GPIO_EVER_P26_Pos) 7877 #define GPIO_EVER_P27_Pos 27 /**< \brief (GPIO_EVER) Event Enable */ 7878 #define GPIO_EVER_P27 (_U_(0x1) << GPIO_EVER_P27_Pos) 7879 #define GPIO_EVER_P28_Pos 28 /**< \brief (GPIO_EVER) Event Enable */ 7880 #define GPIO_EVER_P28 (_U_(0x1) << GPIO_EVER_P28_Pos) 7881 #define GPIO_EVER_P29_Pos 29 /**< \brief (GPIO_EVER) Event Enable */ 7882 #define GPIO_EVER_P29 (_U_(0x1) << GPIO_EVER_P29_Pos) 7883 #define GPIO_EVER_P30_Pos 30 /**< \brief (GPIO_EVER) Event Enable */ 7884 #define GPIO_EVER_P30 (_U_(0x1) << GPIO_EVER_P30_Pos) 7885 #define GPIO_EVER_P31_Pos 31 /**< \brief (GPIO_EVER) Event Enable */ 7886 #define GPIO_EVER_P31 (_U_(0x1) << GPIO_EVER_P31_Pos) 7887 #define GPIO_EVER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_EVER) MASK Register */ 7888 7889 /* -------- GPIO_EVERS : (GPIO Offset: 0x184) ( /W 32) port Event Enable Register - Set -------- */ 7890 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7891 typedef union { 7892 struct { 7893 uint32_t P0:1; /*!< bit: 0 Event Enable */ 7894 uint32_t P1:1; /*!< bit: 1 Event Enable */ 7895 uint32_t P2:1; /*!< bit: 2 Event Enable */ 7896 uint32_t P3:1; /*!< bit: 3 Event Enable */ 7897 uint32_t P4:1; /*!< bit: 4 Event Enable */ 7898 uint32_t P5:1; /*!< bit: 5 Event Enable */ 7899 uint32_t P6:1; /*!< bit: 6 Event Enable */ 7900 uint32_t P7:1; /*!< bit: 7 Event Enable */ 7901 uint32_t P8:1; /*!< bit: 8 Event Enable */ 7902 uint32_t P9:1; /*!< bit: 9 Event Enable */ 7903 uint32_t P10:1; /*!< bit: 10 Event Enable */ 7904 uint32_t P11:1; /*!< bit: 11 Event Enable */ 7905 uint32_t P12:1; /*!< bit: 12 Event Enable */ 7906 uint32_t P13:1; /*!< bit: 13 Event Enable */ 7907 uint32_t P14:1; /*!< bit: 14 Event Enable */ 7908 uint32_t P15:1; /*!< bit: 15 Event Enable */ 7909 uint32_t P16:1; /*!< bit: 16 Event Enable */ 7910 uint32_t P17:1; /*!< bit: 17 Event Enable */ 7911 uint32_t P18:1; /*!< bit: 18 Event Enable */ 7912 uint32_t P19:1; /*!< bit: 19 Event Enable */ 7913 uint32_t P20:1; /*!< bit: 20 Event Enable */ 7914 uint32_t P21:1; /*!< bit: 21 Event Enable */ 7915 uint32_t P22:1; /*!< bit: 22 Event Enable */ 7916 uint32_t P23:1; /*!< bit: 23 Event Enable */ 7917 uint32_t P24:1; /*!< bit: 24 Event Enable */ 7918 uint32_t P25:1; /*!< bit: 25 Event Enable */ 7919 uint32_t P26:1; /*!< bit: 26 Event Enable */ 7920 uint32_t P27:1; /*!< bit: 27 Event Enable */ 7921 uint32_t P28:1; /*!< bit: 28 Event Enable */ 7922 uint32_t P29:1; /*!< bit: 29 Event Enable */ 7923 uint32_t P30:1; /*!< bit: 30 Event Enable */ 7924 uint32_t P31:1; /*!< bit: 31 Event Enable */ 7925 } bit; /*!< Structure used for bit access */ 7926 uint32_t reg; /*!< Type used for register access */ 7927 } GPIO_EVERS_Type; 7928 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7929 7930 #define GPIO_EVERS_OFFSET 0x184 /**< \brief (GPIO_EVERS offset) Event Enable Register - Set */ 7931 7932 #define GPIO_EVERS_P0_Pos 0 /**< \brief (GPIO_EVERS) Event Enable */ 7933 #define GPIO_EVERS_P0 (_U_(0x1) << GPIO_EVERS_P0_Pos) 7934 #define GPIO_EVERS_P1_Pos 1 /**< \brief (GPIO_EVERS) Event Enable */ 7935 #define GPIO_EVERS_P1 (_U_(0x1) << GPIO_EVERS_P1_Pos) 7936 #define GPIO_EVERS_P2_Pos 2 /**< \brief (GPIO_EVERS) Event Enable */ 7937 #define GPIO_EVERS_P2 (_U_(0x1) << GPIO_EVERS_P2_Pos) 7938 #define GPIO_EVERS_P3_Pos 3 /**< \brief (GPIO_EVERS) Event Enable */ 7939 #define GPIO_EVERS_P3 (_U_(0x1) << GPIO_EVERS_P3_Pos) 7940 #define GPIO_EVERS_P4_Pos 4 /**< \brief (GPIO_EVERS) Event Enable */ 7941 #define GPIO_EVERS_P4 (_U_(0x1) << GPIO_EVERS_P4_Pos) 7942 #define GPIO_EVERS_P5_Pos 5 /**< \brief (GPIO_EVERS) Event Enable */ 7943 #define GPIO_EVERS_P5 (_U_(0x1) << GPIO_EVERS_P5_Pos) 7944 #define GPIO_EVERS_P6_Pos 6 /**< \brief (GPIO_EVERS) Event Enable */ 7945 #define GPIO_EVERS_P6 (_U_(0x1) << GPIO_EVERS_P6_Pos) 7946 #define GPIO_EVERS_P7_Pos 7 /**< \brief (GPIO_EVERS) Event Enable */ 7947 #define GPIO_EVERS_P7 (_U_(0x1) << GPIO_EVERS_P7_Pos) 7948 #define GPIO_EVERS_P8_Pos 8 /**< \brief (GPIO_EVERS) Event Enable */ 7949 #define GPIO_EVERS_P8 (_U_(0x1) << GPIO_EVERS_P8_Pos) 7950 #define GPIO_EVERS_P9_Pos 9 /**< \brief (GPIO_EVERS) Event Enable */ 7951 #define GPIO_EVERS_P9 (_U_(0x1) << GPIO_EVERS_P9_Pos) 7952 #define GPIO_EVERS_P10_Pos 10 /**< \brief (GPIO_EVERS) Event Enable */ 7953 #define GPIO_EVERS_P10 (_U_(0x1) << GPIO_EVERS_P10_Pos) 7954 #define GPIO_EVERS_P11_Pos 11 /**< \brief (GPIO_EVERS) Event Enable */ 7955 #define GPIO_EVERS_P11 (_U_(0x1) << GPIO_EVERS_P11_Pos) 7956 #define GPIO_EVERS_P12_Pos 12 /**< \brief (GPIO_EVERS) Event Enable */ 7957 #define GPIO_EVERS_P12 (_U_(0x1) << GPIO_EVERS_P12_Pos) 7958 #define GPIO_EVERS_P13_Pos 13 /**< \brief (GPIO_EVERS) Event Enable */ 7959 #define GPIO_EVERS_P13 (_U_(0x1) << GPIO_EVERS_P13_Pos) 7960 #define GPIO_EVERS_P14_Pos 14 /**< \brief (GPIO_EVERS) Event Enable */ 7961 #define GPIO_EVERS_P14 (_U_(0x1) << GPIO_EVERS_P14_Pos) 7962 #define GPIO_EVERS_P15_Pos 15 /**< \brief (GPIO_EVERS) Event Enable */ 7963 #define GPIO_EVERS_P15 (_U_(0x1) << GPIO_EVERS_P15_Pos) 7964 #define GPIO_EVERS_P16_Pos 16 /**< \brief (GPIO_EVERS) Event Enable */ 7965 #define GPIO_EVERS_P16 (_U_(0x1) << GPIO_EVERS_P16_Pos) 7966 #define GPIO_EVERS_P17_Pos 17 /**< \brief (GPIO_EVERS) Event Enable */ 7967 #define GPIO_EVERS_P17 (_U_(0x1) << GPIO_EVERS_P17_Pos) 7968 #define GPIO_EVERS_P18_Pos 18 /**< \brief (GPIO_EVERS) Event Enable */ 7969 #define GPIO_EVERS_P18 (_U_(0x1) << GPIO_EVERS_P18_Pos) 7970 #define GPIO_EVERS_P19_Pos 19 /**< \brief (GPIO_EVERS) Event Enable */ 7971 #define GPIO_EVERS_P19 (_U_(0x1) << GPIO_EVERS_P19_Pos) 7972 #define GPIO_EVERS_P20_Pos 20 /**< \brief (GPIO_EVERS) Event Enable */ 7973 #define GPIO_EVERS_P20 (_U_(0x1) << GPIO_EVERS_P20_Pos) 7974 #define GPIO_EVERS_P21_Pos 21 /**< \brief (GPIO_EVERS) Event Enable */ 7975 #define GPIO_EVERS_P21 (_U_(0x1) << GPIO_EVERS_P21_Pos) 7976 #define GPIO_EVERS_P22_Pos 22 /**< \brief (GPIO_EVERS) Event Enable */ 7977 #define GPIO_EVERS_P22 (_U_(0x1) << GPIO_EVERS_P22_Pos) 7978 #define GPIO_EVERS_P23_Pos 23 /**< \brief (GPIO_EVERS) Event Enable */ 7979 #define GPIO_EVERS_P23 (_U_(0x1) << GPIO_EVERS_P23_Pos) 7980 #define GPIO_EVERS_P24_Pos 24 /**< \brief (GPIO_EVERS) Event Enable */ 7981 #define GPIO_EVERS_P24 (_U_(0x1) << GPIO_EVERS_P24_Pos) 7982 #define GPIO_EVERS_P25_Pos 25 /**< \brief (GPIO_EVERS) Event Enable */ 7983 #define GPIO_EVERS_P25 (_U_(0x1) << GPIO_EVERS_P25_Pos) 7984 #define GPIO_EVERS_P26_Pos 26 /**< \brief (GPIO_EVERS) Event Enable */ 7985 #define GPIO_EVERS_P26 (_U_(0x1) << GPIO_EVERS_P26_Pos) 7986 #define GPIO_EVERS_P27_Pos 27 /**< \brief (GPIO_EVERS) Event Enable */ 7987 #define GPIO_EVERS_P27 (_U_(0x1) << GPIO_EVERS_P27_Pos) 7988 #define GPIO_EVERS_P28_Pos 28 /**< \brief (GPIO_EVERS) Event Enable */ 7989 #define GPIO_EVERS_P28 (_U_(0x1) << GPIO_EVERS_P28_Pos) 7990 #define GPIO_EVERS_P29_Pos 29 /**< \brief (GPIO_EVERS) Event Enable */ 7991 #define GPIO_EVERS_P29 (_U_(0x1) << GPIO_EVERS_P29_Pos) 7992 #define GPIO_EVERS_P30_Pos 30 /**< \brief (GPIO_EVERS) Event Enable */ 7993 #define GPIO_EVERS_P30 (_U_(0x1) << GPIO_EVERS_P30_Pos) 7994 #define GPIO_EVERS_P31_Pos 31 /**< \brief (GPIO_EVERS) Event Enable */ 7995 #define GPIO_EVERS_P31 (_U_(0x1) << GPIO_EVERS_P31_Pos) 7996 #define GPIO_EVERS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_EVERS) MASK Register */ 7997 7998 /* -------- GPIO_EVERC : (GPIO Offset: 0x188) ( /W 32) port Event Enable Register - Clear -------- */ 7999 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8000 typedef union { 8001 struct { 8002 uint32_t P0:1; /*!< bit: 0 Event Enable */ 8003 uint32_t P1:1; /*!< bit: 1 Event Enable */ 8004 uint32_t P2:1; /*!< bit: 2 Event Enable */ 8005 uint32_t P3:1; /*!< bit: 3 Event Enable */ 8006 uint32_t P4:1; /*!< bit: 4 Event Enable */ 8007 uint32_t P5:1; /*!< bit: 5 Event Enable */ 8008 uint32_t P6:1; /*!< bit: 6 Event Enable */ 8009 uint32_t P7:1; /*!< bit: 7 Event Enable */ 8010 uint32_t P8:1; /*!< bit: 8 Event Enable */ 8011 uint32_t P9:1; /*!< bit: 9 Event Enable */ 8012 uint32_t P10:1; /*!< bit: 10 Event Enable */ 8013 uint32_t P11:1; /*!< bit: 11 Event Enable */ 8014 uint32_t P12:1; /*!< bit: 12 Event Enable */ 8015 uint32_t P13:1; /*!< bit: 13 Event Enable */ 8016 uint32_t P14:1; /*!< bit: 14 Event Enable */ 8017 uint32_t P15:1; /*!< bit: 15 Event Enable */ 8018 uint32_t P16:1; /*!< bit: 16 Event Enable */ 8019 uint32_t P17:1; /*!< bit: 17 Event Enable */ 8020 uint32_t P18:1; /*!< bit: 18 Event Enable */ 8021 uint32_t P19:1; /*!< bit: 19 Event Enable */ 8022 uint32_t P20:1; /*!< bit: 20 Event Enable */ 8023 uint32_t P21:1; /*!< bit: 21 Event Enable */ 8024 uint32_t P22:1; /*!< bit: 22 Event Enable */ 8025 uint32_t P23:1; /*!< bit: 23 Event Enable */ 8026 uint32_t P24:1; /*!< bit: 24 Event Enable */ 8027 uint32_t P25:1; /*!< bit: 25 Event Enable */ 8028 uint32_t P26:1; /*!< bit: 26 Event Enable */ 8029 uint32_t P27:1; /*!< bit: 27 Event Enable */ 8030 uint32_t P28:1; /*!< bit: 28 Event Enable */ 8031 uint32_t P29:1; /*!< bit: 29 Event Enable */ 8032 uint32_t P30:1; /*!< bit: 30 Event Enable */ 8033 uint32_t P31:1; /*!< bit: 31 Event Enable */ 8034 } bit; /*!< Structure used for bit access */ 8035 uint32_t reg; /*!< Type used for register access */ 8036 } GPIO_EVERC_Type; 8037 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8038 8039 #define GPIO_EVERC_OFFSET 0x188 /**< \brief (GPIO_EVERC offset) Event Enable Register - Clear */ 8040 8041 #define GPIO_EVERC_P0_Pos 0 /**< \brief (GPIO_EVERC) Event Enable */ 8042 #define GPIO_EVERC_P0 (_U_(0x1) << GPIO_EVERC_P0_Pos) 8043 #define GPIO_EVERC_P1_Pos 1 /**< \brief (GPIO_EVERC) Event Enable */ 8044 #define GPIO_EVERC_P1 (_U_(0x1) << GPIO_EVERC_P1_Pos) 8045 #define GPIO_EVERC_P2_Pos 2 /**< \brief (GPIO_EVERC) Event Enable */ 8046 #define GPIO_EVERC_P2 (_U_(0x1) << GPIO_EVERC_P2_Pos) 8047 #define GPIO_EVERC_P3_Pos 3 /**< \brief (GPIO_EVERC) Event Enable */ 8048 #define GPIO_EVERC_P3 (_U_(0x1) << GPIO_EVERC_P3_Pos) 8049 #define GPIO_EVERC_P4_Pos 4 /**< \brief (GPIO_EVERC) Event Enable */ 8050 #define GPIO_EVERC_P4 (_U_(0x1) << GPIO_EVERC_P4_Pos) 8051 #define GPIO_EVERC_P5_Pos 5 /**< \brief (GPIO_EVERC) Event Enable */ 8052 #define GPIO_EVERC_P5 (_U_(0x1) << GPIO_EVERC_P5_Pos) 8053 #define GPIO_EVERC_P6_Pos 6 /**< \brief (GPIO_EVERC) Event Enable */ 8054 #define GPIO_EVERC_P6 (_U_(0x1) << GPIO_EVERC_P6_Pos) 8055 #define GPIO_EVERC_P7_Pos 7 /**< \brief (GPIO_EVERC) Event Enable */ 8056 #define GPIO_EVERC_P7 (_U_(0x1) << GPIO_EVERC_P7_Pos) 8057 #define GPIO_EVERC_P8_Pos 8 /**< \brief (GPIO_EVERC) Event Enable */ 8058 #define GPIO_EVERC_P8 (_U_(0x1) << GPIO_EVERC_P8_Pos) 8059 #define GPIO_EVERC_P9_Pos 9 /**< \brief (GPIO_EVERC) Event Enable */ 8060 #define GPIO_EVERC_P9 (_U_(0x1) << GPIO_EVERC_P9_Pos) 8061 #define GPIO_EVERC_P10_Pos 10 /**< \brief (GPIO_EVERC) Event Enable */ 8062 #define GPIO_EVERC_P10 (_U_(0x1) << GPIO_EVERC_P10_Pos) 8063 #define GPIO_EVERC_P11_Pos 11 /**< \brief (GPIO_EVERC) Event Enable */ 8064 #define GPIO_EVERC_P11 (_U_(0x1) << GPIO_EVERC_P11_Pos) 8065 #define GPIO_EVERC_P12_Pos 12 /**< \brief (GPIO_EVERC) Event Enable */ 8066 #define GPIO_EVERC_P12 (_U_(0x1) << GPIO_EVERC_P12_Pos) 8067 #define GPIO_EVERC_P13_Pos 13 /**< \brief (GPIO_EVERC) Event Enable */ 8068 #define GPIO_EVERC_P13 (_U_(0x1) << GPIO_EVERC_P13_Pos) 8069 #define GPIO_EVERC_P14_Pos 14 /**< \brief (GPIO_EVERC) Event Enable */ 8070 #define GPIO_EVERC_P14 (_U_(0x1) << GPIO_EVERC_P14_Pos) 8071 #define GPIO_EVERC_P15_Pos 15 /**< \brief (GPIO_EVERC) Event Enable */ 8072 #define GPIO_EVERC_P15 (_U_(0x1) << GPIO_EVERC_P15_Pos) 8073 #define GPIO_EVERC_P16_Pos 16 /**< \brief (GPIO_EVERC) Event Enable */ 8074 #define GPIO_EVERC_P16 (_U_(0x1) << GPIO_EVERC_P16_Pos) 8075 #define GPIO_EVERC_P17_Pos 17 /**< \brief (GPIO_EVERC) Event Enable */ 8076 #define GPIO_EVERC_P17 (_U_(0x1) << GPIO_EVERC_P17_Pos) 8077 #define GPIO_EVERC_P18_Pos 18 /**< \brief (GPIO_EVERC) Event Enable */ 8078 #define GPIO_EVERC_P18 (_U_(0x1) << GPIO_EVERC_P18_Pos) 8079 #define GPIO_EVERC_P19_Pos 19 /**< \brief (GPIO_EVERC) Event Enable */ 8080 #define GPIO_EVERC_P19 (_U_(0x1) << GPIO_EVERC_P19_Pos) 8081 #define GPIO_EVERC_P20_Pos 20 /**< \brief (GPIO_EVERC) Event Enable */ 8082 #define GPIO_EVERC_P20 (_U_(0x1) << GPIO_EVERC_P20_Pos) 8083 #define GPIO_EVERC_P21_Pos 21 /**< \brief (GPIO_EVERC) Event Enable */ 8084 #define GPIO_EVERC_P21 (_U_(0x1) << GPIO_EVERC_P21_Pos) 8085 #define GPIO_EVERC_P22_Pos 22 /**< \brief (GPIO_EVERC) Event Enable */ 8086 #define GPIO_EVERC_P22 (_U_(0x1) << GPIO_EVERC_P22_Pos) 8087 #define GPIO_EVERC_P23_Pos 23 /**< \brief (GPIO_EVERC) Event Enable */ 8088 #define GPIO_EVERC_P23 (_U_(0x1) << GPIO_EVERC_P23_Pos) 8089 #define GPIO_EVERC_P24_Pos 24 /**< \brief (GPIO_EVERC) Event Enable */ 8090 #define GPIO_EVERC_P24 (_U_(0x1) << GPIO_EVERC_P24_Pos) 8091 #define GPIO_EVERC_P25_Pos 25 /**< \brief (GPIO_EVERC) Event Enable */ 8092 #define GPIO_EVERC_P25 (_U_(0x1) << GPIO_EVERC_P25_Pos) 8093 #define GPIO_EVERC_P26_Pos 26 /**< \brief (GPIO_EVERC) Event Enable */ 8094 #define GPIO_EVERC_P26 (_U_(0x1) << GPIO_EVERC_P26_Pos) 8095 #define GPIO_EVERC_P27_Pos 27 /**< \brief (GPIO_EVERC) Event Enable */ 8096 #define GPIO_EVERC_P27 (_U_(0x1) << GPIO_EVERC_P27_Pos) 8097 #define GPIO_EVERC_P28_Pos 28 /**< \brief (GPIO_EVERC) Event Enable */ 8098 #define GPIO_EVERC_P28 (_U_(0x1) << GPIO_EVERC_P28_Pos) 8099 #define GPIO_EVERC_P29_Pos 29 /**< \brief (GPIO_EVERC) Event Enable */ 8100 #define GPIO_EVERC_P29 (_U_(0x1) << GPIO_EVERC_P29_Pos) 8101 #define GPIO_EVERC_P30_Pos 30 /**< \brief (GPIO_EVERC) Event Enable */ 8102 #define GPIO_EVERC_P30 (_U_(0x1) << GPIO_EVERC_P30_Pos) 8103 #define GPIO_EVERC_P31_Pos 31 /**< \brief (GPIO_EVERC) Event Enable */ 8104 #define GPIO_EVERC_P31 (_U_(0x1) << GPIO_EVERC_P31_Pos) 8105 #define GPIO_EVERC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_EVERC) MASK Register */ 8106 8107 /* -------- GPIO_EVERT : (GPIO Offset: 0x18C) ( /W 32) port Event Enable Register - Toggle -------- */ 8108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8109 typedef union { 8110 struct { 8111 uint32_t P0:1; /*!< bit: 0 Event Enable */ 8112 uint32_t P1:1; /*!< bit: 1 Event Enable */ 8113 uint32_t P2:1; /*!< bit: 2 Event Enable */ 8114 uint32_t P3:1; /*!< bit: 3 Event Enable */ 8115 uint32_t P4:1; /*!< bit: 4 Event Enable */ 8116 uint32_t P5:1; /*!< bit: 5 Event Enable */ 8117 uint32_t P6:1; /*!< bit: 6 Event Enable */ 8118 uint32_t P7:1; /*!< bit: 7 Event Enable */ 8119 uint32_t P8:1; /*!< bit: 8 Event Enable */ 8120 uint32_t P9:1; /*!< bit: 9 Event Enable */ 8121 uint32_t P10:1; /*!< bit: 10 Event Enable */ 8122 uint32_t P11:1; /*!< bit: 11 Event Enable */ 8123 uint32_t P12:1; /*!< bit: 12 Event Enable */ 8124 uint32_t P13:1; /*!< bit: 13 Event Enable */ 8125 uint32_t P14:1; /*!< bit: 14 Event Enable */ 8126 uint32_t P15:1; /*!< bit: 15 Event Enable */ 8127 uint32_t P16:1; /*!< bit: 16 Event Enable */ 8128 uint32_t P17:1; /*!< bit: 17 Event Enable */ 8129 uint32_t P18:1; /*!< bit: 18 Event Enable */ 8130 uint32_t P19:1; /*!< bit: 19 Event Enable */ 8131 uint32_t P20:1; /*!< bit: 20 Event Enable */ 8132 uint32_t P21:1; /*!< bit: 21 Event Enable */ 8133 uint32_t P22:1; /*!< bit: 22 Event Enable */ 8134 uint32_t P23:1; /*!< bit: 23 Event Enable */ 8135 uint32_t P24:1; /*!< bit: 24 Event Enable */ 8136 uint32_t P25:1; /*!< bit: 25 Event Enable */ 8137 uint32_t P26:1; /*!< bit: 26 Event Enable */ 8138 uint32_t P27:1; /*!< bit: 27 Event Enable */ 8139 uint32_t P28:1; /*!< bit: 28 Event Enable */ 8140 uint32_t P29:1; /*!< bit: 29 Event Enable */ 8141 uint32_t P30:1; /*!< bit: 30 Event Enable */ 8142 uint32_t P31:1; /*!< bit: 31 Event Enable */ 8143 } bit; /*!< Structure used for bit access */ 8144 uint32_t reg; /*!< Type used for register access */ 8145 } GPIO_EVERT_Type; 8146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8147 8148 #define GPIO_EVERT_OFFSET 0x18C /**< \brief (GPIO_EVERT offset) Event Enable Register - Toggle */ 8149 8150 #define GPIO_EVERT_P0_Pos 0 /**< \brief (GPIO_EVERT) Event Enable */ 8151 #define GPIO_EVERT_P0 (_U_(0x1) << GPIO_EVERT_P0_Pos) 8152 #define GPIO_EVERT_P1_Pos 1 /**< \brief (GPIO_EVERT) Event Enable */ 8153 #define GPIO_EVERT_P1 (_U_(0x1) << GPIO_EVERT_P1_Pos) 8154 #define GPIO_EVERT_P2_Pos 2 /**< \brief (GPIO_EVERT) Event Enable */ 8155 #define GPIO_EVERT_P2 (_U_(0x1) << GPIO_EVERT_P2_Pos) 8156 #define GPIO_EVERT_P3_Pos 3 /**< \brief (GPIO_EVERT) Event Enable */ 8157 #define GPIO_EVERT_P3 (_U_(0x1) << GPIO_EVERT_P3_Pos) 8158 #define GPIO_EVERT_P4_Pos 4 /**< \brief (GPIO_EVERT) Event Enable */ 8159 #define GPIO_EVERT_P4 (_U_(0x1) << GPIO_EVERT_P4_Pos) 8160 #define GPIO_EVERT_P5_Pos 5 /**< \brief (GPIO_EVERT) Event Enable */ 8161 #define GPIO_EVERT_P5 (_U_(0x1) << GPIO_EVERT_P5_Pos) 8162 #define GPIO_EVERT_P6_Pos 6 /**< \brief (GPIO_EVERT) Event Enable */ 8163 #define GPIO_EVERT_P6 (_U_(0x1) << GPIO_EVERT_P6_Pos) 8164 #define GPIO_EVERT_P7_Pos 7 /**< \brief (GPIO_EVERT) Event Enable */ 8165 #define GPIO_EVERT_P7 (_U_(0x1) << GPIO_EVERT_P7_Pos) 8166 #define GPIO_EVERT_P8_Pos 8 /**< \brief (GPIO_EVERT) Event Enable */ 8167 #define GPIO_EVERT_P8 (_U_(0x1) << GPIO_EVERT_P8_Pos) 8168 #define GPIO_EVERT_P9_Pos 9 /**< \brief (GPIO_EVERT) Event Enable */ 8169 #define GPIO_EVERT_P9 (_U_(0x1) << GPIO_EVERT_P9_Pos) 8170 #define GPIO_EVERT_P10_Pos 10 /**< \brief (GPIO_EVERT) Event Enable */ 8171 #define GPIO_EVERT_P10 (_U_(0x1) << GPIO_EVERT_P10_Pos) 8172 #define GPIO_EVERT_P11_Pos 11 /**< \brief (GPIO_EVERT) Event Enable */ 8173 #define GPIO_EVERT_P11 (_U_(0x1) << GPIO_EVERT_P11_Pos) 8174 #define GPIO_EVERT_P12_Pos 12 /**< \brief (GPIO_EVERT) Event Enable */ 8175 #define GPIO_EVERT_P12 (_U_(0x1) << GPIO_EVERT_P12_Pos) 8176 #define GPIO_EVERT_P13_Pos 13 /**< \brief (GPIO_EVERT) Event Enable */ 8177 #define GPIO_EVERT_P13 (_U_(0x1) << GPIO_EVERT_P13_Pos) 8178 #define GPIO_EVERT_P14_Pos 14 /**< \brief (GPIO_EVERT) Event Enable */ 8179 #define GPIO_EVERT_P14 (_U_(0x1) << GPIO_EVERT_P14_Pos) 8180 #define GPIO_EVERT_P15_Pos 15 /**< \brief (GPIO_EVERT) Event Enable */ 8181 #define GPIO_EVERT_P15 (_U_(0x1) << GPIO_EVERT_P15_Pos) 8182 #define GPIO_EVERT_P16_Pos 16 /**< \brief (GPIO_EVERT) Event Enable */ 8183 #define GPIO_EVERT_P16 (_U_(0x1) << GPIO_EVERT_P16_Pos) 8184 #define GPIO_EVERT_P17_Pos 17 /**< \brief (GPIO_EVERT) Event Enable */ 8185 #define GPIO_EVERT_P17 (_U_(0x1) << GPIO_EVERT_P17_Pos) 8186 #define GPIO_EVERT_P18_Pos 18 /**< \brief (GPIO_EVERT) Event Enable */ 8187 #define GPIO_EVERT_P18 (_U_(0x1) << GPIO_EVERT_P18_Pos) 8188 #define GPIO_EVERT_P19_Pos 19 /**< \brief (GPIO_EVERT) Event Enable */ 8189 #define GPIO_EVERT_P19 (_U_(0x1) << GPIO_EVERT_P19_Pos) 8190 #define GPIO_EVERT_P20_Pos 20 /**< \brief (GPIO_EVERT) Event Enable */ 8191 #define GPIO_EVERT_P20 (_U_(0x1) << GPIO_EVERT_P20_Pos) 8192 #define GPIO_EVERT_P21_Pos 21 /**< \brief (GPIO_EVERT) Event Enable */ 8193 #define GPIO_EVERT_P21 (_U_(0x1) << GPIO_EVERT_P21_Pos) 8194 #define GPIO_EVERT_P22_Pos 22 /**< \brief (GPIO_EVERT) Event Enable */ 8195 #define GPIO_EVERT_P22 (_U_(0x1) << GPIO_EVERT_P22_Pos) 8196 #define GPIO_EVERT_P23_Pos 23 /**< \brief (GPIO_EVERT) Event Enable */ 8197 #define GPIO_EVERT_P23 (_U_(0x1) << GPIO_EVERT_P23_Pos) 8198 #define GPIO_EVERT_P24_Pos 24 /**< \brief (GPIO_EVERT) Event Enable */ 8199 #define GPIO_EVERT_P24 (_U_(0x1) << GPIO_EVERT_P24_Pos) 8200 #define GPIO_EVERT_P25_Pos 25 /**< \brief (GPIO_EVERT) Event Enable */ 8201 #define GPIO_EVERT_P25 (_U_(0x1) << GPIO_EVERT_P25_Pos) 8202 #define GPIO_EVERT_P26_Pos 26 /**< \brief (GPIO_EVERT) Event Enable */ 8203 #define GPIO_EVERT_P26 (_U_(0x1) << GPIO_EVERT_P26_Pos) 8204 #define GPIO_EVERT_P27_Pos 27 /**< \brief (GPIO_EVERT) Event Enable */ 8205 #define GPIO_EVERT_P27 (_U_(0x1) << GPIO_EVERT_P27_Pos) 8206 #define GPIO_EVERT_P28_Pos 28 /**< \brief (GPIO_EVERT) Event Enable */ 8207 #define GPIO_EVERT_P28 (_U_(0x1) << GPIO_EVERT_P28_Pos) 8208 #define GPIO_EVERT_P29_Pos 29 /**< \brief (GPIO_EVERT) Event Enable */ 8209 #define GPIO_EVERT_P29 (_U_(0x1) << GPIO_EVERT_P29_Pos) 8210 #define GPIO_EVERT_P30_Pos 30 /**< \brief (GPIO_EVERT) Event Enable */ 8211 #define GPIO_EVERT_P30 (_U_(0x1) << GPIO_EVERT_P30_Pos) 8212 #define GPIO_EVERT_P31_Pos 31 /**< \brief (GPIO_EVERT) Event Enable */ 8213 #define GPIO_EVERT_P31 (_U_(0x1) << GPIO_EVERT_P31_Pos) 8214 #define GPIO_EVERT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_EVERT) MASK Register */ 8215 8216 /* -------- GPIO_LOCK : (GPIO Offset: 0x1A0) (R/W 32) port Lock Register -------- */ 8217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8218 typedef union { 8219 struct { 8220 uint32_t P0:1; /*!< bit: 0 Lock State */ 8221 uint32_t P1:1; /*!< bit: 1 Lock State */ 8222 uint32_t P2:1; /*!< bit: 2 Lock State */ 8223 uint32_t P3:1; /*!< bit: 3 Lock State */ 8224 uint32_t P4:1; /*!< bit: 4 Lock State */ 8225 uint32_t P5:1; /*!< bit: 5 Lock State */ 8226 uint32_t P6:1; /*!< bit: 6 Lock State */ 8227 uint32_t P7:1; /*!< bit: 7 Lock State */ 8228 uint32_t P8:1; /*!< bit: 8 Lock State */ 8229 uint32_t P9:1; /*!< bit: 9 Lock State */ 8230 uint32_t P10:1; /*!< bit: 10 Lock State */ 8231 uint32_t P11:1; /*!< bit: 11 Lock State */ 8232 uint32_t P12:1; /*!< bit: 12 Lock State */ 8233 uint32_t P13:1; /*!< bit: 13 Lock State */ 8234 uint32_t P14:1; /*!< bit: 14 Lock State */ 8235 uint32_t P15:1; /*!< bit: 15 Lock State */ 8236 uint32_t P16:1; /*!< bit: 16 Lock State */ 8237 uint32_t P17:1; /*!< bit: 17 Lock State */ 8238 uint32_t P18:1; /*!< bit: 18 Lock State */ 8239 uint32_t P19:1; /*!< bit: 19 Lock State */ 8240 uint32_t P20:1; /*!< bit: 20 Lock State */ 8241 uint32_t P21:1; /*!< bit: 21 Lock State */ 8242 uint32_t P22:1; /*!< bit: 22 Lock State */ 8243 uint32_t P23:1; /*!< bit: 23 Lock State */ 8244 uint32_t P24:1; /*!< bit: 24 Lock State */ 8245 uint32_t P25:1; /*!< bit: 25 Lock State */ 8246 uint32_t P26:1; /*!< bit: 26 Lock State */ 8247 uint32_t P27:1; /*!< bit: 27 Lock State */ 8248 uint32_t P28:1; /*!< bit: 28 Lock State */ 8249 uint32_t P29:1; /*!< bit: 29 Lock State */ 8250 uint32_t P30:1; /*!< bit: 30 Lock State */ 8251 uint32_t P31:1; /*!< bit: 31 Lock State */ 8252 } bit; /*!< Structure used for bit access */ 8253 uint32_t reg; /*!< Type used for register access */ 8254 } GPIO_LOCK_Type; 8255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8256 8257 #define GPIO_LOCK_OFFSET 0x1A0 /**< \brief (GPIO_LOCK offset) Lock Register */ 8258 8259 #define GPIO_LOCK_P0_Pos 0 /**< \brief (GPIO_LOCK) Lock State */ 8260 #define GPIO_LOCK_P0 (_U_(0x1) << GPIO_LOCK_P0_Pos) 8261 #define GPIO_LOCK_P1_Pos 1 /**< \brief (GPIO_LOCK) Lock State */ 8262 #define GPIO_LOCK_P1 (_U_(0x1) << GPIO_LOCK_P1_Pos) 8263 #define GPIO_LOCK_P2_Pos 2 /**< \brief (GPIO_LOCK) Lock State */ 8264 #define GPIO_LOCK_P2 (_U_(0x1) << GPIO_LOCK_P2_Pos) 8265 #define GPIO_LOCK_P3_Pos 3 /**< \brief (GPIO_LOCK) Lock State */ 8266 #define GPIO_LOCK_P3 (_U_(0x1) << GPIO_LOCK_P3_Pos) 8267 #define GPIO_LOCK_P4_Pos 4 /**< \brief (GPIO_LOCK) Lock State */ 8268 #define GPIO_LOCK_P4 (_U_(0x1) << GPIO_LOCK_P4_Pos) 8269 #define GPIO_LOCK_P5_Pos 5 /**< \brief (GPIO_LOCK) Lock State */ 8270 #define GPIO_LOCK_P5 (_U_(0x1) << GPIO_LOCK_P5_Pos) 8271 #define GPIO_LOCK_P6_Pos 6 /**< \brief (GPIO_LOCK) Lock State */ 8272 #define GPIO_LOCK_P6 (_U_(0x1) << GPIO_LOCK_P6_Pos) 8273 #define GPIO_LOCK_P7_Pos 7 /**< \brief (GPIO_LOCK) Lock State */ 8274 #define GPIO_LOCK_P7 (_U_(0x1) << GPIO_LOCK_P7_Pos) 8275 #define GPIO_LOCK_P8_Pos 8 /**< \brief (GPIO_LOCK) Lock State */ 8276 #define GPIO_LOCK_P8 (_U_(0x1) << GPIO_LOCK_P8_Pos) 8277 #define GPIO_LOCK_P9_Pos 9 /**< \brief (GPIO_LOCK) Lock State */ 8278 #define GPIO_LOCK_P9 (_U_(0x1) << GPIO_LOCK_P9_Pos) 8279 #define GPIO_LOCK_P10_Pos 10 /**< \brief (GPIO_LOCK) Lock State */ 8280 #define GPIO_LOCK_P10 (_U_(0x1) << GPIO_LOCK_P10_Pos) 8281 #define GPIO_LOCK_P11_Pos 11 /**< \brief (GPIO_LOCK) Lock State */ 8282 #define GPIO_LOCK_P11 (_U_(0x1) << GPIO_LOCK_P11_Pos) 8283 #define GPIO_LOCK_P12_Pos 12 /**< \brief (GPIO_LOCK) Lock State */ 8284 #define GPIO_LOCK_P12 (_U_(0x1) << GPIO_LOCK_P12_Pos) 8285 #define GPIO_LOCK_P13_Pos 13 /**< \brief (GPIO_LOCK) Lock State */ 8286 #define GPIO_LOCK_P13 (_U_(0x1) << GPIO_LOCK_P13_Pos) 8287 #define GPIO_LOCK_P14_Pos 14 /**< \brief (GPIO_LOCK) Lock State */ 8288 #define GPIO_LOCK_P14 (_U_(0x1) << GPIO_LOCK_P14_Pos) 8289 #define GPIO_LOCK_P15_Pos 15 /**< \brief (GPIO_LOCK) Lock State */ 8290 #define GPIO_LOCK_P15 (_U_(0x1) << GPIO_LOCK_P15_Pos) 8291 #define GPIO_LOCK_P16_Pos 16 /**< \brief (GPIO_LOCK) Lock State */ 8292 #define GPIO_LOCK_P16 (_U_(0x1) << GPIO_LOCK_P16_Pos) 8293 #define GPIO_LOCK_P17_Pos 17 /**< \brief (GPIO_LOCK) Lock State */ 8294 #define GPIO_LOCK_P17 (_U_(0x1) << GPIO_LOCK_P17_Pos) 8295 #define GPIO_LOCK_P18_Pos 18 /**< \brief (GPIO_LOCK) Lock State */ 8296 #define GPIO_LOCK_P18 (_U_(0x1) << GPIO_LOCK_P18_Pos) 8297 #define GPIO_LOCK_P19_Pos 19 /**< \brief (GPIO_LOCK) Lock State */ 8298 #define GPIO_LOCK_P19 (_U_(0x1) << GPIO_LOCK_P19_Pos) 8299 #define GPIO_LOCK_P20_Pos 20 /**< \brief (GPIO_LOCK) Lock State */ 8300 #define GPIO_LOCK_P20 (_U_(0x1) << GPIO_LOCK_P20_Pos) 8301 #define GPIO_LOCK_P21_Pos 21 /**< \brief (GPIO_LOCK) Lock State */ 8302 #define GPIO_LOCK_P21 (_U_(0x1) << GPIO_LOCK_P21_Pos) 8303 #define GPIO_LOCK_P22_Pos 22 /**< \brief (GPIO_LOCK) Lock State */ 8304 #define GPIO_LOCK_P22 (_U_(0x1) << GPIO_LOCK_P22_Pos) 8305 #define GPIO_LOCK_P23_Pos 23 /**< \brief (GPIO_LOCK) Lock State */ 8306 #define GPIO_LOCK_P23 (_U_(0x1) << GPIO_LOCK_P23_Pos) 8307 #define GPIO_LOCK_P24_Pos 24 /**< \brief (GPIO_LOCK) Lock State */ 8308 #define GPIO_LOCK_P24 (_U_(0x1) << GPIO_LOCK_P24_Pos) 8309 #define GPIO_LOCK_P25_Pos 25 /**< \brief (GPIO_LOCK) Lock State */ 8310 #define GPIO_LOCK_P25 (_U_(0x1) << GPIO_LOCK_P25_Pos) 8311 #define GPIO_LOCK_P26_Pos 26 /**< \brief (GPIO_LOCK) Lock State */ 8312 #define GPIO_LOCK_P26 (_U_(0x1) << GPIO_LOCK_P26_Pos) 8313 #define GPIO_LOCK_P27_Pos 27 /**< \brief (GPIO_LOCK) Lock State */ 8314 #define GPIO_LOCK_P27 (_U_(0x1) << GPIO_LOCK_P27_Pos) 8315 #define GPIO_LOCK_P28_Pos 28 /**< \brief (GPIO_LOCK) Lock State */ 8316 #define GPIO_LOCK_P28 (_U_(0x1) << GPIO_LOCK_P28_Pos) 8317 #define GPIO_LOCK_P29_Pos 29 /**< \brief (GPIO_LOCK) Lock State */ 8318 #define GPIO_LOCK_P29 (_U_(0x1) << GPIO_LOCK_P29_Pos) 8319 #define GPIO_LOCK_P30_Pos 30 /**< \brief (GPIO_LOCK) Lock State */ 8320 #define GPIO_LOCK_P30 (_U_(0x1) << GPIO_LOCK_P30_Pos) 8321 #define GPIO_LOCK_P31_Pos 31 /**< \brief (GPIO_LOCK) Lock State */ 8322 #define GPIO_LOCK_P31 (_U_(0x1) << GPIO_LOCK_P31_Pos) 8323 #define GPIO_LOCK_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_LOCK) MASK Register */ 8324 8325 /* -------- GPIO_LOCKS : (GPIO Offset: 0x1A4) ( /W 32) port Lock Register - Set -------- */ 8326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8327 typedef union { 8328 struct { 8329 uint32_t P0:1; /*!< bit: 0 Lock State */ 8330 uint32_t P1:1; /*!< bit: 1 Lock State */ 8331 uint32_t P2:1; /*!< bit: 2 Lock State */ 8332 uint32_t P3:1; /*!< bit: 3 Lock State */ 8333 uint32_t P4:1; /*!< bit: 4 Lock State */ 8334 uint32_t P5:1; /*!< bit: 5 Lock State */ 8335 uint32_t P6:1; /*!< bit: 6 Lock State */ 8336 uint32_t P7:1; /*!< bit: 7 Lock State */ 8337 uint32_t P8:1; /*!< bit: 8 Lock State */ 8338 uint32_t P9:1; /*!< bit: 9 Lock State */ 8339 uint32_t P10:1; /*!< bit: 10 Lock State */ 8340 uint32_t P11:1; /*!< bit: 11 Lock State */ 8341 uint32_t P12:1; /*!< bit: 12 Lock State */ 8342 uint32_t P13:1; /*!< bit: 13 Lock State */ 8343 uint32_t P14:1; /*!< bit: 14 Lock State */ 8344 uint32_t P15:1; /*!< bit: 15 Lock State */ 8345 uint32_t P16:1; /*!< bit: 16 Lock State */ 8346 uint32_t P17:1; /*!< bit: 17 Lock State */ 8347 uint32_t P18:1; /*!< bit: 18 Lock State */ 8348 uint32_t P19:1; /*!< bit: 19 Lock State */ 8349 uint32_t P20:1; /*!< bit: 20 Lock State */ 8350 uint32_t P21:1; /*!< bit: 21 Lock State */ 8351 uint32_t P22:1; /*!< bit: 22 Lock State */ 8352 uint32_t P23:1; /*!< bit: 23 Lock State */ 8353 uint32_t P24:1; /*!< bit: 24 Lock State */ 8354 uint32_t P25:1; /*!< bit: 25 Lock State */ 8355 uint32_t P26:1; /*!< bit: 26 Lock State */ 8356 uint32_t P27:1; /*!< bit: 27 Lock State */ 8357 uint32_t P28:1; /*!< bit: 28 Lock State */ 8358 uint32_t P29:1; /*!< bit: 29 Lock State */ 8359 uint32_t P30:1; /*!< bit: 30 Lock State */ 8360 uint32_t P31:1; /*!< bit: 31 Lock State */ 8361 } bit; /*!< Structure used for bit access */ 8362 uint32_t reg; /*!< Type used for register access */ 8363 } GPIO_LOCKS_Type; 8364 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8365 8366 #define GPIO_LOCKS_OFFSET 0x1A4 /**< \brief (GPIO_LOCKS offset) Lock Register - Set */ 8367 8368 #define GPIO_LOCKS_P0_Pos 0 /**< \brief (GPIO_LOCKS) Lock State */ 8369 #define GPIO_LOCKS_P0 (_U_(0x1) << GPIO_LOCKS_P0_Pos) 8370 #define GPIO_LOCKS_P1_Pos 1 /**< \brief (GPIO_LOCKS) Lock State */ 8371 #define GPIO_LOCKS_P1 (_U_(0x1) << GPIO_LOCKS_P1_Pos) 8372 #define GPIO_LOCKS_P2_Pos 2 /**< \brief (GPIO_LOCKS) Lock State */ 8373 #define GPIO_LOCKS_P2 (_U_(0x1) << GPIO_LOCKS_P2_Pos) 8374 #define GPIO_LOCKS_P3_Pos 3 /**< \brief (GPIO_LOCKS) Lock State */ 8375 #define GPIO_LOCKS_P3 (_U_(0x1) << GPIO_LOCKS_P3_Pos) 8376 #define GPIO_LOCKS_P4_Pos 4 /**< \brief (GPIO_LOCKS) Lock State */ 8377 #define GPIO_LOCKS_P4 (_U_(0x1) << GPIO_LOCKS_P4_Pos) 8378 #define GPIO_LOCKS_P5_Pos 5 /**< \brief (GPIO_LOCKS) Lock State */ 8379 #define GPIO_LOCKS_P5 (_U_(0x1) << GPIO_LOCKS_P5_Pos) 8380 #define GPIO_LOCKS_P6_Pos 6 /**< \brief (GPIO_LOCKS) Lock State */ 8381 #define GPIO_LOCKS_P6 (_U_(0x1) << GPIO_LOCKS_P6_Pos) 8382 #define GPIO_LOCKS_P7_Pos 7 /**< \brief (GPIO_LOCKS) Lock State */ 8383 #define GPIO_LOCKS_P7 (_U_(0x1) << GPIO_LOCKS_P7_Pos) 8384 #define GPIO_LOCKS_P8_Pos 8 /**< \brief (GPIO_LOCKS) Lock State */ 8385 #define GPIO_LOCKS_P8 (_U_(0x1) << GPIO_LOCKS_P8_Pos) 8386 #define GPIO_LOCKS_P9_Pos 9 /**< \brief (GPIO_LOCKS) Lock State */ 8387 #define GPIO_LOCKS_P9 (_U_(0x1) << GPIO_LOCKS_P9_Pos) 8388 #define GPIO_LOCKS_P10_Pos 10 /**< \brief (GPIO_LOCKS) Lock State */ 8389 #define GPIO_LOCKS_P10 (_U_(0x1) << GPIO_LOCKS_P10_Pos) 8390 #define GPIO_LOCKS_P11_Pos 11 /**< \brief (GPIO_LOCKS) Lock State */ 8391 #define GPIO_LOCKS_P11 (_U_(0x1) << GPIO_LOCKS_P11_Pos) 8392 #define GPIO_LOCKS_P12_Pos 12 /**< \brief (GPIO_LOCKS) Lock State */ 8393 #define GPIO_LOCKS_P12 (_U_(0x1) << GPIO_LOCKS_P12_Pos) 8394 #define GPIO_LOCKS_P13_Pos 13 /**< \brief (GPIO_LOCKS) Lock State */ 8395 #define GPIO_LOCKS_P13 (_U_(0x1) << GPIO_LOCKS_P13_Pos) 8396 #define GPIO_LOCKS_P14_Pos 14 /**< \brief (GPIO_LOCKS) Lock State */ 8397 #define GPIO_LOCKS_P14 (_U_(0x1) << GPIO_LOCKS_P14_Pos) 8398 #define GPIO_LOCKS_P15_Pos 15 /**< \brief (GPIO_LOCKS) Lock State */ 8399 #define GPIO_LOCKS_P15 (_U_(0x1) << GPIO_LOCKS_P15_Pos) 8400 #define GPIO_LOCKS_P16_Pos 16 /**< \brief (GPIO_LOCKS) Lock State */ 8401 #define GPIO_LOCKS_P16 (_U_(0x1) << GPIO_LOCKS_P16_Pos) 8402 #define GPIO_LOCKS_P17_Pos 17 /**< \brief (GPIO_LOCKS) Lock State */ 8403 #define GPIO_LOCKS_P17 (_U_(0x1) << GPIO_LOCKS_P17_Pos) 8404 #define GPIO_LOCKS_P18_Pos 18 /**< \brief (GPIO_LOCKS) Lock State */ 8405 #define GPIO_LOCKS_P18 (_U_(0x1) << GPIO_LOCKS_P18_Pos) 8406 #define GPIO_LOCKS_P19_Pos 19 /**< \brief (GPIO_LOCKS) Lock State */ 8407 #define GPIO_LOCKS_P19 (_U_(0x1) << GPIO_LOCKS_P19_Pos) 8408 #define GPIO_LOCKS_P20_Pos 20 /**< \brief (GPIO_LOCKS) Lock State */ 8409 #define GPIO_LOCKS_P20 (_U_(0x1) << GPIO_LOCKS_P20_Pos) 8410 #define GPIO_LOCKS_P21_Pos 21 /**< \brief (GPIO_LOCKS) Lock State */ 8411 #define GPIO_LOCKS_P21 (_U_(0x1) << GPIO_LOCKS_P21_Pos) 8412 #define GPIO_LOCKS_P22_Pos 22 /**< \brief (GPIO_LOCKS) Lock State */ 8413 #define GPIO_LOCKS_P22 (_U_(0x1) << GPIO_LOCKS_P22_Pos) 8414 #define GPIO_LOCKS_P23_Pos 23 /**< \brief (GPIO_LOCKS) Lock State */ 8415 #define GPIO_LOCKS_P23 (_U_(0x1) << GPIO_LOCKS_P23_Pos) 8416 #define GPIO_LOCKS_P24_Pos 24 /**< \brief (GPIO_LOCKS) Lock State */ 8417 #define GPIO_LOCKS_P24 (_U_(0x1) << GPIO_LOCKS_P24_Pos) 8418 #define GPIO_LOCKS_P25_Pos 25 /**< \brief (GPIO_LOCKS) Lock State */ 8419 #define GPIO_LOCKS_P25 (_U_(0x1) << GPIO_LOCKS_P25_Pos) 8420 #define GPIO_LOCKS_P26_Pos 26 /**< \brief (GPIO_LOCKS) Lock State */ 8421 #define GPIO_LOCKS_P26 (_U_(0x1) << GPIO_LOCKS_P26_Pos) 8422 #define GPIO_LOCKS_P27_Pos 27 /**< \brief (GPIO_LOCKS) Lock State */ 8423 #define GPIO_LOCKS_P27 (_U_(0x1) << GPIO_LOCKS_P27_Pos) 8424 #define GPIO_LOCKS_P28_Pos 28 /**< \brief (GPIO_LOCKS) Lock State */ 8425 #define GPIO_LOCKS_P28 (_U_(0x1) << GPIO_LOCKS_P28_Pos) 8426 #define GPIO_LOCKS_P29_Pos 29 /**< \brief (GPIO_LOCKS) Lock State */ 8427 #define GPIO_LOCKS_P29 (_U_(0x1) << GPIO_LOCKS_P29_Pos) 8428 #define GPIO_LOCKS_P30_Pos 30 /**< \brief (GPIO_LOCKS) Lock State */ 8429 #define GPIO_LOCKS_P30 (_U_(0x1) << GPIO_LOCKS_P30_Pos) 8430 #define GPIO_LOCKS_P31_Pos 31 /**< \brief (GPIO_LOCKS) Lock State */ 8431 #define GPIO_LOCKS_P31 (_U_(0x1) << GPIO_LOCKS_P31_Pos) 8432 #define GPIO_LOCKS_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_LOCKS) MASK Register */ 8433 8434 /* -------- GPIO_LOCKC : (GPIO Offset: 0x1A8) ( /W 32) port Lock Register - Clear -------- */ 8435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8436 typedef union { 8437 struct { 8438 uint32_t P0:1; /*!< bit: 0 Lock State */ 8439 uint32_t P1:1; /*!< bit: 1 Lock State */ 8440 uint32_t P2:1; /*!< bit: 2 Lock State */ 8441 uint32_t P3:1; /*!< bit: 3 Lock State */ 8442 uint32_t P4:1; /*!< bit: 4 Lock State */ 8443 uint32_t P5:1; /*!< bit: 5 Lock State */ 8444 uint32_t P6:1; /*!< bit: 6 Lock State */ 8445 uint32_t P7:1; /*!< bit: 7 Lock State */ 8446 uint32_t P8:1; /*!< bit: 8 Lock State */ 8447 uint32_t P9:1; /*!< bit: 9 Lock State */ 8448 uint32_t P10:1; /*!< bit: 10 Lock State */ 8449 uint32_t P11:1; /*!< bit: 11 Lock State */ 8450 uint32_t P12:1; /*!< bit: 12 Lock State */ 8451 uint32_t P13:1; /*!< bit: 13 Lock State */ 8452 uint32_t P14:1; /*!< bit: 14 Lock State */ 8453 uint32_t P15:1; /*!< bit: 15 Lock State */ 8454 uint32_t P16:1; /*!< bit: 16 Lock State */ 8455 uint32_t P17:1; /*!< bit: 17 Lock State */ 8456 uint32_t P18:1; /*!< bit: 18 Lock State */ 8457 uint32_t P19:1; /*!< bit: 19 Lock State */ 8458 uint32_t P20:1; /*!< bit: 20 Lock State */ 8459 uint32_t P21:1; /*!< bit: 21 Lock State */ 8460 uint32_t P22:1; /*!< bit: 22 Lock State */ 8461 uint32_t P23:1; /*!< bit: 23 Lock State */ 8462 uint32_t P24:1; /*!< bit: 24 Lock State */ 8463 uint32_t P25:1; /*!< bit: 25 Lock State */ 8464 uint32_t P26:1; /*!< bit: 26 Lock State */ 8465 uint32_t P27:1; /*!< bit: 27 Lock State */ 8466 uint32_t P28:1; /*!< bit: 28 Lock State */ 8467 uint32_t P29:1; /*!< bit: 29 Lock State */ 8468 uint32_t P30:1; /*!< bit: 30 Lock State */ 8469 uint32_t P31:1; /*!< bit: 31 Lock State */ 8470 } bit; /*!< Structure used for bit access */ 8471 uint32_t reg; /*!< Type used for register access */ 8472 } GPIO_LOCKC_Type; 8473 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8474 8475 #define GPIO_LOCKC_OFFSET 0x1A8 /**< \brief (GPIO_LOCKC offset) Lock Register - Clear */ 8476 8477 #define GPIO_LOCKC_P0_Pos 0 /**< \brief (GPIO_LOCKC) Lock State */ 8478 #define GPIO_LOCKC_P0 (_U_(0x1) << GPIO_LOCKC_P0_Pos) 8479 #define GPIO_LOCKC_P1_Pos 1 /**< \brief (GPIO_LOCKC) Lock State */ 8480 #define GPIO_LOCKC_P1 (_U_(0x1) << GPIO_LOCKC_P1_Pos) 8481 #define GPIO_LOCKC_P2_Pos 2 /**< \brief (GPIO_LOCKC) Lock State */ 8482 #define GPIO_LOCKC_P2 (_U_(0x1) << GPIO_LOCKC_P2_Pos) 8483 #define GPIO_LOCKC_P3_Pos 3 /**< \brief (GPIO_LOCKC) Lock State */ 8484 #define GPIO_LOCKC_P3 (_U_(0x1) << GPIO_LOCKC_P3_Pos) 8485 #define GPIO_LOCKC_P4_Pos 4 /**< \brief (GPIO_LOCKC) Lock State */ 8486 #define GPIO_LOCKC_P4 (_U_(0x1) << GPIO_LOCKC_P4_Pos) 8487 #define GPIO_LOCKC_P5_Pos 5 /**< \brief (GPIO_LOCKC) Lock State */ 8488 #define GPIO_LOCKC_P5 (_U_(0x1) << GPIO_LOCKC_P5_Pos) 8489 #define GPIO_LOCKC_P6_Pos 6 /**< \brief (GPIO_LOCKC) Lock State */ 8490 #define GPIO_LOCKC_P6 (_U_(0x1) << GPIO_LOCKC_P6_Pos) 8491 #define GPIO_LOCKC_P7_Pos 7 /**< \brief (GPIO_LOCKC) Lock State */ 8492 #define GPIO_LOCKC_P7 (_U_(0x1) << GPIO_LOCKC_P7_Pos) 8493 #define GPIO_LOCKC_P8_Pos 8 /**< \brief (GPIO_LOCKC) Lock State */ 8494 #define GPIO_LOCKC_P8 (_U_(0x1) << GPIO_LOCKC_P8_Pos) 8495 #define GPIO_LOCKC_P9_Pos 9 /**< \brief (GPIO_LOCKC) Lock State */ 8496 #define GPIO_LOCKC_P9 (_U_(0x1) << GPIO_LOCKC_P9_Pos) 8497 #define GPIO_LOCKC_P10_Pos 10 /**< \brief (GPIO_LOCKC) Lock State */ 8498 #define GPIO_LOCKC_P10 (_U_(0x1) << GPIO_LOCKC_P10_Pos) 8499 #define GPIO_LOCKC_P11_Pos 11 /**< \brief (GPIO_LOCKC) Lock State */ 8500 #define GPIO_LOCKC_P11 (_U_(0x1) << GPIO_LOCKC_P11_Pos) 8501 #define GPIO_LOCKC_P12_Pos 12 /**< \brief (GPIO_LOCKC) Lock State */ 8502 #define GPIO_LOCKC_P12 (_U_(0x1) << GPIO_LOCKC_P12_Pos) 8503 #define GPIO_LOCKC_P13_Pos 13 /**< \brief (GPIO_LOCKC) Lock State */ 8504 #define GPIO_LOCKC_P13 (_U_(0x1) << GPIO_LOCKC_P13_Pos) 8505 #define GPIO_LOCKC_P14_Pos 14 /**< \brief (GPIO_LOCKC) Lock State */ 8506 #define GPIO_LOCKC_P14 (_U_(0x1) << GPIO_LOCKC_P14_Pos) 8507 #define GPIO_LOCKC_P15_Pos 15 /**< \brief (GPIO_LOCKC) Lock State */ 8508 #define GPIO_LOCKC_P15 (_U_(0x1) << GPIO_LOCKC_P15_Pos) 8509 #define GPIO_LOCKC_P16_Pos 16 /**< \brief (GPIO_LOCKC) Lock State */ 8510 #define GPIO_LOCKC_P16 (_U_(0x1) << GPIO_LOCKC_P16_Pos) 8511 #define GPIO_LOCKC_P17_Pos 17 /**< \brief (GPIO_LOCKC) Lock State */ 8512 #define GPIO_LOCKC_P17 (_U_(0x1) << GPIO_LOCKC_P17_Pos) 8513 #define GPIO_LOCKC_P18_Pos 18 /**< \brief (GPIO_LOCKC) Lock State */ 8514 #define GPIO_LOCKC_P18 (_U_(0x1) << GPIO_LOCKC_P18_Pos) 8515 #define GPIO_LOCKC_P19_Pos 19 /**< \brief (GPIO_LOCKC) Lock State */ 8516 #define GPIO_LOCKC_P19 (_U_(0x1) << GPIO_LOCKC_P19_Pos) 8517 #define GPIO_LOCKC_P20_Pos 20 /**< \brief (GPIO_LOCKC) Lock State */ 8518 #define GPIO_LOCKC_P20 (_U_(0x1) << GPIO_LOCKC_P20_Pos) 8519 #define GPIO_LOCKC_P21_Pos 21 /**< \brief (GPIO_LOCKC) Lock State */ 8520 #define GPIO_LOCKC_P21 (_U_(0x1) << GPIO_LOCKC_P21_Pos) 8521 #define GPIO_LOCKC_P22_Pos 22 /**< \brief (GPIO_LOCKC) Lock State */ 8522 #define GPIO_LOCKC_P22 (_U_(0x1) << GPIO_LOCKC_P22_Pos) 8523 #define GPIO_LOCKC_P23_Pos 23 /**< \brief (GPIO_LOCKC) Lock State */ 8524 #define GPIO_LOCKC_P23 (_U_(0x1) << GPIO_LOCKC_P23_Pos) 8525 #define GPIO_LOCKC_P24_Pos 24 /**< \brief (GPIO_LOCKC) Lock State */ 8526 #define GPIO_LOCKC_P24 (_U_(0x1) << GPIO_LOCKC_P24_Pos) 8527 #define GPIO_LOCKC_P25_Pos 25 /**< \brief (GPIO_LOCKC) Lock State */ 8528 #define GPIO_LOCKC_P25 (_U_(0x1) << GPIO_LOCKC_P25_Pos) 8529 #define GPIO_LOCKC_P26_Pos 26 /**< \brief (GPIO_LOCKC) Lock State */ 8530 #define GPIO_LOCKC_P26 (_U_(0x1) << GPIO_LOCKC_P26_Pos) 8531 #define GPIO_LOCKC_P27_Pos 27 /**< \brief (GPIO_LOCKC) Lock State */ 8532 #define GPIO_LOCKC_P27 (_U_(0x1) << GPIO_LOCKC_P27_Pos) 8533 #define GPIO_LOCKC_P28_Pos 28 /**< \brief (GPIO_LOCKC) Lock State */ 8534 #define GPIO_LOCKC_P28 (_U_(0x1) << GPIO_LOCKC_P28_Pos) 8535 #define GPIO_LOCKC_P29_Pos 29 /**< \brief (GPIO_LOCKC) Lock State */ 8536 #define GPIO_LOCKC_P29 (_U_(0x1) << GPIO_LOCKC_P29_Pos) 8537 #define GPIO_LOCKC_P30_Pos 30 /**< \brief (GPIO_LOCKC) Lock State */ 8538 #define GPIO_LOCKC_P30 (_U_(0x1) << GPIO_LOCKC_P30_Pos) 8539 #define GPIO_LOCKC_P31_Pos 31 /**< \brief (GPIO_LOCKC) Lock State */ 8540 #define GPIO_LOCKC_P31 (_U_(0x1) << GPIO_LOCKC_P31_Pos) 8541 #define GPIO_LOCKC_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_LOCKC) MASK Register */ 8542 8543 /* -------- GPIO_LOCKT : (GPIO Offset: 0x1AC) ( /W 32) port Lock Register - Toggle -------- */ 8544 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8545 typedef union { 8546 struct { 8547 uint32_t P0:1; /*!< bit: 0 Lock State */ 8548 uint32_t P1:1; /*!< bit: 1 Lock State */ 8549 uint32_t P2:1; /*!< bit: 2 Lock State */ 8550 uint32_t P3:1; /*!< bit: 3 Lock State */ 8551 uint32_t P4:1; /*!< bit: 4 Lock State */ 8552 uint32_t P5:1; /*!< bit: 5 Lock State */ 8553 uint32_t P6:1; /*!< bit: 6 Lock State */ 8554 uint32_t P7:1; /*!< bit: 7 Lock State */ 8555 uint32_t P8:1; /*!< bit: 8 Lock State */ 8556 uint32_t P9:1; /*!< bit: 9 Lock State */ 8557 uint32_t P10:1; /*!< bit: 10 Lock State */ 8558 uint32_t P11:1; /*!< bit: 11 Lock State */ 8559 uint32_t P12:1; /*!< bit: 12 Lock State */ 8560 uint32_t P13:1; /*!< bit: 13 Lock State */ 8561 uint32_t P14:1; /*!< bit: 14 Lock State */ 8562 uint32_t P15:1; /*!< bit: 15 Lock State */ 8563 uint32_t P16:1; /*!< bit: 16 Lock State */ 8564 uint32_t P17:1; /*!< bit: 17 Lock State */ 8565 uint32_t P18:1; /*!< bit: 18 Lock State */ 8566 uint32_t P19:1; /*!< bit: 19 Lock State */ 8567 uint32_t P20:1; /*!< bit: 20 Lock State */ 8568 uint32_t P21:1; /*!< bit: 21 Lock State */ 8569 uint32_t P22:1; /*!< bit: 22 Lock State */ 8570 uint32_t P23:1; /*!< bit: 23 Lock State */ 8571 uint32_t P24:1; /*!< bit: 24 Lock State */ 8572 uint32_t P25:1; /*!< bit: 25 Lock State */ 8573 uint32_t P26:1; /*!< bit: 26 Lock State */ 8574 uint32_t P27:1; /*!< bit: 27 Lock State */ 8575 uint32_t P28:1; /*!< bit: 28 Lock State */ 8576 uint32_t P29:1; /*!< bit: 29 Lock State */ 8577 uint32_t P30:1; /*!< bit: 30 Lock State */ 8578 uint32_t P31:1; /*!< bit: 31 Lock State */ 8579 } bit; /*!< Structure used for bit access */ 8580 uint32_t reg; /*!< Type used for register access */ 8581 } GPIO_LOCKT_Type; 8582 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8583 8584 #define GPIO_LOCKT_OFFSET 0x1AC /**< \brief (GPIO_LOCKT offset) Lock Register - Toggle */ 8585 8586 #define GPIO_LOCKT_P0_Pos 0 /**< \brief (GPIO_LOCKT) Lock State */ 8587 #define GPIO_LOCKT_P0 (_U_(0x1) << GPIO_LOCKT_P0_Pos) 8588 #define GPIO_LOCKT_P1_Pos 1 /**< \brief (GPIO_LOCKT) Lock State */ 8589 #define GPIO_LOCKT_P1 (_U_(0x1) << GPIO_LOCKT_P1_Pos) 8590 #define GPIO_LOCKT_P2_Pos 2 /**< \brief (GPIO_LOCKT) Lock State */ 8591 #define GPIO_LOCKT_P2 (_U_(0x1) << GPIO_LOCKT_P2_Pos) 8592 #define GPIO_LOCKT_P3_Pos 3 /**< \brief (GPIO_LOCKT) Lock State */ 8593 #define GPIO_LOCKT_P3 (_U_(0x1) << GPIO_LOCKT_P3_Pos) 8594 #define GPIO_LOCKT_P4_Pos 4 /**< \brief (GPIO_LOCKT) Lock State */ 8595 #define GPIO_LOCKT_P4 (_U_(0x1) << GPIO_LOCKT_P4_Pos) 8596 #define GPIO_LOCKT_P5_Pos 5 /**< \brief (GPIO_LOCKT) Lock State */ 8597 #define GPIO_LOCKT_P5 (_U_(0x1) << GPIO_LOCKT_P5_Pos) 8598 #define GPIO_LOCKT_P6_Pos 6 /**< \brief (GPIO_LOCKT) Lock State */ 8599 #define GPIO_LOCKT_P6 (_U_(0x1) << GPIO_LOCKT_P6_Pos) 8600 #define GPIO_LOCKT_P7_Pos 7 /**< \brief (GPIO_LOCKT) Lock State */ 8601 #define GPIO_LOCKT_P7 (_U_(0x1) << GPIO_LOCKT_P7_Pos) 8602 #define GPIO_LOCKT_P8_Pos 8 /**< \brief (GPIO_LOCKT) Lock State */ 8603 #define GPIO_LOCKT_P8 (_U_(0x1) << GPIO_LOCKT_P8_Pos) 8604 #define GPIO_LOCKT_P9_Pos 9 /**< \brief (GPIO_LOCKT) Lock State */ 8605 #define GPIO_LOCKT_P9 (_U_(0x1) << GPIO_LOCKT_P9_Pos) 8606 #define GPIO_LOCKT_P10_Pos 10 /**< \brief (GPIO_LOCKT) Lock State */ 8607 #define GPIO_LOCKT_P10 (_U_(0x1) << GPIO_LOCKT_P10_Pos) 8608 #define GPIO_LOCKT_P11_Pos 11 /**< \brief (GPIO_LOCKT) Lock State */ 8609 #define GPIO_LOCKT_P11 (_U_(0x1) << GPIO_LOCKT_P11_Pos) 8610 #define GPIO_LOCKT_P12_Pos 12 /**< \brief (GPIO_LOCKT) Lock State */ 8611 #define GPIO_LOCKT_P12 (_U_(0x1) << GPIO_LOCKT_P12_Pos) 8612 #define GPIO_LOCKT_P13_Pos 13 /**< \brief (GPIO_LOCKT) Lock State */ 8613 #define GPIO_LOCKT_P13 (_U_(0x1) << GPIO_LOCKT_P13_Pos) 8614 #define GPIO_LOCKT_P14_Pos 14 /**< \brief (GPIO_LOCKT) Lock State */ 8615 #define GPIO_LOCKT_P14 (_U_(0x1) << GPIO_LOCKT_P14_Pos) 8616 #define GPIO_LOCKT_P15_Pos 15 /**< \brief (GPIO_LOCKT) Lock State */ 8617 #define GPIO_LOCKT_P15 (_U_(0x1) << GPIO_LOCKT_P15_Pos) 8618 #define GPIO_LOCKT_P16_Pos 16 /**< \brief (GPIO_LOCKT) Lock State */ 8619 #define GPIO_LOCKT_P16 (_U_(0x1) << GPIO_LOCKT_P16_Pos) 8620 #define GPIO_LOCKT_P17_Pos 17 /**< \brief (GPIO_LOCKT) Lock State */ 8621 #define GPIO_LOCKT_P17 (_U_(0x1) << GPIO_LOCKT_P17_Pos) 8622 #define GPIO_LOCKT_P18_Pos 18 /**< \brief (GPIO_LOCKT) Lock State */ 8623 #define GPIO_LOCKT_P18 (_U_(0x1) << GPIO_LOCKT_P18_Pos) 8624 #define GPIO_LOCKT_P19_Pos 19 /**< \brief (GPIO_LOCKT) Lock State */ 8625 #define GPIO_LOCKT_P19 (_U_(0x1) << GPIO_LOCKT_P19_Pos) 8626 #define GPIO_LOCKT_P20_Pos 20 /**< \brief (GPIO_LOCKT) Lock State */ 8627 #define GPIO_LOCKT_P20 (_U_(0x1) << GPIO_LOCKT_P20_Pos) 8628 #define GPIO_LOCKT_P21_Pos 21 /**< \brief (GPIO_LOCKT) Lock State */ 8629 #define GPIO_LOCKT_P21 (_U_(0x1) << GPIO_LOCKT_P21_Pos) 8630 #define GPIO_LOCKT_P22_Pos 22 /**< \brief (GPIO_LOCKT) Lock State */ 8631 #define GPIO_LOCKT_P22 (_U_(0x1) << GPIO_LOCKT_P22_Pos) 8632 #define GPIO_LOCKT_P23_Pos 23 /**< \brief (GPIO_LOCKT) Lock State */ 8633 #define GPIO_LOCKT_P23 (_U_(0x1) << GPIO_LOCKT_P23_Pos) 8634 #define GPIO_LOCKT_P24_Pos 24 /**< \brief (GPIO_LOCKT) Lock State */ 8635 #define GPIO_LOCKT_P24 (_U_(0x1) << GPIO_LOCKT_P24_Pos) 8636 #define GPIO_LOCKT_P25_Pos 25 /**< \brief (GPIO_LOCKT) Lock State */ 8637 #define GPIO_LOCKT_P25 (_U_(0x1) << GPIO_LOCKT_P25_Pos) 8638 #define GPIO_LOCKT_P26_Pos 26 /**< \brief (GPIO_LOCKT) Lock State */ 8639 #define GPIO_LOCKT_P26 (_U_(0x1) << GPIO_LOCKT_P26_Pos) 8640 #define GPIO_LOCKT_P27_Pos 27 /**< \brief (GPIO_LOCKT) Lock State */ 8641 #define GPIO_LOCKT_P27 (_U_(0x1) << GPIO_LOCKT_P27_Pos) 8642 #define GPIO_LOCKT_P28_Pos 28 /**< \brief (GPIO_LOCKT) Lock State */ 8643 #define GPIO_LOCKT_P28 (_U_(0x1) << GPIO_LOCKT_P28_Pos) 8644 #define GPIO_LOCKT_P29_Pos 29 /**< \brief (GPIO_LOCKT) Lock State */ 8645 #define GPIO_LOCKT_P29 (_U_(0x1) << GPIO_LOCKT_P29_Pos) 8646 #define GPIO_LOCKT_P30_Pos 30 /**< \brief (GPIO_LOCKT) Lock State */ 8647 #define GPIO_LOCKT_P30 (_U_(0x1) << GPIO_LOCKT_P30_Pos) 8648 #define GPIO_LOCKT_P31_Pos 31 /**< \brief (GPIO_LOCKT) Lock State */ 8649 #define GPIO_LOCKT_P31 (_U_(0x1) << GPIO_LOCKT_P31_Pos) 8650 #define GPIO_LOCKT_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_LOCKT) MASK Register */ 8651 8652 /* -------- GPIO_UNLOCK : (GPIO Offset: 0x1E0) ( /W 32) port Unlock Register -------- */ 8653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8654 typedef union { 8655 struct { 8656 uint32_t ADDR:10; /*!< bit: 0.. 9 Offset Register */ 8657 uint32_t :14; /*!< bit: 10..23 Reserved */ 8658 uint32_t KEY:8; /*!< bit: 24..31 Unlocking Key */ 8659 } bit; /*!< Structure used for bit access */ 8660 uint32_t reg; /*!< Type used for register access */ 8661 } GPIO_UNLOCK_Type; 8662 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8663 8664 #define GPIO_UNLOCK_OFFSET 0x1E0 /**< \brief (GPIO_UNLOCK offset) Unlock Register */ 8665 8666 #define GPIO_UNLOCK_ADDR_Pos 0 /**< \brief (GPIO_UNLOCK) Offset Register */ 8667 #define GPIO_UNLOCK_ADDR_Msk (_U_(0x3FF) << GPIO_UNLOCK_ADDR_Pos) 8668 #define GPIO_UNLOCK_ADDR(value) (GPIO_UNLOCK_ADDR_Msk & ((value) << GPIO_UNLOCK_ADDR_Pos)) 8669 #define GPIO_UNLOCK_KEY_Pos 24 /**< \brief (GPIO_UNLOCK) Unlocking Key */ 8670 #define GPIO_UNLOCK_KEY_Msk (_U_(0xFF) << GPIO_UNLOCK_KEY_Pos) 8671 #define GPIO_UNLOCK_KEY(value) (GPIO_UNLOCK_KEY_Msk & ((value) << GPIO_UNLOCK_KEY_Pos)) 8672 #define GPIO_UNLOCK_MASK _U_(0xFF0003FF) /**< \brief (GPIO_UNLOCK) MASK Register */ 8673 8674 /* -------- GPIO_ASR : (GPIO Offset: 0x1E4) (R/W 32) port Access Status Register -------- */ 8675 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8676 typedef union { 8677 struct { 8678 uint32_t AR:1; /*!< bit: 0 Access Error */ 8679 uint32_t :31; /*!< bit: 1..31 Reserved */ 8680 } bit; /*!< Structure used for bit access */ 8681 uint32_t reg; /*!< Type used for register access */ 8682 } GPIO_ASR_Type; 8683 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8684 8685 #define GPIO_ASR_OFFSET 0x1E4 /**< \brief (GPIO_ASR offset) Access Status Register */ 8686 8687 #define GPIO_ASR_AR_Pos 0 /**< \brief (GPIO_ASR) Access Error */ 8688 #define GPIO_ASR_AR (_U_(0x1) << GPIO_ASR_AR_Pos) 8689 #define GPIO_ASR_MASK _U_(0x00000001) /**< \brief (GPIO_ASR) MASK Register */ 8690 8691 /* -------- GPIO_PARAMETER : (GPIO Offset: 0x1F8) (R/ 32) port Parameter Register -------- */ 8692 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8693 typedef union { 8694 struct { 8695 uint32_t PARAMETER:32; /*!< bit: 0..31 Parameter */ 8696 } bit; /*!< Structure used for bit access */ 8697 uint32_t reg; /*!< Type used for register access */ 8698 } GPIO_PARAMETER_Type; 8699 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8700 8701 #define GPIO_PARAMETER_OFFSET 0x1F8 /**< \brief (GPIO_PARAMETER offset) Parameter Register */ 8702 8703 #define GPIO_PARAMETER_PARAMETER_Pos 0 /**< \brief (GPIO_PARAMETER) Parameter */ 8704 #define GPIO_PARAMETER_PARAMETER_Msk (_U_(0xFFFFFFFF) << GPIO_PARAMETER_PARAMETER_Pos) 8705 #define GPIO_PARAMETER_PARAMETER(value) (GPIO_PARAMETER_PARAMETER_Msk & ((value) << GPIO_PARAMETER_PARAMETER_Pos)) 8706 #define GPIO_PARAMETER_MASK _U_(0xFFFFFFFF) /**< \brief (GPIO_PARAMETER) MASK Register */ 8707 8708 /* -------- GPIO_VERSION : (GPIO Offset: 0x1FC) (R/ 32) port Version Register -------- */ 8709 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8710 typedef union { 8711 struct { 8712 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 8713 uint32_t :4; /*!< bit: 12..15 Reserved */ 8714 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 8715 uint32_t :12; /*!< bit: 20..31 Reserved */ 8716 } bit; /*!< Structure used for bit access */ 8717 uint32_t reg; /*!< Type used for register access */ 8718 } GPIO_VERSION_Type; 8719 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8720 8721 #define GPIO_VERSION_OFFSET 0x1FC /**< \brief (GPIO_VERSION offset) Version Register */ 8722 #define GPIO_VERSION_RESETVALUE _U_(0x00000215); /**< \brief (GPIO_VERSION reset_value) Version Register */ 8723 8724 #define GPIO_VERSION_VERSION_Pos 0 /**< \brief (GPIO_VERSION) Version Number */ 8725 #define GPIO_VERSION_VERSION_Msk (_U_(0xFFF) << GPIO_VERSION_VERSION_Pos) 8726 #define GPIO_VERSION_VERSION(value) (GPIO_VERSION_VERSION_Msk & ((value) << GPIO_VERSION_VERSION_Pos)) 8727 #define GPIO_VERSION_VARIANT_Pos 16 /**< \brief (GPIO_VERSION) Variant Number */ 8728 #define GPIO_VERSION_VARIANT_Msk (_U_(0xF) << GPIO_VERSION_VARIANT_Pos) 8729 #define GPIO_VERSION_VARIANT(value) (GPIO_VERSION_VARIANT_Msk & ((value) << GPIO_VERSION_VARIANT_Pos)) 8730 #define GPIO_VERSION_MASK _U_(0x000F0FFF) /**< \brief (GPIO_VERSION) MASK Register */ 8731 8732 /** \brief GpioPort hardware registers */ 8733 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 8734 typedef struct { 8735 __IO uint32_t GPER; /**< \brief Offset: 0x000 (R/W 32) GPIO Enable Register */ 8736 __O uint32_t GPERS; /**< \brief Offset: 0x004 ( /W 32) GPIO Enable Register - Set */ 8737 __O uint32_t GPERC; /**< \brief Offset: 0x008 ( /W 32) GPIO Enable Register - Clear */ 8738 __O uint32_t GPERT; /**< \brief Offset: 0x00C ( /W 32) GPIO Enable Register - Toggle */ 8739 __IO uint32_t PMR0; /**< \brief Offset: 0x010 (R/W 32) Peripheral Mux Register 0 */ 8740 __O uint32_t PMR0S; /**< \brief Offset: 0x014 ( /W 32) Peripheral Mux Register 0 - Set */ 8741 __O uint32_t PMR0C; /**< \brief Offset: 0x018 ( /W 32) Peripheral Mux Register 0 - Clear */ 8742 __O uint32_t PMR0T; /**< \brief Offset: 0x01C ( /W 32) Peripheral Mux Register 0 - Toggle */ 8743 __IO uint32_t PMR1; /**< \brief Offset: 0x020 (R/W 32) Peripheral Mux Register 1 */ 8744 __O uint32_t PMR1S; /**< \brief Offset: 0x024 ( /W 32) Peripheral Mux Register 1 - Set */ 8745 __O uint32_t PMR1C; /**< \brief Offset: 0x028 ( /W 32) Peripheral Mux Register 1 - Clear */ 8746 __O uint32_t PMR1T; /**< \brief Offset: 0x02C ( /W 32) Peripheral Mux Register 1 - Toggle */ 8747 __IO uint32_t PMR2; /**< \brief Offset: 0x030 (R/W 32) Peripheral Mux Register 2 */ 8748 __O uint32_t PMR2S; /**< \brief Offset: 0x034 ( /W 32) Peripheral Mux Register 2 - Set */ 8749 __O uint32_t PMR2C; /**< \brief Offset: 0x038 ( /W 32) Peripheral Mux Register 2 - Clear */ 8750 __O uint32_t PMR2T; /**< \brief Offset: 0x03C ( /W 32) Peripheral Mux Register 2 - Toggle */ 8751 __IO uint32_t ODER; /**< \brief Offset: 0x040 (R/W 32) Output Driver Enable Register */ 8752 __O uint32_t ODERS; /**< \brief Offset: 0x044 ( /W 32) Output Driver Enable Register - Set */ 8753 __O uint32_t ODERC; /**< \brief Offset: 0x048 ( /W 32) Output Driver Enable Register - Clear */ 8754 __O uint32_t ODERT; /**< \brief Offset: 0x04C ( /W 32) Output Driver Enable Register - Toggle */ 8755 __IO uint32_t OVR; /**< \brief Offset: 0x050 (R/W 32) Output Value Register */ 8756 __O uint32_t OVRS; /**< \brief Offset: 0x054 ( /W 32) Output Value Register - Set */ 8757 __O uint32_t OVRC; /**< \brief Offset: 0x058 ( /W 32) Output Value Register - Clear */ 8758 __O uint32_t OVRT; /**< \brief Offset: 0x05C ( /W 32) Output Value Register - Toggle */ 8759 __I uint32_t PVR; /**< \brief Offset: 0x060 (R/ 32) Pin Value Register */ 8760 RoReg8 Reserved1[0xC]; 8761 __IO uint32_t PUER; /**< \brief Offset: 0x070 (R/W 32) Pull-up Enable Register */ 8762 __O uint32_t PUERS; /**< \brief Offset: 0x074 ( /W 32) Pull-up Enable Register - Set */ 8763 __O uint32_t PUERC; /**< \brief Offset: 0x078 ( /W 32) Pull-up Enable Register - Clear */ 8764 __O uint32_t PUERT; /**< \brief Offset: 0x07C ( /W 32) Pull-up Enable Register - Toggle */ 8765 __IO uint32_t PDER; /**< \brief Offset: 0x080 (R/W 32) Pull-down Enable Register */ 8766 __O uint32_t PDERS; /**< \brief Offset: 0x084 ( /W 32) Pull-down Enable Register - Set */ 8767 __O uint32_t PDERC; /**< \brief Offset: 0x088 ( /W 32) Pull-down Enable Register - Clear */ 8768 __O uint32_t PDERT; /**< \brief Offset: 0x08C ( /W 32) Pull-down Enable Register - Toggle */ 8769 __IO uint32_t IER; /**< \brief Offset: 0x090 (R/W 32) Interrupt Enable Register */ 8770 __O uint32_t IERS; /**< \brief Offset: 0x094 ( /W 32) Interrupt Enable Register - Set */ 8771 __O uint32_t IERC; /**< \brief Offset: 0x098 ( /W 32) Interrupt Enable Register - Clear */ 8772 __O uint32_t IERT; /**< \brief Offset: 0x09C ( /W 32) Interrupt Enable Register - Toggle */ 8773 __IO uint32_t IMR0; /**< \brief Offset: 0x0A0 (R/W 32) Interrupt Mode Register 0 */ 8774 __O uint32_t IMR0S; /**< \brief Offset: 0x0A4 ( /W 32) Interrupt Mode Register 0 - Set */ 8775 __O uint32_t IMR0C; /**< \brief Offset: 0x0A8 ( /W 32) Interrupt Mode Register 0 - Clear */ 8776 __O uint32_t IMR0T; /**< \brief Offset: 0x0AC ( /W 32) Interrupt Mode Register 0 - Toggle */ 8777 __IO uint32_t IMR1; /**< \brief Offset: 0x0B0 (R/W 32) Interrupt Mode Register 1 */ 8778 __O uint32_t IMR1S; /**< \brief Offset: 0x0B4 ( /W 32) Interrupt Mode Register 1 - Set */ 8779 __O uint32_t IMR1C; /**< \brief Offset: 0x0B8 ( /W 32) Interrupt Mode Register 1 - Clear */ 8780 __O uint32_t IMR1T; /**< \brief Offset: 0x0BC ( /W 32) Interrupt Mode Register 1 - Toggle */ 8781 __IO uint32_t GFER; /**< \brief Offset: 0x0C0 (R/W 32) Glitch Filter Enable Register */ 8782 __O uint32_t GFERS; /**< \brief Offset: 0x0C4 ( /W 32) Glitch Filter Enable Register - Set */ 8783 __O uint32_t GFERC; /**< \brief Offset: 0x0C8 ( /W 32) Glitch Filter Enable Register - Clear */ 8784 __O uint32_t GFERT; /**< \brief Offset: 0x0CC ( /W 32) Glitch Filter Enable Register - Toggle */ 8785 __I uint32_t IFR; /**< \brief Offset: 0x0D0 (R/ 32) Interrupt Flag Register */ 8786 RoReg8 Reserved2[0x4]; 8787 __O uint32_t IFRC; /**< \brief Offset: 0x0D8 ( /W 32) Interrupt Flag Register - Clear */ 8788 RoReg8 Reserved3[0x4]; 8789 __IO uint32_t ODMER; /**< \brief Offset: 0x0E0 (R/W 32) Open Drain Mode Register */ 8790 __O uint32_t ODMERS; /**< \brief Offset: 0x0E4 ( /W 32) Open Drain Mode Register - Set */ 8791 __O uint32_t ODMERC; /**< \brief Offset: 0x0E8 ( /W 32) Open Drain Mode Register - Clear */ 8792 __O uint32_t ODMERT; /**< \brief Offset: 0x0EC ( /W 32) Open Drain Mode Register - Toggle */ 8793 RoReg8 Reserved4[0x10]; 8794 __IO uint32_t ODCR0; /**< \brief Offset: 0x100 (R/W 32) Output Driving Capability Register 0 */ 8795 __IO uint32_t ODCR0S; /**< \brief Offset: 0x104 (R/W 32) Output Driving Capability Register 0 - Set */ 8796 __IO uint32_t ODCR0C; /**< \brief Offset: 0x108 (R/W 32) Output Driving Capability Register 0 - Clear */ 8797 __IO uint32_t ODCR0T; /**< \brief Offset: 0x10C (R/W 32) Output Driving Capability Register 0 - Toggle */ 8798 __IO uint32_t ODCR1; /**< \brief Offset: 0x110 (R/W 32) Output Driving Capability Register 1 */ 8799 __IO uint32_t ODCR1S; /**< \brief Offset: 0x114 (R/W 32) Output Driving Capability Register 1 - Set */ 8800 __IO uint32_t ODCR1C; /**< \brief Offset: 0x118 (R/W 32) Output Driving Capability Register 1 - Clear */ 8801 __IO uint32_t ODCR1T; /**< \brief Offset: 0x11C (R/W 32) Output Driving Capability Register 1 - Toggle */ 8802 RoReg8 Reserved5[0x10]; 8803 __IO uint32_t OSRR0; /**< \brief Offset: 0x130 (R/W 32) Output Slew Rate Register 0 */ 8804 __IO uint32_t OSRR0S; /**< \brief Offset: 0x134 (R/W 32) Output Slew Rate Register 0 - Set */ 8805 __IO uint32_t OSRR0C; /**< \brief Offset: 0x138 (R/W 32) Output Slew Rate Register 0 - Clear */ 8806 __IO uint32_t OSRR0T; /**< \brief Offset: 0x13C (R/W 32) Output Slew Rate Register 0 - Toggle */ 8807 RoReg8 Reserved6[0x20]; 8808 __IO uint32_t STER; /**< \brief Offset: 0x160 (R/W 32) Schmitt Trigger Enable Register */ 8809 __IO uint32_t STERS; /**< \brief Offset: 0x164 (R/W 32) Schmitt Trigger Enable Register - Set */ 8810 __IO uint32_t STERC; /**< \brief Offset: 0x168 (R/W 32) Schmitt Trigger Enable Register - Clear */ 8811 __IO uint32_t STERT; /**< \brief Offset: 0x16C (R/W 32) Schmitt Trigger Enable Register - Toggle */ 8812 RoReg8 Reserved7[0x10]; 8813 __IO uint32_t EVER; /**< \brief Offset: 0x180 (R/W 32) Event Enable Register */ 8814 __O uint32_t EVERS; /**< \brief Offset: 0x184 ( /W 32) Event Enable Register - Set */ 8815 __O uint32_t EVERC; /**< \brief Offset: 0x188 ( /W 32) Event Enable Register - Clear */ 8816 __O uint32_t EVERT; /**< \brief Offset: 0x18C ( /W 32) Event Enable Register - Toggle */ 8817 RoReg8 Reserved8[0x10]; 8818 __IO uint32_t LOCK; /**< \brief Offset: 0x1A0 (R/W 32) Lock Register */ 8819 __O uint32_t LOCKS; /**< \brief Offset: 0x1A4 ( /W 32) Lock Register - Set */ 8820 __O uint32_t LOCKC; /**< \brief Offset: 0x1A8 ( /W 32) Lock Register - Clear */ 8821 __O uint32_t LOCKT; /**< \brief Offset: 0x1AC ( /W 32) Lock Register - Toggle */ 8822 RoReg8 Reserved9[0x30]; 8823 __O uint32_t UNLOCK; /**< \brief Offset: 0x1E0 ( /W 32) Unlock Register */ 8824 __IO uint32_t ASR; /**< \brief Offset: 0x1E4 (R/W 32) Access Status Register */ 8825 RoReg8 Reserved10[0x10]; 8826 __I uint32_t PARAMETER; /**< \brief Offset: 0x1F8 (R/ 32) Parameter Register */ 8827 __I uint32_t VERSION; /**< \brief Offset: 0x1FC (R/ 32) Version Register */ 8828 } Gpio; 8829 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 8830 8831 /*@}*/ 8832 8833 #endif /* _SAM4L_GPIO_COMPONENT_ */ 8834