1 /** 2 * \file 3 * 4 * \brief Component description for FLASHCALW 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_FLASHCALW_COMPONENT_ 30 #define _SAM4L_FLASHCALW_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR FLASHCALW */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_FLASHCALW Flash Controller */ 36 /*@{*/ 37 38 #define FLASHCALW_I8322 39 #define REV_FLASHCALW 0x110 40 41 /* -------- FLASHCALW_FCR : (FLASHCALW Offset: 0x00) (R/W 32) Flash Controller Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t FRDY:1; /*!< bit: 0 Flash Ready Interrupt Enable */ 46 uint32_t :1; /*!< bit: 1 Reserved */ 47 uint32_t LOCKE:1; /*!< bit: 2 Lock Error Interrupt Enable */ 48 uint32_t PROGE:1; /*!< bit: 3 Programming Error Interrupt Enable */ 49 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 50 uint32_t FWS:1; /*!< bit: 6 Flash Wait State */ 51 uint32_t WS1OPT:1; /*!< bit: 7 Wait State 1 Optimization */ 52 uint32_t :24; /*!< bit: 8..31 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 uint32_t reg; /*!< Type used for register access */ 55 } FLASHCALW_FCR_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define FLASHCALW_FCR_OFFSET 0x00 /**< \brief (FLASHCALW_FCR offset) Flash Controller Control Register */ 59 #define FLASHCALW_FCR_RESETVALUE _U_(0x00000000); /**< \brief (FLASHCALW_FCR reset_value) Flash Controller Control Register */ 60 61 #define FLASHCALW_FCR_FRDY_Pos 0 /**< \brief (FLASHCALW_FCR) Flash Ready Interrupt Enable */ 62 #define FLASHCALW_FCR_FRDY (_U_(0x1) << FLASHCALW_FCR_FRDY_Pos) 63 #define FLASHCALW_FCR_FRDY_0_Val _U_(0x0) /**< \brief (FLASHCALW_FCR) Flash Ready does not generate an interrupt */ 64 #define FLASHCALW_FCR_FRDY_1_Val _U_(0x1) /**< \brief (FLASHCALW_FCR) Flash Ready generates an interrupt */ 65 #define FLASHCALW_FCR_FRDY_0 (FLASHCALW_FCR_FRDY_0_Val << FLASHCALW_FCR_FRDY_Pos) 66 #define FLASHCALW_FCR_FRDY_1 (FLASHCALW_FCR_FRDY_1_Val << FLASHCALW_FCR_FRDY_Pos) 67 #define FLASHCALW_FCR_LOCKE_Pos 2 /**< \brief (FLASHCALW_FCR) Lock Error Interrupt Enable */ 68 #define FLASHCALW_FCR_LOCKE (_U_(0x1) << FLASHCALW_FCR_LOCKE_Pos) 69 #define FLASHCALW_FCR_LOCKE_0_Val _U_(0x0) /**< \brief (FLASHCALW_FCR) Lock Error does not generate an interrupt */ 70 #define FLASHCALW_FCR_LOCKE_1_Val _U_(0x1) /**< \brief (FLASHCALW_FCR) Lock Error generates an interrupt */ 71 #define FLASHCALW_FCR_LOCKE_0 (FLASHCALW_FCR_LOCKE_0_Val << FLASHCALW_FCR_LOCKE_Pos) 72 #define FLASHCALW_FCR_LOCKE_1 (FLASHCALW_FCR_LOCKE_1_Val << FLASHCALW_FCR_LOCKE_Pos) 73 #define FLASHCALW_FCR_PROGE_Pos 3 /**< \brief (FLASHCALW_FCR) Programming Error Interrupt Enable */ 74 #define FLASHCALW_FCR_PROGE (_U_(0x1) << FLASHCALW_FCR_PROGE_Pos) 75 #define FLASHCALW_FCR_PROGE_0_Val _U_(0x0) /**< \brief (FLASHCALW_FCR) Programming Error does not generate an interrupt */ 76 #define FLASHCALW_FCR_PROGE_1_Val _U_(0x1) /**< \brief (FLASHCALW_FCR) Programming Error generates an interrupt */ 77 #define FLASHCALW_FCR_PROGE_0 (FLASHCALW_FCR_PROGE_0_Val << FLASHCALW_FCR_PROGE_Pos) 78 #define FLASHCALW_FCR_PROGE_1 (FLASHCALW_FCR_PROGE_1_Val << FLASHCALW_FCR_PROGE_Pos) 79 #define FLASHCALW_FCR_FWS_Pos 6 /**< \brief (FLASHCALW_FCR) Flash Wait State */ 80 #define FLASHCALW_FCR_FWS (_U_(0x1) << FLASHCALW_FCR_FWS_Pos) 81 #define FLASHCALW_FCR_FWS_0_Val _U_(0x0) /**< \brief (FLASHCALW_FCR) The flash is read with 0 wait states */ 82 #define FLASHCALW_FCR_FWS_1_Val _U_(0x1) /**< \brief (FLASHCALW_FCR) The flash is read with 1 wait states */ 83 #define FLASHCALW_FCR_FWS_0 (FLASHCALW_FCR_FWS_0_Val << FLASHCALW_FCR_FWS_Pos) 84 #define FLASHCALW_FCR_FWS_1 (FLASHCALW_FCR_FWS_1_Val << FLASHCALW_FCR_FWS_Pos) 85 #define FLASHCALW_FCR_WS1OPT_Pos 7 /**< \brief (FLASHCALW_FCR) Wait State 1 Optimization */ 86 #define FLASHCALW_FCR_WS1OPT (_U_(0x1) << FLASHCALW_FCR_WS1OPT_Pos) 87 #define FLASHCALW_FCR_MASK _U_(0x000000CD) /**< \brief (FLASHCALW_FCR) MASK Register */ 88 89 /* -------- FLASHCALW_FCMD : (FLASHCALW Offset: 0x04) (R/W 32) Flash Controller Command Register -------- */ 90 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 91 typedef union { 92 struct { 93 uint32_t CMD:6; /*!< bit: 0.. 5 Command */ 94 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 95 uint32_t PAGEN:16; /*!< bit: 8..23 Page number */ 96 uint32_t KEY:8; /*!< bit: 24..31 Write protection key */ 97 } bit; /*!< Structure used for bit access */ 98 uint32_t reg; /*!< Type used for register access */ 99 } FLASHCALW_FCMD_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #define FLASHCALW_FCMD_OFFSET 0x04 /**< \brief (FLASHCALW_FCMD offset) Flash Controller Command Register */ 103 #define FLASHCALW_FCMD_RESETVALUE _U_(0x00000000); /**< \brief (FLASHCALW_FCMD reset_value) Flash Controller Command Register */ 104 105 #define FLASHCALW_FCMD_CMD_Pos 0 /**< \brief (FLASHCALW_FCMD) Command */ 106 #define FLASHCALW_FCMD_CMD_Msk (_U_(0x3F) << FLASHCALW_FCMD_CMD_Pos) 107 #define FLASHCALW_FCMD_CMD(value) (FLASHCALW_FCMD_CMD_Msk & ((value) << FLASHCALW_FCMD_CMD_Pos)) 108 #define FLASHCALW_FCMD_CMD_NOP_Val _U_(0x0) /**< \brief (FLASHCALW_FCMD) No Operation */ 109 #define FLASHCALW_FCMD_CMD_WP_Val _U_(0x1) /**< \brief (FLASHCALW_FCMD) Write Page */ 110 #define FLASHCALW_FCMD_CMD_EP_Val _U_(0x2) /**< \brief (FLASHCALW_FCMD) Erase Page */ 111 #define FLASHCALW_FCMD_CMD_CPB_Val _U_(0x3) /**< \brief (FLASHCALW_FCMD) Clear Page Buffer */ 112 #define FLASHCALW_FCMD_CMD_LP_Val _U_(0x4) /**< \brief (FLASHCALW_FCMD) Lock Region containing page */ 113 #define FLASHCALW_FCMD_CMD_UP_Val _U_(0x5) /**< \brief (FLASHCALW_FCMD) Unlock Region containing page */ 114 #define FLASHCALW_FCMD_CMD_EA_Val _U_(0x6) /**< \brief (FLASHCALW_FCMD) Erase All, including secuity and fuse bits */ 115 #define FLASHCALW_FCMD_CMD_WGPB_Val _U_(0x7) /**< \brief (FLASHCALW_FCMD) Write General-Purpose fuse Bit */ 116 #define FLASHCALW_FCMD_CMD_EGPB_Val _U_(0x8) /**< \brief (FLASHCALW_FCMD) Erase General-Purpose fuse Bit */ 117 #define FLASHCALW_FCMD_CMD_SSB_Val _U_(0x9) /**< \brief (FLASHCALW_FCMD) Set Security Bit */ 118 #define FLASHCALW_FCMD_CMD_PGPFB_Val _U_(0xA) /**< \brief (FLASHCALW_FCMD) Program GPFuse Byte */ 119 #define FLASHCALW_FCMD_CMD_EAGPF_Val _U_(0xB) /**< \brief (FLASHCALW_FCMD) Erase All GP Fuses */ 120 #define FLASHCALW_FCMD_CMD_QPR_Val _U_(0xC) /**< \brief (FLASHCALW_FCMD) Quick Page Read */ 121 #define FLASHCALW_FCMD_CMD_WUP_Val _U_(0xD) /**< \brief (FLASHCALW_FCMD) Write User Page */ 122 #define FLASHCALW_FCMD_CMD_EUP_Val _U_(0xE) /**< \brief (FLASHCALW_FCMD) Erase User Page */ 123 #define FLASHCALW_FCMD_CMD_QPRUP_Val _U_(0xF) /**< \brief (FLASHCALW_FCMD) Quick Page Read User Page */ 124 #define FLASHCALW_FCMD_CMD_HSEN_Val _U_(0x10) /**< \brief (FLASHCALW_FCMD) High Speed Mode Enable */ 125 #define FLASHCALW_FCMD_CMD_HSDIS_Val _U_(0x11) /**< \brief (FLASHCALW_FCMD) High Speed Mode Disable */ 126 #define FLASHCALW_FCMD_CMD_NOP (FLASHCALW_FCMD_CMD_NOP_Val << FLASHCALW_FCMD_CMD_Pos) 127 #define FLASHCALW_FCMD_CMD_WP (FLASHCALW_FCMD_CMD_WP_Val << FLASHCALW_FCMD_CMD_Pos) 128 #define FLASHCALW_FCMD_CMD_EP (FLASHCALW_FCMD_CMD_EP_Val << FLASHCALW_FCMD_CMD_Pos) 129 #define FLASHCALW_FCMD_CMD_CPB (FLASHCALW_FCMD_CMD_CPB_Val << FLASHCALW_FCMD_CMD_Pos) 130 #define FLASHCALW_FCMD_CMD_LP (FLASHCALW_FCMD_CMD_LP_Val << FLASHCALW_FCMD_CMD_Pos) 131 #define FLASHCALW_FCMD_CMD_UP (FLASHCALW_FCMD_CMD_UP_Val << FLASHCALW_FCMD_CMD_Pos) 132 #define FLASHCALW_FCMD_CMD_EA (FLASHCALW_FCMD_CMD_EA_Val << FLASHCALW_FCMD_CMD_Pos) 133 #define FLASHCALW_FCMD_CMD_WGPB (FLASHCALW_FCMD_CMD_WGPB_Val << FLASHCALW_FCMD_CMD_Pos) 134 #define FLASHCALW_FCMD_CMD_EGPB (FLASHCALW_FCMD_CMD_EGPB_Val << FLASHCALW_FCMD_CMD_Pos) 135 #define FLASHCALW_FCMD_CMD_SSB (FLASHCALW_FCMD_CMD_SSB_Val << FLASHCALW_FCMD_CMD_Pos) 136 #define FLASHCALW_FCMD_CMD_PGPFB (FLASHCALW_FCMD_CMD_PGPFB_Val << FLASHCALW_FCMD_CMD_Pos) 137 #define FLASHCALW_FCMD_CMD_EAGPF (FLASHCALW_FCMD_CMD_EAGPF_Val << FLASHCALW_FCMD_CMD_Pos) 138 #define FLASHCALW_FCMD_CMD_QPR (FLASHCALW_FCMD_CMD_QPR_Val << FLASHCALW_FCMD_CMD_Pos) 139 #define FLASHCALW_FCMD_CMD_WUP (FLASHCALW_FCMD_CMD_WUP_Val << FLASHCALW_FCMD_CMD_Pos) 140 #define FLASHCALW_FCMD_CMD_EUP (FLASHCALW_FCMD_CMD_EUP_Val << FLASHCALW_FCMD_CMD_Pos) 141 #define FLASHCALW_FCMD_CMD_QPRUP (FLASHCALW_FCMD_CMD_QPRUP_Val << FLASHCALW_FCMD_CMD_Pos) 142 #define FLASHCALW_FCMD_CMD_HSEN (FLASHCALW_FCMD_CMD_HSEN_Val << FLASHCALW_FCMD_CMD_Pos) 143 #define FLASHCALW_FCMD_CMD_HSDIS (FLASHCALW_FCMD_CMD_HSDIS_Val << FLASHCALW_FCMD_CMD_Pos) 144 #define FLASHCALW_FCMD_PAGEN_Pos 8 /**< \brief (FLASHCALW_FCMD) Page number */ 145 #define FLASHCALW_FCMD_PAGEN_Msk (_U_(0xFFFF) << FLASHCALW_FCMD_PAGEN_Pos) 146 #define FLASHCALW_FCMD_PAGEN(value) (FLASHCALW_FCMD_PAGEN_Msk & ((value) << FLASHCALW_FCMD_PAGEN_Pos)) 147 #define FLASHCALW_FCMD_KEY_Pos 24 /**< \brief (FLASHCALW_FCMD) Write protection key */ 148 #define FLASHCALW_FCMD_KEY_Msk (_U_(0xFF) << FLASHCALW_FCMD_KEY_Pos) 149 #define FLASHCALW_FCMD_KEY(value) (FLASHCALW_FCMD_KEY_Msk & ((value) << FLASHCALW_FCMD_KEY_Pos)) 150 #define FLASHCALW_FCMD_KEY_KEY_Val _U_(0xA5) /**< \brief (FLASHCALW_FCMD) */ 151 #define FLASHCALW_FCMD_KEY_KEY (FLASHCALW_FCMD_KEY_KEY_Val << FLASHCALW_FCMD_KEY_Pos) 152 #define FLASHCALW_FCMD_MASK _U_(0xFFFFFF3F) /**< \brief (FLASHCALW_FCMD) MASK Register */ 153 154 /* -------- FLASHCALW_FSR : (FLASHCALW Offset: 0x08) (R/W 32) Flash Controller Status Register -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { 157 struct { 158 uint32_t FRDY:1; /*!< bit: 0 Flash Ready Status */ 159 uint32_t :1; /*!< bit: 1 Reserved */ 160 uint32_t LOCKE:1; /*!< bit: 2 Lock Error Status */ 161 uint32_t PROGE:1; /*!< bit: 3 Programming Error Status */ 162 uint32_t SECURITY:1; /*!< bit: 4 Security Bit Status */ 163 uint32_t QPRR:1; /*!< bit: 5 Quick Page Read Result */ 164 uint32_t HSMODE:1; /*!< bit: 6 High Speed Mode */ 165 uint32_t :1; /*!< bit: 7 Reserved */ 166 uint32_t ECCERR:2; /*!< bit: 8.. 9 ECC Error Status */ 167 uint32_t :6; /*!< bit: 10..15 Reserved */ 168 uint32_t LOCK0:1; /*!< bit: 16 Lock Region 0 Lock Status */ 169 uint32_t LOCK1:1; /*!< bit: 17 Lock Region 1 Lock Status */ 170 uint32_t LOCK2:1; /*!< bit: 18 Lock Region 2 Lock Status */ 171 uint32_t LOCK3:1; /*!< bit: 19 Lock Region 3 Lock Status */ 172 uint32_t LOCK4:1; /*!< bit: 20 Lock Region 4 Lock Status */ 173 uint32_t LOCK5:1; /*!< bit: 21 Lock Region 5 Lock Status */ 174 uint32_t LOCK6:1; /*!< bit: 22 Lock Region 6 Lock Status */ 175 uint32_t LOCK7:1; /*!< bit: 23 Lock Region 7 Lock Status */ 176 uint32_t LOCK8:1; /*!< bit: 24 Lock Region 8 Lock Status */ 177 uint32_t LOCK9:1; /*!< bit: 25 Lock Region 9 Lock Status */ 178 uint32_t LOCK10:1; /*!< bit: 26 Lock Region 10 Lock Status */ 179 uint32_t LOCK11:1; /*!< bit: 27 Lock Region 11 Lock Status */ 180 uint32_t LOCK12:1; /*!< bit: 28 Lock Region 12 Lock Status */ 181 uint32_t LOCK13:1; /*!< bit: 29 Lock Region 13 Lock Status */ 182 uint32_t LOCK14:1; /*!< bit: 30 Lock Region 14 Lock Status */ 183 uint32_t LOCK15:1; /*!< bit: 31 Lock Region 15 Lock Status */ 184 } bit; /*!< Structure used for bit access */ 185 uint32_t reg; /*!< Type used for register access */ 186 } FLASHCALW_FSR_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 #define FLASHCALW_FSR_OFFSET 0x08 /**< \brief (FLASHCALW_FSR offset) Flash Controller Status Register */ 190 #define FLASHCALW_FSR_RESETVALUE _U_(0x00000000); /**< \brief (FLASHCALW_FSR reset_value) Flash Controller Status Register */ 191 192 #define FLASHCALW_FSR_FRDY_Pos 0 /**< \brief (FLASHCALW_FSR) Flash Ready Status */ 193 #define FLASHCALW_FSR_FRDY (_U_(0x1) << FLASHCALW_FSR_FRDY_Pos) 194 #define FLASHCALW_FSR_LOCKE_Pos 2 /**< \brief (FLASHCALW_FSR) Lock Error Status */ 195 #define FLASHCALW_FSR_LOCKE (_U_(0x1) << FLASHCALW_FSR_LOCKE_Pos) 196 #define FLASHCALW_FSR_PROGE_Pos 3 /**< \brief (FLASHCALW_FSR) Programming Error Status */ 197 #define FLASHCALW_FSR_PROGE (_U_(0x1) << FLASHCALW_FSR_PROGE_Pos) 198 #define FLASHCALW_FSR_SECURITY_Pos 4 /**< \brief (FLASHCALW_FSR) Security Bit Status */ 199 #define FLASHCALW_FSR_SECURITY (_U_(0x1) << FLASHCALW_FSR_SECURITY_Pos) 200 #define FLASHCALW_FSR_QPRR_Pos 5 /**< \brief (FLASHCALW_FSR) Quick Page Read Result */ 201 #define FLASHCALW_FSR_QPRR (_U_(0x1) << FLASHCALW_FSR_QPRR_Pos) 202 #define FLASHCALW_FSR_HSMODE_Pos 6 /**< \brief (FLASHCALW_FSR) High Speed Mode */ 203 #define FLASHCALW_FSR_HSMODE (_U_(0x1) << FLASHCALW_FSR_HSMODE_Pos) 204 #define FLASHCALW_FSR_ECCERR_Pos 8 /**< \brief (FLASHCALW_FSR) ECC Error Status */ 205 #define FLASHCALW_FSR_ECCERR_Msk (_U_(0x3) << FLASHCALW_FSR_ECCERR_Pos) 206 #define FLASHCALW_FSR_ECCERR(value) (FLASHCALW_FSR_ECCERR_Msk & ((value) << FLASHCALW_FSR_ECCERR_Pos)) 207 #define FLASHCALW_FSR_ECCERR_NOERROR_Val _U_(0x0) /**< \brief (FLASHCALW_FSR) no error */ 208 #define FLASHCALW_FSR_ECCERR_ONEECCERR_Val _U_(0x1) /**< \brief (FLASHCALW_FSR) one ECC error detected */ 209 #define FLASHCALW_FSR_ECCERR_TWOECCERR_Val _U_(0x2) /**< \brief (FLASHCALW_FSR) two ECC errors detected */ 210 #define FLASHCALW_FSR_ECCERR_NOERROR (FLASHCALW_FSR_ECCERR_NOERROR_Val << FLASHCALW_FSR_ECCERR_Pos) 211 #define FLASHCALW_FSR_ECCERR_ONEECCERR (FLASHCALW_FSR_ECCERR_ONEECCERR_Val << FLASHCALW_FSR_ECCERR_Pos) 212 #define FLASHCALW_FSR_ECCERR_TWOECCERR (FLASHCALW_FSR_ECCERR_TWOECCERR_Val << FLASHCALW_FSR_ECCERR_Pos) 213 #define FLASHCALW_FSR_LOCK0_Pos 16 /**< \brief (FLASHCALW_FSR) Lock Region 0 Lock Status */ 214 #define FLASHCALW_FSR_LOCK0 (_U_(0x1) << FLASHCALW_FSR_LOCK0_Pos) 215 #define FLASHCALW_FSR_LOCK1_Pos 17 /**< \brief (FLASHCALW_FSR) Lock Region 1 Lock Status */ 216 #define FLASHCALW_FSR_LOCK1 (_U_(0x1) << FLASHCALW_FSR_LOCK1_Pos) 217 #define FLASHCALW_FSR_LOCK2_Pos 18 /**< \brief (FLASHCALW_FSR) Lock Region 2 Lock Status */ 218 #define FLASHCALW_FSR_LOCK2 (_U_(0x1) << FLASHCALW_FSR_LOCK2_Pos) 219 #define FLASHCALW_FSR_LOCK3_Pos 19 /**< \brief (FLASHCALW_FSR) Lock Region 3 Lock Status */ 220 #define FLASHCALW_FSR_LOCK3 (_U_(0x1) << FLASHCALW_FSR_LOCK3_Pos) 221 #define FLASHCALW_FSR_LOCK4_Pos 20 /**< \brief (FLASHCALW_FSR) Lock Region 4 Lock Status */ 222 #define FLASHCALW_FSR_LOCK4 (_U_(0x1) << FLASHCALW_FSR_LOCK4_Pos) 223 #define FLASHCALW_FSR_LOCK5_Pos 21 /**< \brief (FLASHCALW_FSR) Lock Region 5 Lock Status */ 224 #define FLASHCALW_FSR_LOCK5 (_U_(0x1) << FLASHCALW_FSR_LOCK5_Pos) 225 #define FLASHCALW_FSR_LOCK6_Pos 22 /**< \brief (FLASHCALW_FSR) Lock Region 6 Lock Status */ 226 #define FLASHCALW_FSR_LOCK6 (_U_(0x1) << FLASHCALW_FSR_LOCK6_Pos) 227 #define FLASHCALW_FSR_LOCK7_Pos 23 /**< \brief (FLASHCALW_FSR) Lock Region 7 Lock Status */ 228 #define FLASHCALW_FSR_LOCK7 (_U_(0x1) << FLASHCALW_FSR_LOCK7_Pos) 229 #define FLASHCALW_FSR_LOCK8_Pos 24 /**< \brief (FLASHCALW_FSR) Lock Region 8 Lock Status */ 230 #define FLASHCALW_FSR_LOCK8 (_U_(0x1) << FLASHCALW_FSR_LOCK8_Pos) 231 #define FLASHCALW_FSR_LOCK9_Pos 25 /**< \brief (FLASHCALW_FSR) Lock Region 9 Lock Status */ 232 #define FLASHCALW_FSR_LOCK9 (_U_(0x1) << FLASHCALW_FSR_LOCK9_Pos) 233 #define FLASHCALW_FSR_LOCK10_Pos 26 /**< \brief (FLASHCALW_FSR) Lock Region 10 Lock Status */ 234 #define FLASHCALW_FSR_LOCK10 (_U_(0x1) << FLASHCALW_FSR_LOCK10_Pos) 235 #define FLASHCALW_FSR_LOCK11_Pos 27 /**< \brief (FLASHCALW_FSR) Lock Region 11 Lock Status */ 236 #define FLASHCALW_FSR_LOCK11 (_U_(0x1) << FLASHCALW_FSR_LOCK11_Pos) 237 #define FLASHCALW_FSR_LOCK12_Pos 28 /**< \brief (FLASHCALW_FSR) Lock Region 12 Lock Status */ 238 #define FLASHCALW_FSR_LOCK12 (_U_(0x1) << FLASHCALW_FSR_LOCK12_Pos) 239 #define FLASHCALW_FSR_LOCK13_Pos 29 /**< \brief (FLASHCALW_FSR) Lock Region 13 Lock Status */ 240 #define FLASHCALW_FSR_LOCK13 (_U_(0x1) << FLASHCALW_FSR_LOCK13_Pos) 241 #define FLASHCALW_FSR_LOCK14_Pos 30 /**< \brief (FLASHCALW_FSR) Lock Region 14 Lock Status */ 242 #define FLASHCALW_FSR_LOCK14 (_U_(0x1) << FLASHCALW_FSR_LOCK14_Pos) 243 #define FLASHCALW_FSR_LOCK15_Pos 31 /**< \brief (FLASHCALW_FSR) Lock Region 15 Lock Status */ 244 #define FLASHCALW_FSR_LOCK15 (_U_(0x1) << FLASHCALW_FSR_LOCK15_Pos) 245 #define FLASHCALW_FSR_MASK _U_(0xFFFF037D) /**< \brief (FLASHCALW_FSR) MASK Register */ 246 247 /* -------- FLASHCALW_FPR : (FLASHCALW Offset: 0x0C) (R/ 32) Flash Controller Parameter Register -------- */ 248 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 249 typedef union { 250 struct { 251 uint32_t FSZ:4; /*!< bit: 0.. 3 Flash Size */ 252 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 253 uint32_t PSZ:3; /*!< bit: 8..10 Page Size */ 254 uint32_t :21; /*!< bit: 11..31 Reserved */ 255 } bit; /*!< Structure used for bit access */ 256 uint32_t reg; /*!< Type used for register access */ 257 } FLASHCALW_FPR_Type; 258 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 259 260 #define FLASHCALW_FPR_OFFSET 0x0C /**< \brief (FLASHCALW_FPR offset) Flash Controller Parameter Register */ 261 262 #define FLASHCALW_FPR_FSZ_Pos 0 /**< \brief (FLASHCALW_FPR) Flash Size */ 263 #define FLASHCALW_FPR_FSZ_Msk (_U_(0xF) << FLASHCALW_FPR_FSZ_Pos) 264 #define FLASHCALW_FPR_FSZ(value) (FLASHCALW_FPR_FSZ_Msk & ((value) << FLASHCALW_FPR_FSZ_Pos)) 265 #define FLASHCALW_FPR_PSZ_Pos 8 /**< \brief (FLASHCALW_FPR) Page Size */ 266 #define FLASHCALW_FPR_PSZ_Msk (_U_(0x7) << FLASHCALW_FPR_PSZ_Pos) 267 #define FLASHCALW_FPR_PSZ(value) (FLASHCALW_FPR_PSZ_Msk & ((value) << FLASHCALW_FPR_PSZ_Pos)) 268 #define FLASHCALW_FPR_MASK _U_(0x0000070F) /**< \brief (FLASHCALW_FPR) MASK Register */ 269 270 /* -------- FLASHCALW_VERSION : (FLASHCALW Offset: 0x10) (R/ 32) Flash Controller Version Register -------- */ 271 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 272 typedef union { 273 struct { 274 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 275 uint32_t :4; /*!< bit: 12..15 Reserved */ 276 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 277 uint32_t :12; /*!< bit: 20..31 Reserved */ 278 } bit; /*!< Structure used for bit access */ 279 uint32_t reg; /*!< Type used for register access */ 280 } FLASHCALW_VERSION_Type; 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 282 283 #define FLASHCALW_VERSION_OFFSET 0x10 /**< \brief (FLASHCALW_VERSION offset) Flash Controller Version Register */ 284 #define FLASHCALW_VERSION_RESETVALUE _U_(0x00000110); /**< \brief (FLASHCALW_VERSION reset_value) Flash Controller Version Register */ 285 286 #define FLASHCALW_VERSION_VERSION_Pos 0 /**< \brief (FLASHCALW_VERSION) Version Number */ 287 #define FLASHCALW_VERSION_VERSION_Msk (_U_(0xFFF) << FLASHCALW_VERSION_VERSION_Pos) 288 #define FLASHCALW_VERSION_VERSION(value) (FLASHCALW_VERSION_VERSION_Msk & ((value) << FLASHCALW_VERSION_VERSION_Pos)) 289 #define FLASHCALW_VERSION_VARIANT_Pos 16 /**< \brief (FLASHCALW_VERSION) Variant Number */ 290 #define FLASHCALW_VERSION_VARIANT_Msk (_U_(0xF) << FLASHCALW_VERSION_VARIANT_Pos) 291 #define FLASHCALW_VERSION_VARIANT(value) (FLASHCALW_VERSION_VARIANT_Msk & ((value) << FLASHCALW_VERSION_VARIANT_Pos)) 292 #define FLASHCALW_VERSION_MASK _U_(0x000F0FFF) /**< \brief (FLASHCALW_VERSION) MASK Register */ 293 294 /* -------- FLASHCALW_FGPFRHI : (FLASHCALW Offset: 0x14) (R/W 32) Flash Controller General Purpose Fuse Register High -------- */ 295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 296 typedef union { 297 struct { 298 uint32_t GPF32:1; /*!< bit: 0 General Purpose Fuse 32 */ 299 uint32_t GPF33:1; /*!< bit: 1 General Purpose Fuse 33 */ 300 uint32_t GPF34:1; /*!< bit: 2 General Purpose Fuse 34 */ 301 uint32_t GPF35:1; /*!< bit: 3 General Purpose Fuse 35 */ 302 uint32_t GPF36:1; /*!< bit: 4 General Purpose Fuse 36 */ 303 uint32_t GPF37:1; /*!< bit: 5 General Purpose Fuse 37 */ 304 uint32_t GPF38:1; /*!< bit: 6 General Purpose Fuse 38 */ 305 uint32_t GPF39:1; /*!< bit: 7 General Purpose Fuse 39 */ 306 uint32_t GPF40:1; /*!< bit: 8 General Purpose Fuse 40 */ 307 uint32_t GPF41:1; /*!< bit: 9 General Purpose Fuse 41 */ 308 uint32_t GPF42:1; /*!< bit: 10 General Purpose Fuse 42 */ 309 uint32_t GPF43:1; /*!< bit: 11 General Purpose Fuse 43 */ 310 uint32_t GPF44:1; /*!< bit: 12 General Purpose Fuse 44 */ 311 uint32_t GPF45:1; /*!< bit: 13 General Purpose Fuse 45 */ 312 uint32_t GPF46:1; /*!< bit: 14 General Purpose Fuse 46 */ 313 uint32_t GPF47:1; /*!< bit: 15 General Purpose Fuse 47 */ 314 uint32_t GPF48:1; /*!< bit: 16 General Purpose Fuse 48 */ 315 uint32_t GPF49:1; /*!< bit: 17 General Purpose Fuse 49 */ 316 uint32_t GPF50:1; /*!< bit: 18 General Purpose Fuse 50 */ 317 uint32_t GPF51:1; /*!< bit: 19 General Purpose Fuse 51 */ 318 uint32_t GPF52:1; /*!< bit: 20 General Purpose Fuse 52 */ 319 uint32_t GPF53:1; /*!< bit: 21 General Purpose Fuse 53 */ 320 uint32_t GPF54:1; /*!< bit: 22 General Purpose Fuse 54 */ 321 uint32_t GPF55:1; /*!< bit: 23 General Purpose Fuse 55 */ 322 uint32_t GPF56:1; /*!< bit: 24 General Purpose Fuse 56 */ 323 uint32_t GPF57:1; /*!< bit: 25 General Purpose Fuse 57 */ 324 uint32_t GPF58:1; /*!< bit: 26 General Purpose Fuse 58 */ 325 uint32_t GPF59:1; /*!< bit: 27 General Purpose Fuse 59 */ 326 uint32_t GPF60:1; /*!< bit: 28 General Purpose Fuse 60 */ 327 uint32_t GPF61:1; /*!< bit: 29 General Purpose Fuse 61 */ 328 uint32_t GPF62:1; /*!< bit: 30 General Purpose Fuse 62 */ 329 uint32_t GPF63:1; /*!< bit: 31 General Purpose Fuse 63 */ 330 } bit; /*!< Structure used for bit access */ 331 uint32_t reg; /*!< Type used for register access */ 332 } FLASHCALW_FGPFRHI_Type; 333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 #define FLASHCALW_FGPFRHI_OFFSET 0x14 /**< \brief (FLASHCALW_FGPFRHI offset) Flash Controller General Purpose Fuse Register High */ 336 337 #define FLASHCALW_FGPFRHI_GPF32_Pos 0 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 32 */ 338 #define FLASHCALW_FGPFRHI_GPF32 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF32_Pos) 339 #define FLASHCALW_FGPFRHI_GPF33_Pos 1 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 33 */ 340 #define FLASHCALW_FGPFRHI_GPF33 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF33_Pos) 341 #define FLASHCALW_FGPFRHI_GPF34_Pos 2 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 34 */ 342 #define FLASHCALW_FGPFRHI_GPF34 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF34_Pos) 343 #define FLASHCALW_FGPFRHI_GPF35_Pos 3 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 35 */ 344 #define FLASHCALW_FGPFRHI_GPF35 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF35_Pos) 345 #define FLASHCALW_FGPFRHI_GPF36_Pos 4 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 36 */ 346 #define FLASHCALW_FGPFRHI_GPF36 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF36_Pos) 347 #define FLASHCALW_FGPFRHI_GPF37_Pos 5 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 37 */ 348 #define FLASHCALW_FGPFRHI_GPF37 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF37_Pos) 349 #define FLASHCALW_FGPFRHI_GPF38_Pos 6 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 38 */ 350 #define FLASHCALW_FGPFRHI_GPF38 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF38_Pos) 351 #define FLASHCALW_FGPFRHI_GPF39_Pos 7 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 39 */ 352 #define FLASHCALW_FGPFRHI_GPF39 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF39_Pos) 353 #define FLASHCALW_FGPFRHI_GPF40_Pos 8 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 40 */ 354 #define FLASHCALW_FGPFRHI_GPF40 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF40_Pos) 355 #define FLASHCALW_FGPFRHI_GPF41_Pos 9 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 41 */ 356 #define FLASHCALW_FGPFRHI_GPF41 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF41_Pos) 357 #define FLASHCALW_FGPFRHI_GPF42_Pos 10 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 42 */ 358 #define FLASHCALW_FGPFRHI_GPF42 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF42_Pos) 359 #define FLASHCALW_FGPFRHI_GPF43_Pos 11 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 43 */ 360 #define FLASHCALW_FGPFRHI_GPF43 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF43_Pos) 361 #define FLASHCALW_FGPFRHI_GPF44_Pos 12 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 44 */ 362 #define FLASHCALW_FGPFRHI_GPF44 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF44_Pos) 363 #define FLASHCALW_FGPFRHI_GPF45_Pos 13 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 45 */ 364 #define FLASHCALW_FGPFRHI_GPF45 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF45_Pos) 365 #define FLASHCALW_FGPFRHI_GPF46_Pos 14 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 46 */ 366 #define FLASHCALW_FGPFRHI_GPF46 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF46_Pos) 367 #define FLASHCALW_FGPFRHI_GPF47_Pos 15 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 47 */ 368 #define FLASHCALW_FGPFRHI_GPF47 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF47_Pos) 369 #define FLASHCALW_FGPFRHI_GPF48_Pos 16 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 48 */ 370 #define FLASHCALW_FGPFRHI_GPF48 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF48_Pos) 371 #define FLASHCALW_FGPFRHI_GPF49_Pos 17 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 49 */ 372 #define FLASHCALW_FGPFRHI_GPF49 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF49_Pos) 373 #define FLASHCALW_FGPFRHI_GPF50_Pos 18 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 50 */ 374 #define FLASHCALW_FGPFRHI_GPF50 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF50_Pos) 375 #define FLASHCALW_FGPFRHI_GPF51_Pos 19 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 51 */ 376 #define FLASHCALW_FGPFRHI_GPF51 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF51_Pos) 377 #define FLASHCALW_FGPFRHI_GPF52_Pos 20 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 52 */ 378 #define FLASHCALW_FGPFRHI_GPF52 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF52_Pos) 379 #define FLASHCALW_FGPFRHI_GPF53_Pos 21 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 53 */ 380 #define FLASHCALW_FGPFRHI_GPF53 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF53_Pos) 381 #define FLASHCALW_FGPFRHI_GPF54_Pos 22 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 54 */ 382 #define FLASHCALW_FGPFRHI_GPF54 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF54_Pos) 383 #define FLASHCALW_FGPFRHI_GPF55_Pos 23 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 55 */ 384 #define FLASHCALW_FGPFRHI_GPF55 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF55_Pos) 385 #define FLASHCALW_FGPFRHI_GPF56_Pos 24 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 56 */ 386 #define FLASHCALW_FGPFRHI_GPF56 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF56_Pos) 387 #define FLASHCALW_FGPFRHI_GPF57_Pos 25 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 57 */ 388 #define FLASHCALW_FGPFRHI_GPF57 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF57_Pos) 389 #define FLASHCALW_FGPFRHI_GPF58_Pos 26 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 58 */ 390 #define FLASHCALW_FGPFRHI_GPF58 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF58_Pos) 391 #define FLASHCALW_FGPFRHI_GPF59_Pos 27 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 59 */ 392 #define FLASHCALW_FGPFRHI_GPF59 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF59_Pos) 393 #define FLASHCALW_FGPFRHI_GPF60_Pos 28 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 60 */ 394 #define FLASHCALW_FGPFRHI_GPF60 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF60_Pos) 395 #define FLASHCALW_FGPFRHI_GPF61_Pos 29 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 61 */ 396 #define FLASHCALW_FGPFRHI_GPF61 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF61_Pos) 397 #define FLASHCALW_FGPFRHI_GPF62_Pos 30 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 62 */ 398 #define FLASHCALW_FGPFRHI_GPF62 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF62_Pos) 399 #define FLASHCALW_FGPFRHI_GPF63_Pos 31 /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 63 */ 400 #define FLASHCALW_FGPFRHI_GPF63 (_U_(0x1) << FLASHCALW_FGPFRHI_GPF63_Pos) 401 #define FLASHCALW_FGPFRHI_MASK _U_(0xFFFFFFFF) /**< \brief (FLASHCALW_FGPFRHI) MASK Register */ 402 403 /* -------- FLASHCALW_FGPFRLO : (FLASHCALW Offset: 0x18) (R/W 32) Flash Controller General Purpose Fuse Register Low -------- */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef union { 406 struct { 407 uint32_t LOCK0:1; /*!< bit: 0 Lock Bit 0 */ 408 uint32_t LOCK1:1; /*!< bit: 1 Lock Bit 1 */ 409 uint32_t LOCK2:1; /*!< bit: 2 Lock Bit 2 */ 410 uint32_t LOCK3:1; /*!< bit: 3 Lock Bit 3 */ 411 uint32_t LOCK4:1; /*!< bit: 4 Lock Bit 4 */ 412 uint32_t LOCK5:1; /*!< bit: 5 Lock Bit 5 */ 413 uint32_t LOCK6:1; /*!< bit: 6 Lock Bit 6 */ 414 uint32_t LOCK7:1; /*!< bit: 7 Lock Bit 7 */ 415 uint32_t LOCK8:1; /*!< bit: 8 Lock Bit 8 */ 416 uint32_t LOCK9:1; /*!< bit: 9 Lock Bit 9 */ 417 uint32_t LOCK10:1; /*!< bit: 10 Lock Bit 10 */ 418 uint32_t LOCK11:1; /*!< bit: 11 Lock Bit 11 */ 419 uint32_t LOCK12:1; /*!< bit: 12 Lock Bit 12 */ 420 uint32_t LOCK13:1; /*!< bit: 13 Lock Bit 13 */ 421 uint32_t LOCK14:1; /*!< bit: 14 Lock Bit 14 */ 422 uint32_t LOCK15:1; /*!< bit: 15 Lock Bit 15 */ 423 uint32_t GPF16:1; /*!< bit: 16 General Purpose Fuse 16 */ 424 uint32_t GPF17:1; /*!< bit: 17 General Purpose Fuse 17 */ 425 uint32_t GPF18:1; /*!< bit: 18 General Purpose Fuse 18 */ 426 uint32_t GPF19:1; /*!< bit: 19 General Purpose Fuse 19 */ 427 uint32_t GPF20:1; /*!< bit: 20 General Purpose Fuse 20 */ 428 uint32_t GPF21:1; /*!< bit: 21 General Purpose Fuse 21 */ 429 uint32_t GPF22:1; /*!< bit: 22 General Purpose Fuse 22 */ 430 uint32_t GPF23:1; /*!< bit: 23 General Purpose Fuse 23 */ 431 uint32_t GPF24:1; /*!< bit: 24 General Purpose Fuse 24 */ 432 uint32_t GPF25:1; /*!< bit: 25 General Purpose Fuse 25 */ 433 uint32_t GPF26:1; /*!< bit: 26 General Purpose Fuse 26 */ 434 uint32_t GPF27:1; /*!< bit: 27 General Purpose Fuse 27 */ 435 uint32_t GPF28:1; /*!< bit: 28 General Purpose Fuse 28 */ 436 uint32_t GPF29:1; /*!< bit: 29 General Purpose Fuse 29 */ 437 uint32_t GPF30:1; /*!< bit: 30 General Purpose Fuse 30 */ 438 uint32_t GPF31:1; /*!< bit: 31 General Purpose Fuse 31 */ 439 } bit; /*!< Structure used for bit access */ 440 uint32_t reg; /*!< Type used for register access */ 441 } FLASHCALW_FGPFRLO_Type; 442 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 443 444 #define FLASHCALW_FGPFRLO_OFFSET 0x18 /**< \brief (FLASHCALW_FGPFRLO offset) Flash Controller General Purpose Fuse Register Low */ 445 446 #define FLASHCALW_FGPFRLO_LOCK0_Pos 0 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 0 */ 447 #define FLASHCALW_FGPFRLO_LOCK0 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK0_Pos) 448 #define FLASHCALW_FGPFRLO_LOCK1_Pos 1 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 1 */ 449 #define FLASHCALW_FGPFRLO_LOCK1 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK1_Pos) 450 #define FLASHCALW_FGPFRLO_LOCK2_Pos 2 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 2 */ 451 #define FLASHCALW_FGPFRLO_LOCK2 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK2_Pos) 452 #define FLASHCALW_FGPFRLO_LOCK3_Pos 3 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 3 */ 453 #define FLASHCALW_FGPFRLO_LOCK3 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK3_Pos) 454 #define FLASHCALW_FGPFRLO_LOCK4_Pos 4 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 4 */ 455 #define FLASHCALW_FGPFRLO_LOCK4 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK4_Pos) 456 #define FLASHCALW_FGPFRLO_LOCK5_Pos 5 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 5 */ 457 #define FLASHCALW_FGPFRLO_LOCK5 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK5_Pos) 458 #define FLASHCALW_FGPFRLO_LOCK6_Pos 6 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 6 */ 459 #define FLASHCALW_FGPFRLO_LOCK6 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK6_Pos) 460 #define FLASHCALW_FGPFRLO_LOCK7_Pos 7 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 7 */ 461 #define FLASHCALW_FGPFRLO_LOCK7 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK7_Pos) 462 #define FLASHCALW_FGPFRLO_LOCK8_Pos 8 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 8 */ 463 #define FLASHCALW_FGPFRLO_LOCK8 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK8_Pos) 464 #define FLASHCALW_FGPFRLO_LOCK9_Pos 9 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 9 */ 465 #define FLASHCALW_FGPFRLO_LOCK9 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK9_Pos) 466 #define FLASHCALW_FGPFRLO_LOCK10_Pos 10 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 10 */ 467 #define FLASHCALW_FGPFRLO_LOCK10 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK10_Pos) 468 #define FLASHCALW_FGPFRLO_LOCK11_Pos 11 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 11 */ 469 #define FLASHCALW_FGPFRLO_LOCK11 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK11_Pos) 470 #define FLASHCALW_FGPFRLO_LOCK12_Pos 12 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 12 */ 471 #define FLASHCALW_FGPFRLO_LOCK12 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK12_Pos) 472 #define FLASHCALW_FGPFRLO_LOCK13_Pos 13 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 13 */ 473 #define FLASHCALW_FGPFRLO_LOCK13 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK13_Pos) 474 #define FLASHCALW_FGPFRLO_LOCK14_Pos 14 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 14 */ 475 #define FLASHCALW_FGPFRLO_LOCK14 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK14_Pos) 476 #define FLASHCALW_FGPFRLO_LOCK15_Pos 15 /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 15 */ 477 #define FLASHCALW_FGPFRLO_LOCK15 (_U_(0x1) << FLASHCALW_FGPFRLO_LOCK15_Pos) 478 #define FLASHCALW_FGPFRLO_GPF16_Pos 16 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 16 */ 479 #define FLASHCALW_FGPFRLO_GPF16 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF16_Pos) 480 #define FLASHCALW_FGPFRLO_GPF17_Pos 17 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 17 */ 481 #define FLASHCALW_FGPFRLO_GPF17 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF17_Pos) 482 #define FLASHCALW_FGPFRLO_GPF18_Pos 18 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 18 */ 483 #define FLASHCALW_FGPFRLO_GPF18 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF18_Pos) 484 #define FLASHCALW_FGPFRLO_GPF19_Pos 19 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 19 */ 485 #define FLASHCALW_FGPFRLO_GPF19 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF19_Pos) 486 #define FLASHCALW_FGPFRLO_GPF20_Pos 20 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 20 */ 487 #define FLASHCALW_FGPFRLO_GPF20 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF20_Pos) 488 #define FLASHCALW_FGPFRLO_GPF21_Pos 21 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 21 */ 489 #define FLASHCALW_FGPFRLO_GPF21 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF21_Pos) 490 #define FLASHCALW_FGPFRLO_GPF22_Pos 22 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 22 */ 491 #define FLASHCALW_FGPFRLO_GPF22 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF22_Pos) 492 #define FLASHCALW_FGPFRLO_GPF23_Pos 23 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 23 */ 493 #define FLASHCALW_FGPFRLO_GPF23 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF23_Pos) 494 #define FLASHCALW_FGPFRLO_GPF24_Pos 24 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 24 */ 495 #define FLASHCALW_FGPFRLO_GPF24 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF24_Pos) 496 #define FLASHCALW_FGPFRLO_GPF25_Pos 25 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 25 */ 497 #define FLASHCALW_FGPFRLO_GPF25 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF25_Pos) 498 #define FLASHCALW_FGPFRLO_GPF26_Pos 26 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 26 */ 499 #define FLASHCALW_FGPFRLO_GPF26 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF26_Pos) 500 #define FLASHCALW_FGPFRLO_GPF27_Pos 27 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 27 */ 501 #define FLASHCALW_FGPFRLO_GPF27 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF27_Pos) 502 #define FLASHCALW_FGPFRLO_GPF28_Pos 28 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 28 */ 503 #define FLASHCALW_FGPFRLO_GPF28 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF28_Pos) 504 #define FLASHCALW_FGPFRLO_GPF29_Pos 29 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 29 */ 505 #define FLASHCALW_FGPFRLO_GPF29 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF29_Pos) 506 #define FLASHCALW_FGPFRLO_GPF30_Pos 30 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 30 */ 507 #define FLASHCALW_FGPFRLO_GPF30 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF30_Pos) 508 #define FLASHCALW_FGPFRLO_GPF31_Pos 31 /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 31 */ 509 #define FLASHCALW_FGPFRLO_GPF31 (_U_(0x1) << FLASHCALW_FGPFRLO_GPF31_Pos) 510 #define FLASHCALW_FGPFRLO_MASK _U_(0xFFFFFFFF) /**< \brief (FLASHCALW_FGPFRLO) MASK Register */ 511 512 /** \brief FLASHCALW APB hardware registers */ 513 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 514 typedef struct { 515 __IO uint32_t FCR; /**< \brief Offset: 0x00 (R/W 32) Flash Controller Control Register */ 516 __IO uint32_t FCMD; /**< \brief Offset: 0x04 (R/W 32) Flash Controller Command Register */ 517 __IO uint32_t FSR; /**< \brief Offset: 0x08 (R/W 32) Flash Controller Status Register */ 518 __I uint32_t FPR; /**< \brief Offset: 0x0C (R/ 32) Flash Controller Parameter Register */ 519 __I uint32_t VERSION; /**< \brief Offset: 0x10 (R/ 32) Flash Controller Version Register */ 520 __IO uint32_t FGPFRHI; /**< \brief Offset: 0x14 (R/W 32) Flash Controller General Purpose Fuse Register High */ 521 __IO uint32_t FGPFRLO; /**< \brief Offset: 0x18 (R/W 32) Flash Controller General Purpose Fuse Register Low */ 522 } Flashcalw; 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 525 #define SECTION_FLASHCALW_FROW 526 527 #define SECTION_FLASHCALW_USER 528 529 /*@}*/ 530 531 /* ************************************************************************** */ 532 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 533 /* ************************************************************************** */ 534 /** \addtogroup fuses_api Peripheral Software API */ 535 /*@{*/ 536 537 538 #define FUSES_BOD18ACTION_ADDR HFLASHC_USER 539 #define FUSES_BOD18ACTION_Pos 18 /**< \brief (HFLASHC_USER) BOD18 Action */ 540 #define FUSES_BOD18ACTION_Msk (_U_(0x3) << FUSES_BOD18ACTION_Pos) 541 #define FUSES_BOD18ACTION(value) (FUSES_BOD18ACTION_Msk & ((value) << FUSES_BOD18ACTION_Pos)) 542 543 #define FUSES_BOD18EN_ADDR HFLASHC_USER 544 #define FUSES_BOD18EN_Pos 17 /**< \brief (HFLASHC_USER) BOD18 Enable */ 545 #define FUSES_BOD18EN_Msk (_U_(0x1) << FUSES_BOD18EN_Pos) 546 547 #define FUSES_BOD18HYST_ADDR HFLASHC_USER 548 #define FUSES_BOD18HYST_Pos 20 /**< \brief (HFLASHC_USER) BOD18 Hysteresis */ 549 #define FUSES_BOD18HYST_Msk (_U_(0x1) << FUSES_BOD18HYST_Pos) 550 551 #define FUSES_BOD18LV_ADDR HFLASHC_USER 552 #define FUSES_BOD18LV_Pos 11 /**< \brief (HFLASHC_USER) BOD18 Level */ 553 #define FUSES_BOD18LV_Msk (_U_(0x3F) << FUSES_BOD18LV_Pos) 554 #define FUSES_BOD18LV(value) (FUSES_BOD18LV_Msk & ((value) << FUSES_BOD18LV_Pos)) 555 556 #define FUSES_BOD33ACTION_ADDR HFLASHC_USER 557 #define FUSES_BOD33ACTION_Pos 8 /**< \brief (HFLASHC_USER) BOD33 Action */ 558 #define FUSES_BOD33ACTION_Msk (_U_(0x3) << FUSES_BOD33ACTION_Pos) 559 #define FUSES_BOD33ACTION(value) (FUSES_BOD33ACTION_Msk & ((value) << FUSES_BOD33ACTION_Pos)) 560 561 #define FUSES_BOD33EN_ADDR HFLASHC_USER 562 #define FUSES_BOD33EN_Pos 7 /**< \brief (HFLASHC_USER) BOD33 Enable */ 563 #define FUSES_BOD33EN_Msk (_U_(0x1) << FUSES_BOD33EN_Pos) 564 565 #define FUSES_BOD33LEVEL_ADDR HFLASHC_USER 566 #define FUSES_BOD33LEVEL_Pos 1 /**< \brief (HFLASHC_USER) BOD33 Level */ 567 #define FUSES_BOD33LEVEL_Msk (_U_(0x3F) << FUSES_BOD33LEVEL_Pos) 568 #define FUSES_BOD33LEVEL(value) (FUSES_BOD33LEVEL_Msk & ((value) << FUSES_BOD33LEVEL_Pos)) 569 570 #define FUSES_BOD33_HYST_ADDR HFLASHC_USER 571 #define FUSES_BOD33_HYST_Pos 10 /**< \brief (HFLASHC_USER) BOD33 Hysteresis */ 572 #define FUSES_BOD33_HYST_Msk (_U_(0x1) << FUSES_BOD33_HYST_Pos) 573 574 #define WDT_FUSES_WDTAUTO_ADDR HFLASHC_USER 575 #define WDT_FUSES_WDTAUTO_Pos 0 /**< \brief (HFLASHC_USER) Watchdog Enabled at Reset */ 576 #define WDT_FUSES_WDTAUTO_Msk (_U_(0x1) << WDT_FUSES_WDTAUTO_Pos) 577 578 /*@}*/ 579 580 #endif /* _SAM4L_FLASHCALW_COMPONENT_ */ 581
