1 /** 2 * \file 3 * 4 * \brief Component description for EIC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_EIC_COMPONENT_ 30 #define _SAM4L_EIC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR EIC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_EIC External Interrupt Controller */ 36 /*@{*/ 37 38 #define EIC_I7529 39 #define REV_EIC 0x302 40 41 /* -------- EIC_IER : (EIC Offset: 0x000) ( /W 32) Interrupt Enable Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 46 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 47 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 48 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 49 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 50 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 51 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 52 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 53 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 54 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 55 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 56 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 57 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 58 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 59 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 60 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 61 uint32_t :16; /*!< bit: 16..31 Reserved */ 62 } bit; /*!< Structure used for bit access */ 63 uint32_t reg; /*!< Type used for register access */ 64 } EIC_IER_Type; 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define EIC_IER_OFFSET 0x000 /**< \brief (EIC_IER offset) Interrupt Enable Register */ 68 #define EIC_IER_RESETVALUE _U_(0x00000000); /**< \brief (EIC_IER reset_value) Interrupt Enable Register */ 69 70 #define EIC_IER_NMI_Pos 0 /**< \brief (EIC_IER) External Non Maskable CPU interrupt */ 71 #define EIC_IER_NMI (_U_(0x1) << EIC_IER_NMI_Pos) 72 #define EIC_IER_INT1_Pos 1 /**< \brief (EIC_IER) External Interrupt 1 */ 73 #define EIC_IER_INT1 (_U_(0x1) << EIC_IER_INT1_Pos) 74 #define EIC_IER_INT1_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */ 75 #define EIC_IER_INT1_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */ 76 #define EIC_IER_INT1_0 (EIC_IER_INT1_0_Val << EIC_IER_INT1_Pos) 77 #define EIC_IER_INT1_1 (EIC_IER_INT1_1_Val << EIC_IER_INT1_Pos) 78 #define EIC_IER_INT2_Pos 2 /**< \brief (EIC_IER) External Interrupt 2 */ 79 #define EIC_IER_INT2 (_U_(0x1) << EIC_IER_INT2_Pos) 80 #define EIC_IER_INT2_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */ 81 #define EIC_IER_INT2_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */ 82 #define EIC_IER_INT2_0 (EIC_IER_INT2_0_Val << EIC_IER_INT2_Pos) 83 #define EIC_IER_INT2_1 (EIC_IER_INT2_1_Val << EIC_IER_INT2_Pos) 84 #define EIC_IER_INT3_Pos 3 /**< \brief (EIC_IER) External Interrupt 3 */ 85 #define EIC_IER_INT3 (_U_(0x1) << EIC_IER_INT3_Pos) 86 #define EIC_IER_INT3_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */ 87 #define EIC_IER_INT3_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */ 88 #define EIC_IER_INT3_0 (EIC_IER_INT3_0_Val << EIC_IER_INT3_Pos) 89 #define EIC_IER_INT3_1 (EIC_IER_INT3_1_Val << EIC_IER_INT3_Pos) 90 #define EIC_IER_INT4_Pos 4 /**< \brief (EIC_IER) External Interrupt 4 */ 91 #define EIC_IER_INT4 (_U_(0x1) << EIC_IER_INT4_Pos) 92 #define EIC_IER_INT4_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */ 93 #define EIC_IER_INT4_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */ 94 #define EIC_IER_INT4_0 (EIC_IER_INT4_0_Val << EIC_IER_INT4_Pos) 95 #define EIC_IER_INT4_1 (EIC_IER_INT4_1_Val << EIC_IER_INT4_Pos) 96 #define EIC_IER_INT5_Pos 5 /**< \brief (EIC_IER) External Interrupt 5 */ 97 #define EIC_IER_INT5 (_U_(0x1) << EIC_IER_INT5_Pos) 98 #define EIC_IER_INT6_Pos 6 /**< \brief (EIC_IER) External Interrupt 6 */ 99 #define EIC_IER_INT6 (_U_(0x1) << EIC_IER_INT6_Pos) 100 #define EIC_IER_INT7_Pos 7 /**< \brief (EIC_IER) External Interrupt 7 */ 101 #define EIC_IER_INT7 (_U_(0x1) << EIC_IER_INT7_Pos) 102 #define EIC_IER_INT8_Pos 8 /**< \brief (EIC_IER) External Interrupt 8 */ 103 #define EIC_IER_INT8 (_U_(0x1) << EIC_IER_INT8_Pos) 104 #define EIC_IER_INT9_Pos 9 /**< \brief (EIC_IER) External Interrupt 9 */ 105 #define EIC_IER_INT9 (_U_(0x1) << EIC_IER_INT9_Pos) 106 #define EIC_IER_INT10_Pos 10 /**< \brief (EIC_IER) External Interrupt 10 */ 107 #define EIC_IER_INT10 (_U_(0x1) << EIC_IER_INT10_Pos) 108 #define EIC_IER_INT11_Pos 11 /**< \brief (EIC_IER) External Interrupt 11 */ 109 #define EIC_IER_INT11 (_U_(0x1) << EIC_IER_INT11_Pos) 110 #define EIC_IER_INT12_Pos 12 /**< \brief (EIC_IER) External Interrupt 12 */ 111 #define EIC_IER_INT12 (_U_(0x1) << EIC_IER_INT12_Pos) 112 #define EIC_IER_INT13_Pos 13 /**< \brief (EIC_IER) External Interrupt 13 */ 113 #define EIC_IER_INT13 (_U_(0x1) << EIC_IER_INT13_Pos) 114 #define EIC_IER_INT14_Pos 14 /**< \brief (EIC_IER) External Interrupt 14 */ 115 #define EIC_IER_INT14 (_U_(0x1) << EIC_IER_INT14_Pos) 116 #define EIC_IER_INT15_Pos 15 /**< \brief (EIC_IER) External Interrupt 15 */ 117 #define EIC_IER_INT15 (_U_(0x1) << EIC_IER_INT15_Pos) 118 #define EIC_IER_MASK _U_(0x0000FFFF) /**< \brief (EIC_IER) MASK Register */ 119 120 /* -------- EIC_IDR : (EIC Offset: 0x004) ( /W 32) Interrupt Disable Register -------- */ 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 122 typedef union { 123 struct { 124 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 125 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 126 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 127 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 128 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 129 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 130 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 131 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 132 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 133 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 134 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 135 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 136 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 137 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 138 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 139 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 140 uint32_t :16; /*!< bit: 16..31 Reserved */ 141 } bit; /*!< Structure used for bit access */ 142 uint32_t reg; /*!< Type used for register access */ 143 } EIC_IDR_Type; 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 #define EIC_IDR_OFFSET 0x004 /**< \brief (EIC_IDR offset) Interrupt Disable Register */ 147 #define EIC_IDR_RESETVALUE _U_(0x00000000); /**< \brief (EIC_IDR reset_value) Interrupt Disable Register */ 148 149 #define EIC_IDR_NMI_Pos 0 /**< \brief (EIC_IDR) External Non Maskable CPU interrupt */ 150 #define EIC_IDR_NMI (_U_(0x1) << EIC_IDR_NMI_Pos) 151 #define EIC_IDR_INT1_Pos 1 /**< \brief (EIC_IDR) External Interrupt 1 */ 152 #define EIC_IDR_INT1 (_U_(0x1) << EIC_IDR_INT1_Pos) 153 #define EIC_IDR_INT1_0_Val _U_(0x0) /**< \brief (EIC_IDR) No effect */ 154 #define EIC_IDR_INT1_1_Val _U_(0x1) /**< \brief (EIC_IDR) Disable Interrupt. */ 155 #define EIC_IDR_INT1_0 (EIC_IDR_INT1_0_Val << EIC_IDR_INT1_Pos) 156 #define EIC_IDR_INT1_1 (EIC_IDR_INT1_1_Val << EIC_IDR_INT1_Pos) 157 #define EIC_IDR_INT2_Pos 2 /**< \brief (EIC_IDR) External Interrupt 2 */ 158 #define EIC_IDR_INT2 (_U_(0x1) << EIC_IDR_INT2_Pos) 159 #define EIC_IDR_INT2_0_Val _U_(0x0) /**< \brief (EIC_IDR) No effect */ 160 #define EIC_IDR_INT2_1_Val _U_(0x1) /**< \brief (EIC_IDR) Disable Interrupt. */ 161 #define EIC_IDR_INT2_0 (EIC_IDR_INT2_0_Val << EIC_IDR_INT2_Pos) 162 #define EIC_IDR_INT2_1 (EIC_IDR_INT2_1_Val << EIC_IDR_INT2_Pos) 163 #define EIC_IDR_INT3_Pos 3 /**< \brief (EIC_IDR) External Interrupt 3 */ 164 #define EIC_IDR_INT3 (_U_(0x1) << EIC_IDR_INT3_Pos) 165 #define EIC_IDR_INT3_0_Val _U_(0x0) /**< \brief (EIC_IDR) No effect */ 166 #define EIC_IDR_INT3_1_Val _U_(0x1) /**< \brief (EIC_IDR) Disable Interrupt. */ 167 #define EIC_IDR_INT3_0 (EIC_IDR_INT3_0_Val << EIC_IDR_INT3_Pos) 168 #define EIC_IDR_INT3_1 (EIC_IDR_INT3_1_Val << EIC_IDR_INT3_Pos) 169 #define EIC_IDR_INT4_Pos 4 /**< \brief (EIC_IDR) External Interrupt 4 */ 170 #define EIC_IDR_INT4 (_U_(0x1) << EIC_IDR_INT4_Pos) 171 #define EIC_IDR_INT4_0_Val _U_(0x0) /**< \brief (EIC_IDR) No effect */ 172 #define EIC_IDR_INT4_1_Val _U_(0x1) /**< \brief (EIC_IDR) Disable Interrupt. */ 173 #define EIC_IDR_INT4_0 (EIC_IDR_INT4_0_Val << EIC_IDR_INT4_Pos) 174 #define EIC_IDR_INT4_1 (EIC_IDR_INT4_1_Val << EIC_IDR_INT4_Pos) 175 #define EIC_IDR_INT5_Pos 5 /**< \brief (EIC_IDR) External Interrupt 5 */ 176 #define EIC_IDR_INT5 (_U_(0x1) << EIC_IDR_INT5_Pos) 177 #define EIC_IDR_INT6_Pos 6 /**< \brief (EIC_IDR) External Interrupt 6 */ 178 #define EIC_IDR_INT6 (_U_(0x1) << EIC_IDR_INT6_Pos) 179 #define EIC_IDR_INT7_Pos 7 /**< \brief (EIC_IDR) External Interrupt 7 */ 180 #define EIC_IDR_INT7 (_U_(0x1) << EIC_IDR_INT7_Pos) 181 #define EIC_IDR_INT8_Pos 8 /**< \brief (EIC_IDR) External Interrupt 8 */ 182 #define EIC_IDR_INT8 (_U_(0x1) << EIC_IDR_INT8_Pos) 183 #define EIC_IDR_INT9_Pos 9 /**< \brief (EIC_IDR) External Interrupt 9 */ 184 #define EIC_IDR_INT9 (_U_(0x1) << EIC_IDR_INT9_Pos) 185 #define EIC_IDR_INT10_Pos 10 /**< \brief (EIC_IDR) External Interrupt 10 */ 186 #define EIC_IDR_INT10 (_U_(0x1) << EIC_IDR_INT10_Pos) 187 #define EIC_IDR_INT11_Pos 11 /**< \brief (EIC_IDR) External Interrupt 11 */ 188 #define EIC_IDR_INT11 (_U_(0x1) << EIC_IDR_INT11_Pos) 189 #define EIC_IDR_INT12_Pos 12 /**< \brief (EIC_IDR) External Interrupt 12 */ 190 #define EIC_IDR_INT12 (_U_(0x1) << EIC_IDR_INT12_Pos) 191 #define EIC_IDR_INT13_Pos 13 /**< \brief (EIC_IDR) External Interrupt 13 */ 192 #define EIC_IDR_INT13 (_U_(0x1) << EIC_IDR_INT13_Pos) 193 #define EIC_IDR_INT14_Pos 14 /**< \brief (EIC_IDR) External Interrupt 14 */ 194 #define EIC_IDR_INT14 (_U_(0x1) << EIC_IDR_INT14_Pos) 195 #define EIC_IDR_INT15_Pos 15 /**< \brief (EIC_IDR) External Interrupt 15 */ 196 #define EIC_IDR_INT15 (_U_(0x1) << EIC_IDR_INT15_Pos) 197 #define EIC_IDR_MASK _U_(0x0000FFFF) /**< \brief (EIC_IDR) MASK Register */ 198 199 /* -------- EIC_IMR : (EIC Offset: 0x008) (R/ 32) Interrupt Mask Register -------- */ 200 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 201 typedef union { 202 struct { 203 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 204 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 205 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 206 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 207 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 208 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 209 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 210 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 211 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 212 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 213 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 214 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 215 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 216 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 217 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 218 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 219 uint32_t :16; /*!< bit: 16..31 Reserved */ 220 } bit; /*!< Structure used for bit access */ 221 uint32_t reg; /*!< Type used for register access */ 222 } EIC_IMR_Type; 223 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 224 225 #define EIC_IMR_OFFSET 0x008 /**< \brief (EIC_IMR offset) Interrupt Mask Register */ 226 #define EIC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (EIC_IMR reset_value) Interrupt Mask Register */ 227 228 #define EIC_IMR_NMI_Pos 0 /**< \brief (EIC_IMR) External Non Maskable CPU interrupt */ 229 #define EIC_IMR_NMI (_U_(0x1) << EIC_IMR_NMI_Pos) 230 #define EIC_IMR_INT1_Pos 1 /**< \brief (EIC_IMR) External Interrupt 1 */ 231 #define EIC_IMR_INT1 (_U_(0x1) << EIC_IMR_INT1_Pos) 232 #define EIC_IMR_INT1_0_Val _U_(0x0) /**< \brief (EIC_IMR) Interrupt is disabled */ 233 #define EIC_IMR_INT1_1_Val _U_(0x1) /**< \brief (EIC_IMR) Interrupt is enabled. */ 234 #define EIC_IMR_INT1_0 (EIC_IMR_INT1_0_Val << EIC_IMR_INT1_Pos) 235 #define EIC_IMR_INT1_1 (EIC_IMR_INT1_1_Val << EIC_IMR_INT1_Pos) 236 #define EIC_IMR_INT2_Pos 2 /**< \brief (EIC_IMR) External Interrupt 2 */ 237 #define EIC_IMR_INT2 (_U_(0x1) << EIC_IMR_INT2_Pos) 238 #define EIC_IMR_INT2_0_Val _U_(0x0) /**< \brief (EIC_IMR) Interrupt is disabled */ 239 #define EIC_IMR_INT2_1_Val _U_(0x1) /**< \brief (EIC_IMR) Interrupt is enabled. */ 240 #define EIC_IMR_INT2_0 (EIC_IMR_INT2_0_Val << EIC_IMR_INT2_Pos) 241 #define EIC_IMR_INT2_1 (EIC_IMR_INT2_1_Val << EIC_IMR_INT2_Pos) 242 #define EIC_IMR_INT3_Pos 3 /**< \brief (EIC_IMR) External Interrupt 3 */ 243 #define EIC_IMR_INT3 (_U_(0x1) << EIC_IMR_INT3_Pos) 244 #define EIC_IMR_INT3_0_Val _U_(0x0) /**< \brief (EIC_IMR) Interrupt is disabled */ 245 #define EIC_IMR_INT3_1_Val _U_(0x1) /**< \brief (EIC_IMR) Interrupt is enabled. */ 246 #define EIC_IMR_INT3_0 (EIC_IMR_INT3_0_Val << EIC_IMR_INT3_Pos) 247 #define EIC_IMR_INT3_1 (EIC_IMR_INT3_1_Val << EIC_IMR_INT3_Pos) 248 #define EIC_IMR_INT4_Pos 4 /**< \brief (EIC_IMR) External Interrupt 4 */ 249 #define EIC_IMR_INT4 (_U_(0x1) << EIC_IMR_INT4_Pos) 250 #define EIC_IMR_INT4_0_Val _U_(0x0) /**< \brief (EIC_IMR) Interrupt is disabled */ 251 #define EIC_IMR_INT4_1_Val _U_(0x1) /**< \brief (EIC_IMR) Interrupt is enabled. */ 252 #define EIC_IMR_INT4_0 (EIC_IMR_INT4_0_Val << EIC_IMR_INT4_Pos) 253 #define EIC_IMR_INT4_1 (EIC_IMR_INT4_1_Val << EIC_IMR_INT4_Pos) 254 #define EIC_IMR_INT5_Pos 5 /**< \brief (EIC_IMR) External Interrupt 5 */ 255 #define EIC_IMR_INT5 (_U_(0x1) << EIC_IMR_INT5_Pos) 256 #define EIC_IMR_INT6_Pos 6 /**< \brief (EIC_IMR) External Interrupt 6 */ 257 #define EIC_IMR_INT6 (_U_(0x1) << EIC_IMR_INT6_Pos) 258 #define EIC_IMR_INT7_Pos 7 /**< \brief (EIC_IMR) External Interrupt 7 */ 259 #define EIC_IMR_INT7 (_U_(0x1) << EIC_IMR_INT7_Pos) 260 #define EIC_IMR_INT8_Pos 8 /**< \brief (EIC_IMR) External Interrupt 8 */ 261 #define EIC_IMR_INT8 (_U_(0x1) << EIC_IMR_INT8_Pos) 262 #define EIC_IMR_INT9_Pos 9 /**< \brief (EIC_IMR) External Interrupt 9 */ 263 #define EIC_IMR_INT9 (_U_(0x1) << EIC_IMR_INT9_Pos) 264 #define EIC_IMR_INT10_Pos 10 /**< \brief (EIC_IMR) External Interrupt 10 */ 265 #define EIC_IMR_INT10 (_U_(0x1) << EIC_IMR_INT10_Pos) 266 #define EIC_IMR_INT11_Pos 11 /**< \brief (EIC_IMR) External Interrupt 11 */ 267 #define EIC_IMR_INT11 (_U_(0x1) << EIC_IMR_INT11_Pos) 268 #define EIC_IMR_INT12_Pos 12 /**< \brief (EIC_IMR) External Interrupt 12 */ 269 #define EIC_IMR_INT12 (_U_(0x1) << EIC_IMR_INT12_Pos) 270 #define EIC_IMR_INT13_Pos 13 /**< \brief (EIC_IMR) External Interrupt 13 */ 271 #define EIC_IMR_INT13 (_U_(0x1) << EIC_IMR_INT13_Pos) 272 #define EIC_IMR_INT14_Pos 14 /**< \brief (EIC_IMR) External Interrupt 14 */ 273 #define EIC_IMR_INT14 (_U_(0x1) << EIC_IMR_INT14_Pos) 274 #define EIC_IMR_INT15_Pos 15 /**< \brief (EIC_IMR) External Interrupt 15 */ 275 #define EIC_IMR_INT15 (_U_(0x1) << EIC_IMR_INT15_Pos) 276 #define EIC_IMR_MASK _U_(0x0000FFFF) /**< \brief (EIC_IMR) MASK Register */ 277 278 /* -------- EIC_ISR : (EIC Offset: 0x00C) (R/ 32) Interrupt Status Register -------- */ 279 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 280 typedef union { 281 struct { 282 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 283 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 284 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 285 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 286 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 287 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 288 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 289 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 290 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 291 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 292 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 293 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 294 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 295 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 296 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 297 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 298 uint32_t :16; /*!< bit: 16..31 Reserved */ 299 } bit; /*!< Structure used for bit access */ 300 uint32_t reg; /*!< Type used for register access */ 301 } EIC_ISR_Type; 302 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 303 304 #define EIC_ISR_OFFSET 0x00C /**< \brief (EIC_ISR offset) Interrupt Status Register */ 305 #define EIC_ISR_RESETVALUE _U_(0x00000000); /**< \brief (EIC_ISR reset_value) Interrupt Status Register */ 306 307 #define EIC_ISR_NMI_Pos 0 /**< \brief (EIC_ISR) External Non Maskable CPU interrupt */ 308 #define EIC_ISR_NMI (_U_(0x1) << EIC_ISR_NMI_Pos) 309 #define EIC_ISR_INT1_Pos 1 /**< \brief (EIC_ISR) External Interrupt 1 */ 310 #define EIC_ISR_INT1 (_U_(0x1) << EIC_ISR_INT1_Pos) 311 #define EIC_ISR_INT1_0_Val _U_(0x0) /**< \brief (EIC_ISR) An interrupt event has not occurred */ 312 #define EIC_ISR_INT1_1_Val _U_(0x1) /**< \brief (EIC_ISR) An interrupt event has occurred. */ 313 #define EIC_ISR_INT1_0 (EIC_ISR_INT1_0_Val << EIC_ISR_INT1_Pos) 314 #define EIC_ISR_INT1_1 (EIC_ISR_INT1_1_Val << EIC_ISR_INT1_Pos) 315 #define EIC_ISR_INT2_Pos 2 /**< \brief (EIC_ISR) External Interrupt 2 */ 316 #define EIC_ISR_INT2 (_U_(0x1) << EIC_ISR_INT2_Pos) 317 #define EIC_ISR_INT2_0_Val _U_(0x0) /**< \brief (EIC_ISR) An interrupt event has not occurred */ 318 #define EIC_ISR_INT2_1_Val _U_(0x1) /**< \brief (EIC_ISR) An interrupt event has occurred. */ 319 #define EIC_ISR_INT2_0 (EIC_ISR_INT2_0_Val << EIC_ISR_INT2_Pos) 320 #define EIC_ISR_INT2_1 (EIC_ISR_INT2_1_Val << EIC_ISR_INT2_Pos) 321 #define EIC_ISR_INT3_Pos 3 /**< \brief (EIC_ISR) External Interrupt 3 */ 322 #define EIC_ISR_INT3 (_U_(0x1) << EIC_ISR_INT3_Pos) 323 #define EIC_ISR_INT3_0_Val _U_(0x0) /**< \brief (EIC_ISR) An interrupt event has not occurred */ 324 #define EIC_ISR_INT3_1_Val _U_(0x1) /**< \brief (EIC_ISR) An interrupt event has occurred. */ 325 #define EIC_ISR_INT3_0 (EIC_ISR_INT3_0_Val << EIC_ISR_INT3_Pos) 326 #define EIC_ISR_INT3_1 (EIC_ISR_INT3_1_Val << EIC_ISR_INT3_Pos) 327 #define EIC_ISR_INT4_Pos 4 /**< \brief (EIC_ISR) External Interrupt 4 */ 328 #define EIC_ISR_INT4 (_U_(0x1) << EIC_ISR_INT4_Pos) 329 #define EIC_ISR_INT4_0_Val _U_(0x0) /**< \brief (EIC_ISR) An interrupt event has not occurred */ 330 #define EIC_ISR_INT4_1_Val _U_(0x1) /**< \brief (EIC_ISR) An interrupt event has occurred. */ 331 #define EIC_ISR_INT4_0 (EIC_ISR_INT4_0_Val << EIC_ISR_INT4_Pos) 332 #define EIC_ISR_INT4_1 (EIC_ISR_INT4_1_Val << EIC_ISR_INT4_Pos) 333 #define EIC_ISR_INT5_Pos 5 /**< \brief (EIC_ISR) External Interrupt 5 */ 334 #define EIC_ISR_INT5 (_U_(0x1) << EIC_ISR_INT5_Pos) 335 #define EIC_ISR_INT6_Pos 6 /**< \brief (EIC_ISR) External Interrupt 6 */ 336 #define EIC_ISR_INT6 (_U_(0x1) << EIC_ISR_INT6_Pos) 337 #define EIC_ISR_INT7_Pos 7 /**< \brief (EIC_ISR) External Interrupt 7 */ 338 #define EIC_ISR_INT7 (_U_(0x1) << EIC_ISR_INT7_Pos) 339 #define EIC_ISR_INT8_Pos 8 /**< \brief (EIC_ISR) External Interrupt 8 */ 340 #define EIC_ISR_INT8 (_U_(0x1) << EIC_ISR_INT8_Pos) 341 #define EIC_ISR_INT9_Pos 9 /**< \brief (EIC_ISR) External Interrupt 9 */ 342 #define EIC_ISR_INT9 (_U_(0x1) << EIC_ISR_INT9_Pos) 343 #define EIC_ISR_INT10_Pos 10 /**< \brief (EIC_ISR) External Interrupt 10 */ 344 #define EIC_ISR_INT10 (_U_(0x1) << EIC_ISR_INT10_Pos) 345 #define EIC_ISR_INT11_Pos 11 /**< \brief (EIC_ISR) External Interrupt 11 */ 346 #define EIC_ISR_INT11 (_U_(0x1) << EIC_ISR_INT11_Pos) 347 #define EIC_ISR_INT12_Pos 12 /**< \brief (EIC_ISR) External Interrupt 12 */ 348 #define EIC_ISR_INT12 (_U_(0x1) << EIC_ISR_INT12_Pos) 349 #define EIC_ISR_INT13_Pos 13 /**< \brief (EIC_ISR) External Interrupt 13 */ 350 #define EIC_ISR_INT13 (_U_(0x1) << EIC_ISR_INT13_Pos) 351 #define EIC_ISR_INT14_Pos 14 /**< \brief (EIC_ISR) External Interrupt 14 */ 352 #define EIC_ISR_INT14 (_U_(0x1) << EIC_ISR_INT14_Pos) 353 #define EIC_ISR_INT15_Pos 15 /**< \brief (EIC_ISR) External Interrupt 15 */ 354 #define EIC_ISR_INT15 (_U_(0x1) << EIC_ISR_INT15_Pos) 355 #define EIC_ISR_MASK _U_(0x0000FFFF) /**< \brief (EIC_ISR) MASK Register */ 356 357 /* -------- EIC_ICR : (EIC Offset: 0x010) ( /W 32) Interrupt Clear Register -------- */ 358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 359 typedef union { 360 struct { 361 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 362 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 363 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 364 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 365 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 366 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 367 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 368 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 369 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 370 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 371 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 372 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 373 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 374 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 375 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 376 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 377 uint32_t :16; /*!< bit: 16..31 Reserved */ 378 } bit; /*!< Structure used for bit access */ 379 uint32_t reg; /*!< Type used for register access */ 380 } EIC_ICR_Type; 381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 382 383 #define EIC_ICR_OFFSET 0x010 /**< \brief (EIC_ICR offset) Interrupt Clear Register */ 384 #define EIC_ICR_RESETVALUE _U_(0x00000000); /**< \brief (EIC_ICR reset_value) Interrupt Clear Register */ 385 386 #define EIC_ICR_NMI_Pos 0 /**< \brief (EIC_ICR) External Non Maskable CPU interrupt */ 387 #define EIC_ICR_NMI (_U_(0x1) << EIC_ICR_NMI_Pos) 388 #define EIC_ICR_INT1_Pos 1 /**< \brief (EIC_ICR) External Interrupt 1 */ 389 #define EIC_ICR_INT1 (_U_(0x1) << EIC_ICR_INT1_Pos) 390 #define EIC_ICR_INT1_0_Val _U_(0x0) /**< \brief (EIC_ICR) No effect */ 391 #define EIC_ICR_INT1_1_Val _U_(0x1) /**< \brief (EIC_ICR) Clear Interrupt. */ 392 #define EIC_ICR_INT1_0 (EIC_ICR_INT1_0_Val << EIC_ICR_INT1_Pos) 393 #define EIC_ICR_INT1_1 (EIC_ICR_INT1_1_Val << EIC_ICR_INT1_Pos) 394 #define EIC_ICR_INT2_Pos 2 /**< \brief (EIC_ICR) External Interrupt 2 */ 395 #define EIC_ICR_INT2 (_U_(0x1) << EIC_ICR_INT2_Pos) 396 #define EIC_ICR_INT2_0_Val _U_(0x0) /**< \brief (EIC_ICR) No effect */ 397 #define EIC_ICR_INT2_1_Val _U_(0x1) /**< \brief (EIC_ICR) Clear Interrupt. */ 398 #define EIC_ICR_INT2_0 (EIC_ICR_INT2_0_Val << EIC_ICR_INT2_Pos) 399 #define EIC_ICR_INT2_1 (EIC_ICR_INT2_1_Val << EIC_ICR_INT2_Pos) 400 #define EIC_ICR_INT3_Pos 3 /**< \brief (EIC_ICR) External Interrupt 3 */ 401 #define EIC_ICR_INT3 (_U_(0x1) << EIC_ICR_INT3_Pos) 402 #define EIC_ICR_INT3_0_Val _U_(0x0) /**< \brief (EIC_ICR) No effect */ 403 #define EIC_ICR_INT3_1_Val _U_(0x1) /**< \brief (EIC_ICR) Clear Interrupt. */ 404 #define EIC_ICR_INT3_0 (EIC_ICR_INT3_0_Val << EIC_ICR_INT3_Pos) 405 #define EIC_ICR_INT3_1 (EIC_ICR_INT3_1_Val << EIC_ICR_INT3_Pos) 406 #define EIC_ICR_INT4_Pos 4 /**< \brief (EIC_ICR) External Interrupt 4 */ 407 #define EIC_ICR_INT4 (_U_(0x1) << EIC_ICR_INT4_Pos) 408 #define EIC_ICR_INT4_0_Val _U_(0x0) /**< \brief (EIC_ICR) No effect */ 409 #define EIC_ICR_INT4_1_Val _U_(0x1) /**< \brief (EIC_ICR) Clear Interrupt. */ 410 #define EIC_ICR_INT4_0 (EIC_ICR_INT4_0_Val << EIC_ICR_INT4_Pos) 411 #define EIC_ICR_INT4_1 (EIC_ICR_INT4_1_Val << EIC_ICR_INT4_Pos) 412 #define EIC_ICR_INT5_Pos 5 /**< \brief (EIC_ICR) External Interrupt 5 */ 413 #define EIC_ICR_INT5 (_U_(0x1) << EIC_ICR_INT5_Pos) 414 #define EIC_ICR_INT6_Pos 6 /**< \brief (EIC_ICR) External Interrupt 6 */ 415 #define EIC_ICR_INT6 (_U_(0x1) << EIC_ICR_INT6_Pos) 416 #define EIC_ICR_INT7_Pos 7 /**< \brief (EIC_ICR) External Interrupt 7 */ 417 #define EIC_ICR_INT7 (_U_(0x1) << EIC_ICR_INT7_Pos) 418 #define EIC_ICR_INT8_Pos 8 /**< \brief (EIC_ICR) External Interrupt 8 */ 419 #define EIC_ICR_INT8 (_U_(0x1) << EIC_ICR_INT8_Pos) 420 #define EIC_ICR_INT9_Pos 9 /**< \brief (EIC_ICR) External Interrupt 9 */ 421 #define EIC_ICR_INT9 (_U_(0x1) << EIC_ICR_INT9_Pos) 422 #define EIC_ICR_INT10_Pos 10 /**< \brief (EIC_ICR) External Interrupt 10 */ 423 #define EIC_ICR_INT10 (_U_(0x1) << EIC_ICR_INT10_Pos) 424 #define EIC_ICR_INT11_Pos 11 /**< \brief (EIC_ICR) External Interrupt 11 */ 425 #define EIC_ICR_INT11 (_U_(0x1) << EIC_ICR_INT11_Pos) 426 #define EIC_ICR_INT12_Pos 12 /**< \brief (EIC_ICR) External Interrupt 12 */ 427 #define EIC_ICR_INT12 (_U_(0x1) << EIC_ICR_INT12_Pos) 428 #define EIC_ICR_INT13_Pos 13 /**< \brief (EIC_ICR) External Interrupt 13 */ 429 #define EIC_ICR_INT13 (_U_(0x1) << EIC_ICR_INT13_Pos) 430 #define EIC_ICR_INT14_Pos 14 /**< \brief (EIC_ICR) External Interrupt 14 */ 431 #define EIC_ICR_INT14 (_U_(0x1) << EIC_ICR_INT14_Pos) 432 #define EIC_ICR_INT15_Pos 15 /**< \brief (EIC_ICR) External Interrupt 15 */ 433 #define EIC_ICR_INT15 (_U_(0x1) << EIC_ICR_INT15_Pos) 434 #define EIC_ICR_MASK _U_(0x0000FFFF) /**< \brief (EIC_ICR) MASK Register */ 435 436 /* -------- EIC_MODE : (EIC Offset: 0x014) (R/W 32) Mode Register -------- */ 437 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 438 typedef union { 439 struct { 440 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 441 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 442 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 443 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 444 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 445 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 446 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 447 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 448 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 449 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 450 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 451 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 452 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 453 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 454 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 455 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 456 uint32_t :16; /*!< bit: 16..31 Reserved */ 457 } bit; /*!< Structure used for bit access */ 458 uint32_t reg; /*!< Type used for register access */ 459 } EIC_MODE_Type; 460 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define EIC_MODE_OFFSET 0x014 /**< \brief (EIC_MODE offset) Mode Register */ 463 #define EIC_MODE_RESETVALUE _U_(0x00000000); /**< \brief (EIC_MODE reset_value) Mode Register */ 464 465 #define EIC_MODE_NMI_Pos 0 /**< \brief (EIC_MODE) External Non Maskable CPU interrupt */ 466 #define EIC_MODE_NMI (_U_(0x1) << EIC_MODE_NMI_Pos) 467 #define EIC_MODE_INT1_Pos 1 /**< \brief (EIC_MODE) External Interrupt 1 */ 468 #define EIC_MODE_INT1 (_U_(0x1) << EIC_MODE_INT1_Pos) 469 #define EIC_MODE_INT1_0_Val _U_(0x0) /**< \brief (EIC_MODE) Edge triggered interrupt */ 470 #define EIC_MODE_INT1_1_Val _U_(0x1) /**< \brief (EIC_MODE) Level triggered interrupt */ 471 #define EIC_MODE_INT1_0 (EIC_MODE_INT1_0_Val << EIC_MODE_INT1_Pos) 472 #define EIC_MODE_INT1_1 (EIC_MODE_INT1_1_Val << EIC_MODE_INT1_Pos) 473 #define EIC_MODE_INT2_Pos 2 /**< \brief (EIC_MODE) External Interrupt 2 */ 474 #define EIC_MODE_INT2 (_U_(0x1) << EIC_MODE_INT2_Pos) 475 #define EIC_MODE_INT2_0_Val _U_(0x0) /**< \brief (EIC_MODE) Edge triggered interrupt */ 476 #define EIC_MODE_INT2_1_Val _U_(0x1) /**< \brief (EIC_MODE) Level triggered interrupt */ 477 #define EIC_MODE_INT2_0 (EIC_MODE_INT2_0_Val << EIC_MODE_INT2_Pos) 478 #define EIC_MODE_INT2_1 (EIC_MODE_INT2_1_Val << EIC_MODE_INT2_Pos) 479 #define EIC_MODE_INT3_Pos 3 /**< \brief (EIC_MODE) External Interrupt 3 */ 480 #define EIC_MODE_INT3 (_U_(0x1) << EIC_MODE_INT3_Pos) 481 #define EIC_MODE_INT3_0_Val _U_(0x0) /**< \brief (EIC_MODE) Edge triggered interrupt */ 482 #define EIC_MODE_INT3_1_Val _U_(0x1) /**< \brief (EIC_MODE) Level triggered interrupt */ 483 #define EIC_MODE_INT3_0 (EIC_MODE_INT3_0_Val << EIC_MODE_INT3_Pos) 484 #define EIC_MODE_INT3_1 (EIC_MODE_INT3_1_Val << EIC_MODE_INT3_Pos) 485 #define EIC_MODE_INT4_Pos 4 /**< \brief (EIC_MODE) External Interrupt 4 */ 486 #define EIC_MODE_INT4 (_U_(0x1) << EIC_MODE_INT4_Pos) 487 #define EIC_MODE_INT4_0_Val _U_(0x0) /**< \brief (EIC_MODE) Edge triggered interrupt */ 488 #define EIC_MODE_INT4_1_Val _U_(0x1) /**< \brief (EIC_MODE) Level triggered interrupt */ 489 #define EIC_MODE_INT4_0 (EIC_MODE_INT4_0_Val << EIC_MODE_INT4_Pos) 490 #define EIC_MODE_INT4_1 (EIC_MODE_INT4_1_Val << EIC_MODE_INT4_Pos) 491 #define EIC_MODE_INT5_Pos 5 /**< \brief (EIC_MODE) External Interrupt 5 */ 492 #define EIC_MODE_INT5 (_U_(0x1) << EIC_MODE_INT5_Pos) 493 #define EIC_MODE_INT6_Pos 6 /**< \brief (EIC_MODE) External Interrupt 6 */ 494 #define EIC_MODE_INT6 (_U_(0x1) << EIC_MODE_INT6_Pos) 495 #define EIC_MODE_INT7_Pos 7 /**< \brief (EIC_MODE) External Interrupt 7 */ 496 #define EIC_MODE_INT7 (_U_(0x1) << EIC_MODE_INT7_Pos) 497 #define EIC_MODE_INT8_Pos 8 /**< \brief (EIC_MODE) External Interrupt 8 */ 498 #define EIC_MODE_INT8 (_U_(0x1) << EIC_MODE_INT8_Pos) 499 #define EIC_MODE_INT9_Pos 9 /**< \brief (EIC_MODE) External Interrupt 9 */ 500 #define EIC_MODE_INT9 (_U_(0x1) << EIC_MODE_INT9_Pos) 501 #define EIC_MODE_INT10_Pos 10 /**< \brief (EIC_MODE) External Interrupt 10 */ 502 #define EIC_MODE_INT10 (_U_(0x1) << EIC_MODE_INT10_Pos) 503 #define EIC_MODE_INT11_Pos 11 /**< \brief (EIC_MODE) External Interrupt 11 */ 504 #define EIC_MODE_INT11 (_U_(0x1) << EIC_MODE_INT11_Pos) 505 #define EIC_MODE_INT12_Pos 12 /**< \brief (EIC_MODE) External Interrupt 12 */ 506 #define EIC_MODE_INT12 (_U_(0x1) << EIC_MODE_INT12_Pos) 507 #define EIC_MODE_INT13_Pos 13 /**< \brief (EIC_MODE) External Interrupt 13 */ 508 #define EIC_MODE_INT13 (_U_(0x1) << EIC_MODE_INT13_Pos) 509 #define EIC_MODE_INT14_Pos 14 /**< \brief (EIC_MODE) External Interrupt 14 */ 510 #define EIC_MODE_INT14 (_U_(0x1) << EIC_MODE_INT14_Pos) 511 #define EIC_MODE_INT15_Pos 15 /**< \brief (EIC_MODE) External Interrupt 15 */ 512 #define EIC_MODE_INT15 (_U_(0x1) << EIC_MODE_INT15_Pos) 513 #define EIC_MODE_MASK _U_(0x0000FFFF) /**< \brief (EIC_MODE) MASK Register */ 514 515 /* -------- EIC_EDGE : (EIC Offset: 0x018) (R/W 32) Edge Register -------- */ 516 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 517 typedef union { 518 struct { 519 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 520 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 521 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 522 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 523 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 524 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 525 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 526 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 527 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 528 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 529 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 530 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 531 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 532 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 533 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 534 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 535 uint32_t :16; /*!< bit: 16..31 Reserved */ 536 } bit; /*!< Structure used for bit access */ 537 uint32_t reg; /*!< Type used for register access */ 538 } EIC_EDGE_Type; 539 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 540 541 #define EIC_EDGE_OFFSET 0x018 /**< \brief (EIC_EDGE offset) Edge Register */ 542 #define EIC_EDGE_RESETVALUE _U_(0x00000000); /**< \brief (EIC_EDGE reset_value) Edge Register */ 543 544 #define EIC_EDGE_NMI_Pos 0 /**< \brief (EIC_EDGE) External Non Maskable CPU interrupt */ 545 #define EIC_EDGE_NMI (_U_(0x1) << EIC_EDGE_NMI_Pos) 546 #define EIC_EDGE_INT1_Pos 1 /**< \brief (EIC_EDGE) External Interrupt 1 */ 547 #define EIC_EDGE_INT1 (_U_(0x1) << EIC_EDGE_INT1_Pos) 548 #define EIC_EDGE_INT1_0_Val _U_(0x0) /**< \brief (EIC_EDGE) Triggers on falling edge */ 549 #define EIC_EDGE_INT1_1_Val _U_(0x1) /**< \brief (EIC_EDGE) Triggers on rising edge. */ 550 #define EIC_EDGE_INT1_0 (EIC_EDGE_INT1_0_Val << EIC_EDGE_INT1_Pos) 551 #define EIC_EDGE_INT1_1 (EIC_EDGE_INT1_1_Val << EIC_EDGE_INT1_Pos) 552 #define EIC_EDGE_INT2_Pos 2 /**< \brief (EIC_EDGE) External Interrupt 2 */ 553 #define EIC_EDGE_INT2 (_U_(0x1) << EIC_EDGE_INT2_Pos) 554 #define EIC_EDGE_INT2_0_Val _U_(0x0) /**< \brief (EIC_EDGE) Triggers on falling edge */ 555 #define EIC_EDGE_INT2_1_Val _U_(0x1) /**< \brief (EIC_EDGE) Triggers on rising edge. */ 556 #define EIC_EDGE_INT2_0 (EIC_EDGE_INT2_0_Val << EIC_EDGE_INT2_Pos) 557 #define EIC_EDGE_INT2_1 (EIC_EDGE_INT2_1_Val << EIC_EDGE_INT2_Pos) 558 #define EIC_EDGE_INT3_Pos 3 /**< \brief (EIC_EDGE) External Interrupt 3 */ 559 #define EIC_EDGE_INT3 (_U_(0x1) << EIC_EDGE_INT3_Pos) 560 #define EIC_EDGE_INT3_0_Val _U_(0x0) /**< \brief (EIC_EDGE) Triggers on falling edge */ 561 #define EIC_EDGE_INT3_1_Val _U_(0x1) /**< \brief (EIC_EDGE) Triggers on rising edge. */ 562 #define EIC_EDGE_INT3_0 (EIC_EDGE_INT3_0_Val << EIC_EDGE_INT3_Pos) 563 #define EIC_EDGE_INT3_1 (EIC_EDGE_INT3_1_Val << EIC_EDGE_INT3_Pos) 564 #define EIC_EDGE_INT4_Pos 4 /**< \brief (EIC_EDGE) External Interrupt 4 */ 565 #define EIC_EDGE_INT4 (_U_(0x1) << EIC_EDGE_INT4_Pos) 566 #define EIC_EDGE_INT4_0_Val _U_(0x0) /**< \brief (EIC_EDGE) Triggers on falling edge */ 567 #define EIC_EDGE_INT4_1_Val _U_(0x1) /**< \brief (EIC_EDGE) Triggers on rising edge. */ 568 #define EIC_EDGE_INT4_0 (EIC_EDGE_INT4_0_Val << EIC_EDGE_INT4_Pos) 569 #define EIC_EDGE_INT4_1 (EIC_EDGE_INT4_1_Val << EIC_EDGE_INT4_Pos) 570 #define EIC_EDGE_INT5_Pos 5 /**< \brief (EIC_EDGE) External Interrupt 5 */ 571 #define EIC_EDGE_INT5 (_U_(0x1) << EIC_EDGE_INT5_Pos) 572 #define EIC_EDGE_INT6_Pos 6 /**< \brief (EIC_EDGE) External Interrupt 6 */ 573 #define EIC_EDGE_INT6 (_U_(0x1) << EIC_EDGE_INT6_Pos) 574 #define EIC_EDGE_INT7_Pos 7 /**< \brief (EIC_EDGE) External Interrupt 7 */ 575 #define EIC_EDGE_INT7 (_U_(0x1) << EIC_EDGE_INT7_Pos) 576 #define EIC_EDGE_INT8_Pos 8 /**< \brief (EIC_EDGE) External Interrupt 8 */ 577 #define EIC_EDGE_INT8 (_U_(0x1) << EIC_EDGE_INT8_Pos) 578 #define EIC_EDGE_INT9_Pos 9 /**< \brief (EIC_EDGE) External Interrupt 9 */ 579 #define EIC_EDGE_INT9 (_U_(0x1) << EIC_EDGE_INT9_Pos) 580 #define EIC_EDGE_INT10_Pos 10 /**< \brief (EIC_EDGE) External Interrupt 10 */ 581 #define EIC_EDGE_INT10 (_U_(0x1) << EIC_EDGE_INT10_Pos) 582 #define EIC_EDGE_INT11_Pos 11 /**< \brief (EIC_EDGE) External Interrupt 11 */ 583 #define EIC_EDGE_INT11 (_U_(0x1) << EIC_EDGE_INT11_Pos) 584 #define EIC_EDGE_INT12_Pos 12 /**< \brief (EIC_EDGE) External Interrupt 12 */ 585 #define EIC_EDGE_INT12 (_U_(0x1) << EIC_EDGE_INT12_Pos) 586 #define EIC_EDGE_INT13_Pos 13 /**< \brief (EIC_EDGE) External Interrupt 13 */ 587 #define EIC_EDGE_INT13 (_U_(0x1) << EIC_EDGE_INT13_Pos) 588 #define EIC_EDGE_INT14_Pos 14 /**< \brief (EIC_EDGE) External Interrupt 14 */ 589 #define EIC_EDGE_INT14 (_U_(0x1) << EIC_EDGE_INT14_Pos) 590 #define EIC_EDGE_INT15_Pos 15 /**< \brief (EIC_EDGE) External Interrupt 15 */ 591 #define EIC_EDGE_INT15 (_U_(0x1) << EIC_EDGE_INT15_Pos) 592 #define EIC_EDGE_MASK _U_(0x0000FFFF) /**< \brief (EIC_EDGE) MASK Register */ 593 594 /* -------- EIC_LEVEL : (EIC Offset: 0x01C) (R/W 32) Level Register -------- */ 595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 596 typedef union { 597 struct { 598 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 599 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 600 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 601 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 602 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 603 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 604 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 605 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 606 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 607 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 608 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 609 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 610 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 611 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 612 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 613 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 614 uint32_t :16; /*!< bit: 16..31 Reserved */ 615 } bit; /*!< Structure used for bit access */ 616 uint32_t reg; /*!< Type used for register access */ 617 } EIC_LEVEL_Type; 618 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 619 620 #define EIC_LEVEL_OFFSET 0x01C /**< \brief (EIC_LEVEL offset) Level Register */ 621 #define EIC_LEVEL_RESETVALUE _U_(0x00000000); /**< \brief (EIC_LEVEL reset_value) Level Register */ 622 623 #define EIC_LEVEL_NMI_Pos 0 /**< \brief (EIC_LEVEL) External Non Maskable CPU interrupt */ 624 #define EIC_LEVEL_NMI (_U_(0x1) << EIC_LEVEL_NMI_Pos) 625 #define EIC_LEVEL_INT1_Pos 1 /**< \brief (EIC_LEVEL) External Interrupt 1 */ 626 #define EIC_LEVEL_INT1 (_U_(0x1) << EIC_LEVEL_INT1_Pos) 627 #define EIC_LEVEL_INT2_Pos 2 /**< \brief (EIC_LEVEL) External Interrupt 2 */ 628 #define EIC_LEVEL_INT2 (_U_(0x1) << EIC_LEVEL_INT2_Pos) 629 #define EIC_LEVEL_INT3_Pos 3 /**< \brief (EIC_LEVEL) External Interrupt 3 */ 630 #define EIC_LEVEL_INT3 (_U_(0x1) << EIC_LEVEL_INT3_Pos) 631 #define EIC_LEVEL_INT4_Pos 4 /**< \brief (EIC_LEVEL) External Interrupt 4 */ 632 #define EIC_LEVEL_INT4 (_U_(0x1) << EIC_LEVEL_INT4_Pos) 633 #define EIC_LEVEL_INT5_Pos 5 /**< \brief (EIC_LEVEL) External Interrupt 5 */ 634 #define EIC_LEVEL_INT5 (_U_(0x1) << EIC_LEVEL_INT5_Pos) 635 #define EIC_LEVEL_INT6_Pos 6 /**< \brief (EIC_LEVEL) External Interrupt 6 */ 636 #define EIC_LEVEL_INT6 (_U_(0x1) << EIC_LEVEL_INT6_Pos) 637 #define EIC_LEVEL_INT7_Pos 7 /**< \brief (EIC_LEVEL) External Interrupt 7 */ 638 #define EIC_LEVEL_INT7 (_U_(0x1) << EIC_LEVEL_INT7_Pos) 639 #define EIC_LEVEL_INT8_Pos 8 /**< \brief (EIC_LEVEL) External Interrupt 8 */ 640 #define EIC_LEVEL_INT8 (_U_(0x1) << EIC_LEVEL_INT8_Pos) 641 #define EIC_LEVEL_INT9_Pos 9 /**< \brief (EIC_LEVEL) External Interrupt 9 */ 642 #define EIC_LEVEL_INT9 (_U_(0x1) << EIC_LEVEL_INT9_Pos) 643 #define EIC_LEVEL_INT10_Pos 10 /**< \brief (EIC_LEVEL) External Interrupt 10 */ 644 #define EIC_LEVEL_INT10 (_U_(0x1) << EIC_LEVEL_INT10_Pos) 645 #define EIC_LEVEL_INT11_Pos 11 /**< \brief (EIC_LEVEL) External Interrupt 11 */ 646 #define EIC_LEVEL_INT11 (_U_(0x1) << EIC_LEVEL_INT11_Pos) 647 #define EIC_LEVEL_INT12_Pos 12 /**< \brief (EIC_LEVEL) External Interrupt 12 */ 648 #define EIC_LEVEL_INT12 (_U_(0x1) << EIC_LEVEL_INT12_Pos) 649 #define EIC_LEVEL_INT13_Pos 13 /**< \brief (EIC_LEVEL) External Interrupt 13 */ 650 #define EIC_LEVEL_INT13 (_U_(0x1) << EIC_LEVEL_INT13_Pos) 651 #define EIC_LEVEL_INT14_Pos 14 /**< \brief (EIC_LEVEL) External Interrupt 14 */ 652 #define EIC_LEVEL_INT14 (_U_(0x1) << EIC_LEVEL_INT14_Pos) 653 #define EIC_LEVEL_INT15_Pos 15 /**< \brief (EIC_LEVEL) External Interrupt 15 */ 654 #define EIC_LEVEL_INT15 (_U_(0x1) << EIC_LEVEL_INT15_Pos) 655 #define EIC_LEVEL_MASK _U_(0x0000FFFF) /**< \brief (EIC_LEVEL) MASK Register */ 656 657 /* -------- EIC_FILTER : (EIC Offset: 0x020) (R/W 32) Filter Register -------- */ 658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 659 typedef union { 660 struct { 661 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 662 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 663 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 664 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 665 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 666 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 667 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 668 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 669 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 670 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 671 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 672 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 673 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 674 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 675 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 676 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 677 uint32_t :16; /*!< bit: 16..31 Reserved */ 678 } bit; /*!< Structure used for bit access */ 679 uint32_t reg; /*!< Type used for register access */ 680 } EIC_FILTER_Type; 681 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 682 683 #define EIC_FILTER_OFFSET 0x020 /**< \brief (EIC_FILTER offset) Filter Register */ 684 #define EIC_FILTER_RESETVALUE _U_(0x00000000); /**< \brief (EIC_FILTER reset_value) Filter Register */ 685 686 #define EIC_FILTER_NMI_Pos 0 /**< \brief (EIC_FILTER) External Non Maskable CPU interrupt */ 687 #define EIC_FILTER_NMI (_U_(0x1) << EIC_FILTER_NMI_Pos) 688 #define EIC_FILTER_INT1_Pos 1 /**< \brief (EIC_FILTER) External Interrupt 1 */ 689 #define EIC_FILTER_INT1 (_U_(0x1) << EIC_FILTER_INT1_Pos) 690 #define EIC_FILTER_INT2_Pos 2 /**< \brief (EIC_FILTER) External Interrupt 2 */ 691 #define EIC_FILTER_INT2 (_U_(0x1) << EIC_FILTER_INT2_Pos) 692 #define EIC_FILTER_INT3_Pos 3 /**< \brief (EIC_FILTER) External Interrupt 3 */ 693 #define EIC_FILTER_INT3 (_U_(0x1) << EIC_FILTER_INT3_Pos) 694 #define EIC_FILTER_INT4_Pos 4 /**< \brief (EIC_FILTER) External Interrupt 4 */ 695 #define EIC_FILTER_INT4 (_U_(0x1) << EIC_FILTER_INT4_Pos) 696 #define EIC_FILTER_INT5_Pos 5 /**< \brief (EIC_FILTER) External Interrupt 5 */ 697 #define EIC_FILTER_INT5 (_U_(0x1) << EIC_FILTER_INT5_Pos) 698 #define EIC_FILTER_INT6_Pos 6 /**< \brief (EIC_FILTER) External Interrupt 6 */ 699 #define EIC_FILTER_INT6 (_U_(0x1) << EIC_FILTER_INT6_Pos) 700 #define EIC_FILTER_INT7_Pos 7 /**< \brief (EIC_FILTER) External Interrupt 7 */ 701 #define EIC_FILTER_INT7 (_U_(0x1) << EIC_FILTER_INT7_Pos) 702 #define EIC_FILTER_INT8_Pos 8 /**< \brief (EIC_FILTER) External Interrupt 8 */ 703 #define EIC_FILTER_INT8 (_U_(0x1) << EIC_FILTER_INT8_Pos) 704 #define EIC_FILTER_INT9_Pos 9 /**< \brief (EIC_FILTER) External Interrupt 9 */ 705 #define EIC_FILTER_INT9 (_U_(0x1) << EIC_FILTER_INT9_Pos) 706 #define EIC_FILTER_INT10_Pos 10 /**< \brief (EIC_FILTER) External Interrupt 10 */ 707 #define EIC_FILTER_INT10 (_U_(0x1) << EIC_FILTER_INT10_Pos) 708 #define EIC_FILTER_INT11_Pos 11 /**< \brief (EIC_FILTER) External Interrupt 11 */ 709 #define EIC_FILTER_INT11 (_U_(0x1) << EIC_FILTER_INT11_Pos) 710 #define EIC_FILTER_INT12_Pos 12 /**< \brief (EIC_FILTER) External Interrupt 12 */ 711 #define EIC_FILTER_INT12 (_U_(0x1) << EIC_FILTER_INT12_Pos) 712 #define EIC_FILTER_INT13_Pos 13 /**< \brief (EIC_FILTER) External Interrupt 13 */ 713 #define EIC_FILTER_INT13 (_U_(0x1) << EIC_FILTER_INT13_Pos) 714 #define EIC_FILTER_INT14_Pos 14 /**< \brief (EIC_FILTER) External Interrupt 14 */ 715 #define EIC_FILTER_INT14 (_U_(0x1) << EIC_FILTER_INT14_Pos) 716 #define EIC_FILTER_INT15_Pos 15 /**< \brief (EIC_FILTER) External Interrupt 15 */ 717 #define EIC_FILTER_INT15 (_U_(0x1) << EIC_FILTER_INT15_Pos) 718 #define EIC_FILTER_MASK _U_(0x0000FFFF) /**< \brief (EIC_FILTER) MASK Register */ 719 720 /* -------- EIC_ASYNC : (EIC Offset: 0x028) (R/W 32) Asynchronous Register -------- */ 721 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 722 typedef union { 723 struct { 724 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 725 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 726 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 727 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 728 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 729 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 730 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 731 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 732 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 733 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 734 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 735 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 736 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 737 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 738 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 739 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 740 uint32_t :16; /*!< bit: 16..31 Reserved */ 741 } bit; /*!< Structure used for bit access */ 742 uint32_t reg; /*!< Type used for register access */ 743 } EIC_ASYNC_Type; 744 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 745 746 #define EIC_ASYNC_OFFSET 0x028 /**< \brief (EIC_ASYNC offset) Asynchronous Register */ 747 #define EIC_ASYNC_RESETVALUE _U_(0x00000000); /**< \brief (EIC_ASYNC reset_value) Asynchronous Register */ 748 749 #define EIC_ASYNC_NMI_Pos 0 /**< \brief (EIC_ASYNC) External Non Maskable CPU interrupt */ 750 #define EIC_ASYNC_NMI (_U_(0x1) << EIC_ASYNC_NMI_Pos) 751 #define EIC_ASYNC_INT1_Pos 1 /**< \brief (EIC_ASYNC) External Interrupt 1 */ 752 #define EIC_ASYNC_INT1 (_U_(0x1) << EIC_ASYNC_INT1_Pos) 753 #define EIC_ASYNC_INT2_Pos 2 /**< \brief (EIC_ASYNC) External Interrupt 2 */ 754 #define EIC_ASYNC_INT2 (_U_(0x1) << EIC_ASYNC_INT2_Pos) 755 #define EIC_ASYNC_INT3_Pos 3 /**< \brief (EIC_ASYNC) External Interrupt 3 */ 756 #define EIC_ASYNC_INT3 (_U_(0x1) << EIC_ASYNC_INT3_Pos) 757 #define EIC_ASYNC_INT4_Pos 4 /**< \brief (EIC_ASYNC) External Interrupt 4 */ 758 #define EIC_ASYNC_INT4 (_U_(0x1) << EIC_ASYNC_INT4_Pos) 759 #define EIC_ASYNC_INT5_Pos 5 /**< \brief (EIC_ASYNC) External Interrupt 5 */ 760 #define EIC_ASYNC_INT5 (_U_(0x1) << EIC_ASYNC_INT5_Pos) 761 #define EIC_ASYNC_INT6_Pos 6 /**< \brief (EIC_ASYNC) External Interrupt 6 */ 762 #define EIC_ASYNC_INT6 (_U_(0x1) << EIC_ASYNC_INT6_Pos) 763 #define EIC_ASYNC_INT7_Pos 7 /**< \brief (EIC_ASYNC) External Interrupt 7 */ 764 #define EIC_ASYNC_INT7 (_U_(0x1) << EIC_ASYNC_INT7_Pos) 765 #define EIC_ASYNC_INT8_Pos 8 /**< \brief (EIC_ASYNC) External Interrupt 8 */ 766 #define EIC_ASYNC_INT8 (_U_(0x1) << EIC_ASYNC_INT8_Pos) 767 #define EIC_ASYNC_INT9_Pos 9 /**< \brief (EIC_ASYNC) External Interrupt 9 */ 768 #define EIC_ASYNC_INT9 (_U_(0x1) << EIC_ASYNC_INT9_Pos) 769 #define EIC_ASYNC_INT10_Pos 10 /**< \brief (EIC_ASYNC) External Interrupt 10 */ 770 #define EIC_ASYNC_INT10 (_U_(0x1) << EIC_ASYNC_INT10_Pos) 771 #define EIC_ASYNC_INT11_Pos 11 /**< \brief (EIC_ASYNC) External Interrupt 11 */ 772 #define EIC_ASYNC_INT11 (_U_(0x1) << EIC_ASYNC_INT11_Pos) 773 #define EIC_ASYNC_INT12_Pos 12 /**< \brief (EIC_ASYNC) External Interrupt 12 */ 774 #define EIC_ASYNC_INT12 (_U_(0x1) << EIC_ASYNC_INT12_Pos) 775 #define EIC_ASYNC_INT13_Pos 13 /**< \brief (EIC_ASYNC) External Interrupt 13 */ 776 #define EIC_ASYNC_INT13 (_U_(0x1) << EIC_ASYNC_INT13_Pos) 777 #define EIC_ASYNC_INT14_Pos 14 /**< \brief (EIC_ASYNC) External Interrupt 14 */ 778 #define EIC_ASYNC_INT14 (_U_(0x1) << EIC_ASYNC_INT14_Pos) 779 #define EIC_ASYNC_INT15_Pos 15 /**< \brief (EIC_ASYNC) External Interrupt 15 */ 780 #define EIC_ASYNC_INT15 (_U_(0x1) << EIC_ASYNC_INT15_Pos) 781 #define EIC_ASYNC_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNC) MASK Register */ 782 783 /* -------- EIC_EN : (EIC Offset: 0x030) ( /W 32) Enable Register -------- */ 784 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 785 typedef union { 786 struct { 787 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 788 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 789 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 790 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 791 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 792 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 793 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 794 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 795 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 796 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 797 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 798 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 799 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 800 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 801 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 802 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 803 uint32_t :16; /*!< bit: 16..31 Reserved */ 804 } bit; /*!< Structure used for bit access */ 805 uint32_t reg; /*!< Type used for register access */ 806 } EIC_EN_Type; 807 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 808 809 #define EIC_EN_OFFSET 0x030 /**< \brief (EIC_EN offset) Enable Register */ 810 #define EIC_EN_RESETVALUE _U_(0x00000000); /**< \brief (EIC_EN reset_value) Enable Register */ 811 812 #define EIC_EN_NMI_Pos 0 /**< \brief (EIC_EN) External Non Maskable CPU interrupt */ 813 #define EIC_EN_NMI (_U_(0x1) << EIC_EN_NMI_Pos) 814 #define EIC_EN_INT1_Pos 1 /**< \brief (EIC_EN) External Interrupt 1 */ 815 #define EIC_EN_INT1 (_U_(0x1) << EIC_EN_INT1_Pos) 816 #define EIC_EN_INT2_Pos 2 /**< \brief (EIC_EN) External Interrupt 2 */ 817 #define EIC_EN_INT2 (_U_(0x1) << EIC_EN_INT2_Pos) 818 #define EIC_EN_INT3_Pos 3 /**< \brief (EIC_EN) External Interrupt 3 */ 819 #define EIC_EN_INT3 (_U_(0x1) << EIC_EN_INT3_Pos) 820 #define EIC_EN_INT4_Pos 4 /**< \brief (EIC_EN) External Interrupt 4 */ 821 #define EIC_EN_INT4 (_U_(0x1) << EIC_EN_INT4_Pos) 822 #define EIC_EN_INT5_Pos 5 /**< \brief (EIC_EN) External Interrupt 5 */ 823 #define EIC_EN_INT5 (_U_(0x1) << EIC_EN_INT5_Pos) 824 #define EIC_EN_INT6_Pos 6 /**< \brief (EIC_EN) External Interrupt 6 */ 825 #define EIC_EN_INT6 (_U_(0x1) << EIC_EN_INT6_Pos) 826 #define EIC_EN_INT7_Pos 7 /**< \brief (EIC_EN) External Interrupt 7 */ 827 #define EIC_EN_INT7 (_U_(0x1) << EIC_EN_INT7_Pos) 828 #define EIC_EN_INT8_Pos 8 /**< \brief (EIC_EN) External Interrupt 8 */ 829 #define EIC_EN_INT8 (_U_(0x1) << EIC_EN_INT8_Pos) 830 #define EIC_EN_INT9_Pos 9 /**< \brief (EIC_EN) External Interrupt 9 */ 831 #define EIC_EN_INT9 (_U_(0x1) << EIC_EN_INT9_Pos) 832 #define EIC_EN_INT10_Pos 10 /**< \brief (EIC_EN) External Interrupt 10 */ 833 #define EIC_EN_INT10 (_U_(0x1) << EIC_EN_INT10_Pos) 834 #define EIC_EN_INT11_Pos 11 /**< \brief (EIC_EN) External Interrupt 11 */ 835 #define EIC_EN_INT11 (_U_(0x1) << EIC_EN_INT11_Pos) 836 #define EIC_EN_INT12_Pos 12 /**< \brief (EIC_EN) External Interrupt 12 */ 837 #define EIC_EN_INT12 (_U_(0x1) << EIC_EN_INT12_Pos) 838 #define EIC_EN_INT13_Pos 13 /**< \brief (EIC_EN) External Interrupt 13 */ 839 #define EIC_EN_INT13 (_U_(0x1) << EIC_EN_INT13_Pos) 840 #define EIC_EN_INT14_Pos 14 /**< \brief (EIC_EN) External Interrupt 14 */ 841 #define EIC_EN_INT14 (_U_(0x1) << EIC_EN_INT14_Pos) 842 #define EIC_EN_INT15_Pos 15 /**< \brief (EIC_EN) External Interrupt 15 */ 843 #define EIC_EN_INT15 (_U_(0x1) << EIC_EN_INT15_Pos) 844 #define EIC_EN_MASK _U_(0x0000FFFF) /**< \brief (EIC_EN) MASK Register */ 845 846 /* -------- EIC_DIS : (EIC Offset: 0x034) ( /W 32) Disable Register -------- */ 847 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 848 typedef union { 849 struct { 850 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 851 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 852 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 853 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 854 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 855 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 856 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 857 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 858 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 859 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 860 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 861 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 862 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 863 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 864 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 865 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 866 uint32_t :16; /*!< bit: 16..31 Reserved */ 867 } bit; /*!< Structure used for bit access */ 868 uint32_t reg; /*!< Type used for register access */ 869 } EIC_DIS_Type; 870 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 871 872 #define EIC_DIS_OFFSET 0x034 /**< \brief (EIC_DIS offset) Disable Register */ 873 #define EIC_DIS_RESETVALUE _U_(0x00000000); /**< \brief (EIC_DIS reset_value) Disable Register */ 874 875 #define EIC_DIS_NMI_Pos 0 /**< \brief (EIC_DIS) External Non Maskable CPU interrupt */ 876 #define EIC_DIS_NMI (_U_(0x1) << EIC_DIS_NMI_Pos) 877 #define EIC_DIS_INT1_Pos 1 /**< \brief (EIC_DIS) External Interrupt 1 */ 878 #define EIC_DIS_INT1 (_U_(0x1) << EIC_DIS_INT1_Pos) 879 #define EIC_DIS_INT2_Pos 2 /**< \brief (EIC_DIS) External Interrupt 2 */ 880 #define EIC_DIS_INT2 (_U_(0x1) << EIC_DIS_INT2_Pos) 881 #define EIC_DIS_INT3_Pos 3 /**< \brief (EIC_DIS) External Interrupt 3 */ 882 #define EIC_DIS_INT3 (_U_(0x1) << EIC_DIS_INT3_Pos) 883 #define EIC_DIS_INT4_Pos 4 /**< \brief (EIC_DIS) External Interrupt 4 */ 884 #define EIC_DIS_INT4 (_U_(0x1) << EIC_DIS_INT4_Pos) 885 #define EIC_DIS_INT5_Pos 5 /**< \brief (EIC_DIS) External Interrupt 5 */ 886 #define EIC_DIS_INT5 (_U_(0x1) << EIC_DIS_INT5_Pos) 887 #define EIC_DIS_INT6_Pos 6 /**< \brief (EIC_DIS) External Interrupt 6 */ 888 #define EIC_DIS_INT6 (_U_(0x1) << EIC_DIS_INT6_Pos) 889 #define EIC_DIS_INT7_Pos 7 /**< \brief (EIC_DIS) External Interrupt 7 */ 890 #define EIC_DIS_INT7 (_U_(0x1) << EIC_DIS_INT7_Pos) 891 #define EIC_DIS_INT8_Pos 8 /**< \brief (EIC_DIS) External Interrupt 8 */ 892 #define EIC_DIS_INT8 (_U_(0x1) << EIC_DIS_INT8_Pos) 893 #define EIC_DIS_INT9_Pos 9 /**< \brief (EIC_DIS) External Interrupt 9 */ 894 #define EIC_DIS_INT9 (_U_(0x1) << EIC_DIS_INT9_Pos) 895 #define EIC_DIS_INT10_Pos 10 /**< \brief (EIC_DIS) External Interrupt 10 */ 896 #define EIC_DIS_INT10 (_U_(0x1) << EIC_DIS_INT10_Pos) 897 #define EIC_DIS_INT11_Pos 11 /**< \brief (EIC_DIS) External Interrupt 11 */ 898 #define EIC_DIS_INT11 (_U_(0x1) << EIC_DIS_INT11_Pos) 899 #define EIC_DIS_INT12_Pos 12 /**< \brief (EIC_DIS) External Interrupt 12 */ 900 #define EIC_DIS_INT12 (_U_(0x1) << EIC_DIS_INT12_Pos) 901 #define EIC_DIS_INT13_Pos 13 /**< \brief (EIC_DIS) External Interrupt 13 */ 902 #define EIC_DIS_INT13 (_U_(0x1) << EIC_DIS_INT13_Pos) 903 #define EIC_DIS_INT14_Pos 14 /**< \brief (EIC_DIS) External Interrupt 14 */ 904 #define EIC_DIS_INT14 (_U_(0x1) << EIC_DIS_INT14_Pos) 905 #define EIC_DIS_INT15_Pos 15 /**< \brief (EIC_DIS) External Interrupt 15 */ 906 #define EIC_DIS_INT15 (_U_(0x1) << EIC_DIS_INT15_Pos) 907 #define EIC_DIS_MASK _U_(0x0000FFFF) /**< \brief (EIC_DIS) MASK Register */ 908 909 /* -------- EIC_CTRL : (EIC Offset: 0x038) (R/ 32) Control Register -------- */ 910 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 911 typedef union { 912 struct { 913 uint32_t NMI:1; /*!< bit: 0 External Non Maskable CPU interrupt */ 914 uint32_t INT1:1; /*!< bit: 1 External Interrupt 1 */ 915 uint32_t INT2:1; /*!< bit: 2 External Interrupt 2 */ 916 uint32_t INT3:1; /*!< bit: 3 External Interrupt 3 */ 917 uint32_t INT4:1; /*!< bit: 4 External Interrupt 4 */ 918 uint32_t INT5:1; /*!< bit: 5 External Interrupt 5 */ 919 uint32_t INT6:1; /*!< bit: 6 External Interrupt 6 */ 920 uint32_t INT7:1; /*!< bit: 7 External Interrupt 7 */ 921 uint32_t INT8:1; /*!< bit: 8 External Interrupt 8 */ 922 uint32_t INT9:1; /*!< bit: 9 External Interrupt 9 */ 923 uint32_t INT10:1; /*!< bit: 10 External Interrupt 10 */ 924 uint32_t INT11:1; /*!< bit: 11 External Interrupt 11 */ 925 uint32_t INT12:1; /*!< bit: 12 External Interrupt 12 */ 926 uint32_t INT13:1; /*!< bit: 13 External Interrupt 13 */ 927 uint32_t INT14:1; /*!< bit: 14 External Interrupt 14 */ 928 uint32_t INT15:1; /*!< bit: 15 External Interrupt 15 */ 929 uint32_t :16; /*!< bit: 16..31 Reserved */ 930 } bit; /*!< Structure used for bit access */ 931 uint32_t reg; /*!< Type used for register access */ 932 } EIC_CTRL_Type; 933 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 934 935 #define EIC_CTRL_OFFSET 0x038 /**< \brief (EIC_CTRL offset) Control Register */ 936 #define EIC_CTRL_RESETVALUE _U_(0x00000000); /**< \brief (EIC_CTRL reset_value) Control Register */ 937 938 #define EIC_CTRL_NMI_Pos 0 /**< \brief (EIC_CTRL) External Non Maskable CPU interrupt */ 939 #define EIC_CTRL_NMI (_U_(0x1) << EIC_CTRL_NMI_Pos) 940 #define EIC_CTRL_INT1_Pos 1 /**< \brief (EIC_CTRL) External Interrupt 1 */ 941 #define EIC_CTRL_INT1 (_U_(0x1) << EIC_CTRL_INT1_Pos) 942 #define EIC_CTRL_INT2_Pos 2 /**< \brief (EIC_CTRL) External Interrupt 2 */ 943 #define EIC_CTRL_INT2 (_U_(0x1) << EIC_CTRL_INT2_Pos) 944 #define EIC_CTRL_INT3_Pos 3 /**< \brief (EIC_CTRL) External Interrupt 3 */ 945 #define EIC_CTRL_INT3 (_U_(0x1) << EIC_CTRL_INT3_Pos) 946 #define EIC_CTRL_INT4_Pos 4 /**< \brief (EIC_CTRL) External Interrupt 4 */ 947 #define EIC_CTRL_INT4 (_U_(0x1) << EIC_CTRL_INT4_Pos) 948 #define EIC_CTRL_INT5_Pos 5 /**< \brief (EIC_CTRL) External Interrupt 5 */ 949 #define EIC_CTRL_INT5 (_U_(0x1) << EIC_CTRL_INT5_Pos) 950 #define EIC_CTRL_INT6_Pos 6 /**< \brief (EIC_CTRL) External Interrupt 6 */ 951 #define EIC_CTRL_INT6 (_U_(0x1) << EIC_CTRL_INT6_Pos) 952 #define EIC_CTRL_INT7_Pos 7 /**< \brief (EIC_CTRL) External Interrupt 7 */ 953 #define EIC_CTRL_INT7 (_U_(0x1) << EIC_CTRL_INT7_Pos) 954 #define EIC_CTRL_INT8_Pos 8 /**< \brief (EIC_CTRL) External Interrupt 8 */ 955 #define EIC_CTRL_INT8 (_U_(0x1) << EIC_CTRL_INT8_Pos) 956 #define EIC_CTRL_INT9_Pos 9 /**< \brief (EIC_CTRL) External Interrupt 9 */ 957 #define EIC_CTRL_INT9 (_U_(0x1) << EIC_CTRL_INT9_Pos) 958 #define EIC_CTRL_INT10_Pos 10 /**< \brief (EIC_CTRL) External Interrupt 10 */ 959 #define EIC_CTRL_INT10 (_U_(0x1) << EIC_CTRL_INT10_Pos) 960 #define EIC_CTRL_INT11_Pos 11 /**< \brief (EIC_CTRL) External Interrupt 11 */ 961 #define EIC_CTRL_INT11 (_U_(0x1) << EIC_CTRL_INT11_Pos) 962 #define EIC_CTRL_INT12_Pos 12 /**< \brief (EIC_CTRL) External Interrupt 12 */ 963 #define EIC_CTRL_INT12 (_U_(0x1) << EIC_CTRL_INT12_Pos) 964 #define EIC_CTRL_INT13_Pos 13 /**< \brief (EIC_CTRL) External Interrupt 13 */ 965 #define EIC_CTRL_INT13 (_U_(0x1) << EIC_CTRL_INT13_Pos) 966 #define EIC_CTRL_INT14_Pos 14 /**< \brief (EIC_CTRL) External Interrupt 14 */ 967 #define EIC_CTRL_INT14 (_U_(0x1) << EIC_CTRL_INT14_Pos) 968 #define EIC_CTRL_INT15_Pos 15 /**< \brief (EIC_CTRL) External Interrupt 15 */ 969 #define EIC_CTRL_INT15 (_U_(0x1) << EIC_CTRL_INT15_Pos) 970 #define EIC_CTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_CTRL) MASK Register */ 971 972 /* -------- EIC_VERSION : (EIC Offset: 0x3FC) (R/ 32) Version Register -------- */ 973 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 974 typedef union { 975 struct { 976 uint32_t VERSION:12; /*!< bit: 0..11 Version bits */ 977 uint32_t :20; /*!< bit: 12..31 Reserved */ 978 } bit; /*!< Structure used for bit access */ 979 uint32_t reg; /*!< Type used for register access */ 980 } EIC_VERSION_Type; 981 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 982 983 #define EIC_VERSION_OFFSET 0x3FC /**< \brief (EIC_VERSION offset) Version Register */ 984 #define EIC_VERSION_RESETVALUE _U_(0x00000302); /**< \brief (EIC_VERSION reset_value) Version Register */ 985 986 #define EIC_VERSION_VERSION_Pos 0 /**< \brief (EIC_VERSION) Version bits */ 987 #define EIC_VERSION_VERSION_Msk (_U_(0xFFF) << EIC_VERSION_VERSION_Pos) 988 #define EIC_VERSION_VERSION(value) (EIC_VERSION_VERSION_Msk & ((value) << EIC_VERSION_VERSION_Pos)) 989 #define EIC_VERSION_MASK _U_(0x00000FFF) /**< \brief (EIC_VERSION) MASK Register */ 990 991 /** \brief EIC hardware registers */ 992 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 993 typedef struct { 994 __O uint32_t IER; /**< \brief Offset: 0x000 ( /W 32) Interrupt Enable Register */ 995 __O uint32_t IDR; /**< \brief Offset: 0x004 ( /W 32) Interrupt Disable Register */ 996 __I uint32_t IMR; /**< \brief Offset: 0x008 (R/ 32) Interrupt Mask Register */ 997 __I uint32_t ISR; /**< \brief Offset: 0x00C (R/ 32) Interrupt Status Register */ 998 __O uint32_t ICR; /**< \brief Offset: 0x010 ( /W 32) Interrupt Clear Register */ 999 __IO uint32_t MODE; /**< \brief Offset: 0x014 (R/W 32) Mode Register */ 1000 __IO uint32_t EDGE; /**< \brief Offset: 0x018 (R/W 32) Edge Register */ 1001 __IO uint32_t LEVEL; /**< \brief Offset: 0x01C (R/W 32) Level Register */ 1002 __IO uint32_t FILTER; /**< \brief Offset: 0x020 (R/W 32) Filter Register */ 1003 RoReg8 Reserved1[0x4]; 1004 __IO uint32_t ASYNC; /**< \brief Offset: 0x028 (R/W 32) Asynchronous Register */ 1005 RoReg8 Reserved2[0x4]; 1006 __O uint32_t EN; /**< \brief Offset: 0x030 ( /W 32) Enable Register */ 1007 __O uint32_t DIS; /**< \brief Offset: 0x034 ( /W 32) Disable Register */ 1008 __I uint32_t CTRL; /**< \brief Offset: 0x038 (R/ 32) Control Register */ 1009 RoReg8 Reserved3[0x3C0]; 1010 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) Version Register */ 1011 } Eic; 1012 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1013 1014 /*@}*/ 1015 1016 #endif /* _SAM4L_EIC_COMPONENT_ */ 1017
