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Searched refs:CMCC_SR_CSTS (Results 1 – 6 of 6) sorted by relevance

/hal_atmel-latest/asf/sam/include/sam4e/component/
Dcmcc.h85 #define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */ macro
/hal_atmel-latest/asf/sam/include/sam4s/component/
Dcmcc.h85 #define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */ macro
/hal_atmel-latest/asf/sam0/include/same51/component/
Dcmcc.h186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) macro
/hal_atmel-latest/asf/sam0/include/samd51/component/
Dcmcc.h186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) macro
/hal_atmel-latest/asf/sam0/include/same53/component/
Dcmcc.h186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) macro
/hal_atmel-latest/asf/sam0/include/same54/component/
Dcmcc.h186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) macro