1 /** 2 * \file 3 * 4 * \brief Component description for BSCIF 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_BSCIF_COMPONENT_ 30 #define _SAM4L_BSCIF_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR BSCIF */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_BSCIF Backup System Control Interface */ 36 /*@{*/ 37 38 #define BSCIF_ 39 #define REV_BSCIF 0x100 40 41 /* -------- BSCIF_IER : (BSCIF Offset: 0x000) ( /W 32) Interrupt Enable Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 46 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 47 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 48 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 49 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 50 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 51 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 52 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 53 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 54 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 55 uint32_t VREGOK:1; /*!< bit: 10 Main VREG OK */ 56 uint32_t :1; /*!< bit: 11 Reserved */ 57 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 58 uint32_t :18; /*!< bit: 13..30 Reserved */ 59 uint32_t AE:1; /*!< bit: 31 Access Error */ 60 } bit; /*!< Structure used for bit access */ 61 uint32_t reg; /*!< Type used for register access */ 62 } BSCIF_IER_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define BSCIF_IER_OFFSET 0x000 /**< \brief (BSCIF_IER offset) Interrupt Enable Register */ 66 #define BSCIF_IER_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_IER reset_value) Interrupt Enable Register */ 67 68 #define BSCIF_IER_OSC32RDY_Pos 0 /**< \brief (BSCIF_IER) 32kHz Oscillator Ready */ 69 #define BSCIF_IER_OSC32RDY (_U_(0x1) << BSCIF_IER_OSC32RDY_Pos) 70 #define BSCIF_IER_RC32KRDY_Pos 1 /**< \brief (BSCIF_IER) 32kHz RC Oscillator Ready */ 71 #define BSCIF_IER_RC32KRDY (_U_(0x1) << BSCIF_IER_RC32KRDY_Pos) 72 #define BSCIF_IER_RC32KLOCK_Pos 2 /**< \brief (BSCIF_IER) 32kHz RC Oscillator Lock */ 73 #define BSCIF_IER_RC32KLOCK (_U_(0x1) << BSCIF_IER_RC32KLOCK_Pos) 74 #define BSCIF_IER_RC32KREFE_Pos 3 /**< \brief (BSCIF_IER) 32kHz RC Oscillator Reference Error */ 75 #define BSCIF_IER_RC32KREFE (_U_(0x1) << BSCIF_IER_RC32KREFE_Pos) 76 #define BSCIF_IER_RC32KSAT_Pos 4 /**< \brief (BSCIF_IER) 32kHz RC Oscillator Saturation */ 77 #define BSCIF_IER_RC32KSAT (_U_(0x1) << BSCIF_IER_RC32KSAT_Pos) 78 #define BSCIF_IER_BOD33DET_Pos 5 /**< \brief (BSCIF_IER) BOD33 Detected */ 79 #define BSCIF_IER_BOD33DET (_U_(0x1) << BSCIF_IER_BOD33DET_Pos) 80 #define BSCIF_IER_BOD18DET_Pos 6 /**< \brief (BSCIF_IER) BOD18 Detected */ 81 #define BSCIF_IER_BOD18DET (_U_(0x1) << BSCIF_IER_BOD18DET_Pos) 82 #define BSCIF_IER_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_IER) BOD33 Synchronization Ready */ 83 #define BSCIF_IER_BOD33SYNRDY (_U_(0x1) << BSCIF_IER_BOD33SYNRDY_Pos) 84 #define BSCIF_IER_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_IER) BOD18 Synchronization Ready */ 85 #define BSCIF_IER_BOD18SYNRDY (_U_(0x1) << BSCIF_IER_BOD18SYNRDY_Pos) 86 #define BSCIF_IER_SSWRDY_Pos 9 /**< \brief (BSCIF_IER) VREG Stop Switching Ready */ 87 #define BSCIF_IER_SSWRDY (_U_(0x1) << BSCIF_IER_SSWRDY_Pos) 88 #define BSCIF_IER_VREGOK_Pos 10 /**< \brief (BSCIF_IER) Main VREG OK */ 89 #define BSCIF_IER_VREGOK (_U_(0x1) << BSCIF_IER_VREGOK_Pos) 90 #define BSCIF_IER_LPBGRDY_Pos 12 /**< \brief (BSCIF_IER) Low Power Bandgap Voltage Reference Ready */ 91 #define BSCIF_IER_LPBGRDY (_U_(0x1) << BSCIF_IER_LPBGRDY_Pos) 92 #define BSCIF_IER_AE_Pos 31 /**< \brief (BSCIF_IER) Access Error */ 93 #define BSCIF_IER_AE (_U_(0x1) << BSCIF_IER_AE_Pos) 94 #define BSCIF_IER_MASK _U_(0x800017FF) /**< \brief (BSCIF_IER) MASK Register */ 95 96 /* -------- BSCIF_IDR : (BSCIF Offset: 0x004) ( /W 32) Interrupt Disable Register -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 101 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 102 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 103 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 104 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 105 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 106 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 107 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 108 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 109 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 110 uint32_t VREGOK:1; /*!< bit: 10 Mai n VREG OK */ 111 uint32_t :1; /*!< bit: 11 Reserved */ 112 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 113 uint32_t :18; /*!< bit: 13..30 Reserved */ 114 uint32_t AE:1; /*!< bit: 31 Access Error */ 115 } bit; /*!< Structure used for bit access */ 116 uint32_t reg; /*!< Type used for register access */ 117 } BSCIF_IDR_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define BSCIF_IDR_OFFSET 0x004 /**< \brief (BSCIF_IDR offset) Interrupt Disable Register */ 121 #define BSCIF_IDR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_IDR reset_value) Interrupt Disable Register */ 122 123 #define BSCIF_IDR_OSC32RDY_Pos 0 /**< \brief (BSCIF_IDR) 32kHz Oscillator Ready */ 124 #define BSCIF_IDR_OSC32RDY (_U_(0x1) << BSCIF_IDR_OSC32RDY_Pos) 125 #define BSCIF_IDR_RC32KRDY_Pos 1 /**< \brief (BSCIF_IDR) 32kHz RC Oscillator Ready */ 126 #define BSCIF_IDR_RC32KRDY (_U_(0x1) << BSCIF_IDR_RC32KRDY_Pos) 127 #define BSCIF_IDR_RC32KLOCK_Pos 2 /**< \brief (BSCIF_IDR) 32kHz RC Oscillator Lock */ 128 #define BSCIF_IDR_RC32KLOCK (_U_(0x1) << BSCIF_IDR_RC32KLOCK_Pos) 129 #define BSCIF_IDR_RC32KREFE_Pos 3 /**< \brief (BSCIF_IDR) 32kHz RC Oscillator Reference Error */ 130 #define BSCIF_IDR_RC32KREFE (_U_(0x1) << BSCIF_IDR_RC32KREFE_Pos) 131 #define BSCIF_IDR_RC32KSAT_Pos 4 /**< \brief (BSCIF_IDR) 32kHz RC Oscillator Saturation */ 132 #define BSCIF_IDR_RC32KSAT (_U_(0x1) << BSCIF_IDR_RC32KSAT_Pos) 133 #define BSCIF_IDR_BOD33DET_Pos 5 /**< \brief (BSCIF_IDR) BOD33 Detected */ 134 #define BSCIF_IDR_BOD33DET (_U_(0x1) << BSCIF_IDR_BOD33DET_Pos) 135 #define BSCIF_IDR_BOD18DET_Pos 6 /**< \brief (BSCIF_IDR) BOD18 Detected */ 136 #define BSCIF_IDR_BOD18DET (_U_(0x1) << BSCIF_IDR_BOD18DET_Pos) 137 #define BSCIF_IDR_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_IDR) BOD33 Synchronization Ready */ 138 #define BSCIF_IDR_BOD33SYNRDY (_U_(0x1) << BSCIF_IDR_BOD33SYNRDY_Pos) 139 #define BSCIF_IDR_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_IDR) BOD18 Synchronization Ready */ 140 #define BSCIF_IDR_BOD18SYNRDY (_U_(0x1) << BSCIF_IDR_BOD18SYNRDY_Pos) 141 #define BSCIF_IDR_SSWRDY_Pos 9 /**< \brief (BSCIF_IDR) VREG Stop Switching Ready */ 142 #define BSCIF_IDR_SSWRDY (_U_(0x1) << BSCIF_IDR_SSWRDY_Pos) 143 #define BSCIF_IDR_VREGOK_Pos 10 /**< \brief (BSCIF_IDR) Mai n VREG OK */ 144 #define BSCIF_IDR_VREGOK (_U_(0x1) << BSCIF_IDR_VREGOK_Pos) 145 #define BSCIF_IDR_LPBGRDY_Pos 12 /**< \brief (BSCIF_IDR) Low Power Bandgap Voltage Reference Ready */ 146 #define BSCIF_IDR_LPBGRDY (_U_(0x1) << BSCIF_IDR_LPBGRDY_Pos) 147 #define BSCIF_IDR_AE_Pos 31 /**< \brief (BSCIF_IDR) Access Error */ 148 #define BSCIF_IDR_AE (_U_(0x1) << BSCIF_IDR_AE_Pos) 149 #define BSCIF_IDR_MASK _U_(0x800017FF) /**< \brief (BSCIF_IDR) MASK Register */ 150 151 /* -------- BSCIF_IMR : (BSCIF Offset: 0x008) (R/ 32) Interrupt Mask Register -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 156 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 157 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 158 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 159 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 160 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 161 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 162 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 163 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 164 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 165 uint32_t VREGOK:1; /*!< bit: 10 Main VREG OK */ 166 uint32_t :1; /*!< bit: 11 Reserved */ 167 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 168 uint32_t :18; /*!< bit: 13..30 Reserved */ 169 uint32_t AE:1; /*!< bit: 31 Access Error */ 170 } bit; /*!< Structure used for bit access */ 171 uint32_t reg; /*!< Type used for register access */ 172 } BSCIF_IMR_Type; 173 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 174 175 #define BSCIF_IMR_OFFSET 0x008 /**< \brief (BSCIF_IMR offset) Interrupt Mask Register */ 176 #define BSCIF_IMR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_IMR reset_value) Interrupt Mask Register */ 177 178 #define BSCIF_IMR_OSC32RDY_Pos 0 /**< \brief (BSCIF_IMR) 32kHz Oscillator Ready */ 179 #define BSCIF_IMR_OSC32RDY (_U_(0x1) << BSCIF_IMR_OSC32RDY_Pos) 180 #define BSCIF_IMR_RC32KRDY_Pos 1 /**< \brief (BSCIF_IMR) 32kHz RC Oscillator Ready */ 181 #define BSCIF_IMR_RC32KRDY (_U_(0x1) << BSCIF_IMR_RC32KRDY_Pos) 182 #define BSCIF_IMR_RC32KLOCK_Pos 2 /**< \brief (BSCIF_IMR) 32kHz RC Oscillator Lock */ 183 #define BSCIF_IMR_RC32KLOCK (_U_(0x1) << BSCIF_IMR_RC32KLOCK_Pos) 184 #define BSCIF_IMR_RC32KREFE_Pos 3 /**< \brief (BSCIF_IMR) 32kHz RC Oscillator Reference Error */ 185 #define BSCIF_IMR_RC32KREFE (_U_(0x1) << BSCIF_IMR_RC32KREFE_Pos) 186 #define BSCIF_IMR_RC32KSAT_Pos 4 /**< \brief (BSCIF_IMR) 32kHz RC Oscillator Saturation */ 187 #define BSCIF_IMR_RC32KSAT (_U_(0x1) << BSCIF_IMR_RC32KSAT_Pos) 188 #define BSCIF_IMR_BOD33DET_Pos 5 /**< \brief (BSCIF_IMR) BOD33 Detected */ 189 #define BSCIF_IMR_BOD33DET (_U_(0x1) << BSCIF_IMR_BOD33DET_Pos) 190 #define BSCIF_IMR_BOD18DET_Pos 6 /**< \brief (BSCIF_IMR) BOD18 Detected */ 191 #define BSCIF_IMR_BOD18DET (_U_(0x1) << BSCIF_IMR_BOD18DET_Pos) 192 #define BSCIF_IMR_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_IMR) BOD33 Synchronization Ready */ 193 #define BSCIF_IMR_BOD33SYNRDY (_U_(0x1) << BSCIF_IMR_BOD33SYNRDY_Pos) 194 #define BSCIF_IMR_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_IMR) BOD18 Synchronization Ready */ 195 #define BSCIF_IMR_BOD18SYNRDY (_U_(0x1) << BSCIF_IMR_BOD18SYNRDY_Pos) 196 #define BSCIF_IMR_SSWRDY_Pos 9 /**< \brief (BSCIF_IMR) VREG Stop Switching Ready */ 197 #define BSCIF_IMR_SSWRDY (_U_(0x1) << BSCIF_IMR_SSWRDY_Pos) 198 #define BSCIF_IMR_VREGOK_Pos 10 /**< \brief (BSCIF_IMR) Main VREG OK */ 199 #define BSCIF_IMR_VREGOK (_U_(0x1) << BSCIF_IMR_VREGOK_Pos) 200 #define BSCIF_IMR_LPBGRDY_Pos 12 /**< \brief (BSCIF_IMR) Low Power Bandgap Voltage Reference Ready */ 201 #define BSCIF_IMR_LPBGRDY (_U_(0x1) << BSCIF_IMR_LPBGRDY_Pos) 202 #define BSCIF_IMR_AE_Pos 31 /**< \brief (BSCIF_IMR) Access Error */ 203 #define BSCIF_IMR_AE (_U_(0x1) << BSCIF_IMR_AE_Pos) 204 #define BSCIF_IMR_MASK _U_(0x800017FF) /**< \brief (BSCIF_IMR) MASK Register */ 205 206 /* -------- BSCIF_ISR : (BSCIF Offset: 0x00C) (R/ 32) Interrupt Status Register -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 211 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 212 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 213 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 214 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 215 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 216 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 217 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 218 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 219 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 220 uint32_t VREGOK:1; /*!< bit: 10 Main VREG OK */ 221 uint32_t :1; /*!< bit: 11 Reserved */ 222 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 223 uint32_t :18; /*!< bit: 13..30 Reserved */ 224 uint32_t AE:1; /*!< bit: 31 Access Error */ 225 } bit; /*!< Structure used for bit access */ 226 uint32_t reg; /*!< Type used for register access */ 227 } BSCIF_ISR_Type; 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define BSCIF_ISR_OFFSET 0x00C /**< \brief (BSCIF_ISR offset) Interrupt Status Register */ 231 #define BSCIF_ISR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_ISR reset_value) Interrupt Status Register */ 232 233 #define BSCIF_ISR_OSC32RDY_Pos 0 /**< \brief (BSCIF_ISR) 32kHz Oscillator Ready */ 234 #define BSCIF_ISR_OSC32RDY (_U_(0x1) << BSCIF_ISR_OSC32RDY_Pos) 235 #define BSCIF_ISR_RC32KRDY_Pos 1 /**< \brief (BSCIF_ISR) 32kHz RC Oscillator Ready */ 236 #define BSCIF_ISR_RC32KRDY (_U_(0x1) << BSCIF_ISR_RC32KRDY_Pos) 237 #define BSCIF_ISR_RC32KLOCK_Pos 2 /**< \brief (BSCIF_ISR) 32kHz RC Oscillator Lock */ 238 #define BSCIF_ISR_RC32KLOCK (_U_(0x1) << BSCIF_ISR_RC32KLOCK_Pos) 239 #define BSCIF_ISR_RC32KREFE_Pos 3 /**< \brief (BSCIF_ISR) 32kHz RC Oscillator Reference Error */ 240 #define BSCIF_ISR_RC32KREFE (_U_(0x1) << BSCIF_ISR_RC32KREFE_Pos) 241 #define BSCIF_ISR_RC32KSAT_Pos 4 /**< \brief (BSCIF_ISR) 32kHz RC Oscillator Saturation */ 242 #define BSCIF_ISR_RC32KSAT (_U_(0x1) << BSCIF_ISR_RC32KSAT_Pos) 243 #define BSCIF_ISR_BOD33DET_Pos 5 /**< \brief (BSCIF_ISR) BOD33 Detected */ 244 #define BSCIF_ISR_BOD33DET (_U_(0x1) << BSCIF_ISR_BOD33DET_Pos) 245 #define BSCIF_ISR_BOD18DET_Pos 6 /**< \brief (BSCIF_ISR) BOD18 Detected */ 246 #define BSCIF_ISR_BOD18DET (_U_(0x1) << BSCIF_ISR_BOD18DET_Pos) 247 #define BSCIF_ISR_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_ISR) BOD33 Synchronization Ready */ 248 #define BSCIF_ISR_BOD33SYNRDY (_U_(0x1) << BSCIF_ISR_BOD33SYNRDY_Pos) 249 #define BSCIF_ISR_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_ISR) BOD18 Synchronization Ready */ 250 #define BSCIF_ISR_BOD18SYNRDY (_U_(0x1) << BSCIF_ISR_BOD18SYNRDY_Pos) 251 #define BSCIF_ISR_SSWRDY_Pos 9 /**< \brief (BSCIF_ISR) VREG Stop Switching Ready */ 252 #define BSCIF_ISR_SSWRDY (_U_(0x1) << BSCIF_ISR_SSWRDY_Pos) 253 #define BSCIF_ISR_VREGOK_Pos 10 /**< \brief (BSCIF_ISR) Main VREG OK */ 254 #define BSCIF_ISR_VREGOK (_U_(0x1) << BSCIF_ISR_VREGOK_Pos) 255 #define BSCIF_ISR_LPBGRDY_Pos 12 /**< \brief (BSCIF_ISR) Low Power Bandgap Voltage Reference Ready */ 256 #define BSCIF_ISR_LPBGRDY (_U_(0x1) << BSCIF_ISR_LPBGRDY_Pos) 257 #define BSCIF_ISR_AE_Pos 31 /**< \brief (BSCIF_ISR) Access Error */ 258 #define BSCIF_ISR_AE (_U_(0x1) << BSCIF_ISR_AE_Pos) 259 #define BSCIF_ISR_MASK _U_(0x800017FF) /**< \brief (BSCIF_ISR) MASK Register */ 260 261 /* -------- BSCIF_ICR : (BSCIF Offset: 0x010) ( /W 32) Interrupt Clear Register -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 266 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 267 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 268 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 269 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 270 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 271 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 272 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 273 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 274 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 275 uint32_t VREGOK:1; /*!< bit: 10 Main VREG OK */ 276 uint32_t :1; /*!< bit: 11 Reserved */ 277 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 278 uint32_t :18; /*!< bit: 13..30 Reserved */ 279 uint32_t AE:1; /*!< bit: 31 Access Error */ 280 } bit; /*!< Structure used for bit access */ 281 uint32_t reg; /*!< Type used for register access */ 282 } BSCIF_ICR_Type; 283 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 284 285 #define BSCIF_ICR_OFFSET 0x010 /**< \brief (BSCIF_ICR offset) Interrupt Clear Register */ 286 #define BSCIF_ICR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_ICR reset_value) Interrupt Clear Register */ 287 288 #define BSCIF_ICR_OSC32RDY_Pos 0 /**< \brief (BSCIF_ICR) 32kHz Oscillator Ready */ 289 #define BSCIF_ICR_OSC32RDY (_U_(0x1) << BSCIF_ICR_OSC32RDY_Pos) 290 #define BSCIF_ICR_RC32KRDY_Pos 1 /**< \brief (BSCIF_ICR) 32kHz RC Oscillator Ready */ 291 #define BSCIF_ICR_RC32KRDY (_U_(0x1) << BSCIF_ICR_RC32KRDY_Pos) 292 #define BSCIF_ICR_RC32KLOCK_Pos 2 /**< \brief (BSCIF_ICR) 32kHz RC Oscillator Lock */ 293 #define BSCIF_ICR_RC32KLOCK (_U_(0x1) << BSCIF_ICR_RC32KLOCK_Pos) 294 #define BSCIF_ICR_RC32KREFE_Pos 3 /**< \brief (BSCIF_ICR) 32kHz RC Oscillator Reference Error */ 295 #define BSCIF_ICR_RC32KREFE (_U_(0x1) << BSCIF_ICR_RC32KREFE_Pos) 296 #define BSCIF_ICR_RC32KSAT_Pos 4 /**< \brief (BSCIF_ICR) 32kHz RC Oscillator Saturation */ 297 #define BSCIF_ICR_RC32KSAT (_U_(0x1) << BSCIF_ICR_RC32KSAT_Pos) 298 #define BSCIF_ICR_BOD33DET_Pos 5 /**< \brief (BSCIF_ICR) BOD33 Detected */ 299 #define BSCIF_ICR_BOD33DET (_U_(0x1) << BSCIF_ICR_BOD33DET_Pos) 300 #define BSCIF_ICR_BOD18DET_Pos 6 /**< \brief (BSCIF_ICR) BOD18 Detected */ 301 #define BSCIF_ICR_BOD18DET (_U_(0x1) << BSCIF_ICR_BOD18DET_Pos) 302 #define BSCIF_ICR_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_ICR) BOD33 Synchronization Ready */ 303 #define BSCIF_ICR_BOD33SYNRDY (_U_(0x1) << BSCIF_ICR_BOD33SYNRDY_Pos) 304 #define BSCIF_ICR_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_ICR) BOD18 Synchronization Ready */ 305 #define BSCIF_ICR_BOD18SYNRDY (_U_(0x1) << BSCIF_ICR_BOD18SYNRDY_Pos) 306 #define BSCIF_ICR_SSWRDY_Pos 9 /**< \brief (BSCIF_ICR) VREG Stop Switching Ready */ 307 #define BSCIF_ICR_SSWRDY (_U_(0x1) << BSCIF_ICR_SSWRDY_Pos) 308 #define BSCIF_ICR_VREGOK_Pos 10 /**< \brief (BSCIF_ICR) Main VREG OK */ 309 #define BSCIF_ICR_VREGOK (_U_(0x1) << BSCIF_ICR_VREGOK_Pos) 310 #define BSCIF_ICR_LPBGRDY_Pos 12 /**< \brief (BSCIF_ICR) Low Power Bandgap Voltage Reference Ready */ 311 #define BSCIF_ICR_LPBGRDY (_U_(0x1) << BSCIF_ICR_LPBGRDY_Pos) 312 #define BSCIF_ICR_AE_Pos 31 /**< \brief (BSCIF_ICR) Access Error */ 313 #define BSCIF_ICR_AE (_U_(0x1) << BSCIF_ICR_AE_Pos) 314 #define BSCIF_ICR_MASK _U_(0x800017FF) /**< \brief (BSCIF_ICR) MASK Register */ 315 316 /* -------- BSCIF_PCLKSR : (BSCIF Offset: 0x014) (R/ 32) Power and Clocks Status Register -------- */ 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 318 typedef union { 319 struct { 320 uint32_t OSC32RDY:1; /*!< bit: 0 32kHz Oscillator Ready */ 321 uint32_t RC32KRDY:1; /*!< bit: 1 32kHz RC Oscillator Ready */ 322 uint32_t RC32KLOCK:1; /*!< bit: 2 32kHz RC Oscillator Lock */ 323 uint32_t RC32KREFE:1; /*!< bit: 3 32kHz RC Oscillator Reference Error */ 324 uint32_t RC32KSAT:1; /*!< bit: 4 32kHz RC Oscillator Saturation */ 325 uint32_t BOD33DET:1; /*!< bit: 5 BOD33 Detected */ 326 uint32_t BOD18DET:1; /*!< bit: 6 BOD18 Detected */ 327 uint32_t BOD33SYNRDY:1; /*!< bit: 7 BOD33 Synchronization Ready */ 328 uint32_t BOD18SYNRDY:1; /*!< bit: 8 BOD18 Synchronization Ready */ 329 uint32_t SSWRDY:1; /*!< bit: 9 VREG Stop Switching Ready */ 330 uint32_t VREGOK:1; /*!< bit: 10 Main VREG OK */ 331 uint32_t RC1MRDY:1; /*!< bit: 11 RC 1MHz Oscillator Ready */ 332 uint32_t LPBGRDY:1; /*!< bit: 12 Low Power Bandgap Voltage Reference Ready */ 333 uint32_t :19; /*!< bit: 13..31 Reserved */ 334 } bit; /*!< Structure used for bit access */ 335 uint32_t reg; /*!< Type used for register access */ 336 } BSCIF_PCLKSR_Type; 337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 #define BSCIF_PCLKSR_OFFSET 0x014 /**< \brief (BSCIF_PCLKSR offset) Power and Clocks Status Register */ 340 #define BSCIF_PCLKSR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_PCLKSR reset_value) Power and Clocks Status Register */ 341 342 #define BSCIF_PCLKSR_OSC32RDY_Pos 0 /**< \brief (BSCIF_PCLKSR) 32kHz Oscillator Ready */ 343 #define BSCIF_PCLKSR_OSC32RDY (_U_(0x1) << BSCIF_PCLKSR_OSC32RDY_Pos) 344 #define BSCIF_PCLKSR_RC32KRDY_Pos 1 /**< \brief (BSCIF_PCLKSR) 32kHz RC Oscillator Ready */ 345 #define BSCIF_PCLKSR_RC32KRDY (_U_(0x1) << BSCIF_PCLKSR_RC32KRDY_Pos) 346 #define BSCIF_PCLKSR_RC32KLOCK_Pos 2 /**< \brief (BSCIF_PCLKSR) 32kHz RC Oscillator Lock */ 347 #define BSCIF_PCLKSR_RC32KLOCK (_U_(0x1) << BSCIF_PCLKSR_RC32KLOCK_Pos) 348 #define BSCIF_PCLKSR_RC32KREFE_Pos 3 /**< \brief (BSCIF_PCLKSR) 32kHz RC Oscillator Reference Error */ 349 #define BSCIF_PCLKSR_RC32KREFE (_U_(0x1) << BSCIF_PCLKSR_RC32KREFE_Pos) 350 #define BSCIF_PCLKSR_RC32KSAT_Pos 4 /**< \brief (BSCIF_PCLKSR) 32kHz RC Oscillator Saturation */ 351 #define BSCIF_PCLKSR_RC32KSAT (_U_(0x1) << BSCIF_PCLKSR_RC32KSAT_Pos) 352 #define BSCIF_PCLKSR_BOD33DET_Pos 5 /**< \brief (BSCIF_PCLKSR) BOD33 Detected */ 353 #define BSCIF_PCLKSR_BOD33DET (_U_(0x1) << BSCIF_PCLKSR_BOD33DET_Pos) 354 #define BSCIF_PCLKSR_BOD18DET_Pos 6 /**< \brief (BSCIF_PCLKSR) BOD18 Detected */ 355 #define BSCIF_PCLKSR_BOD18DET (_U_(0x1) << BSCIF_PCLKSR_BOD18DET_Pos) 356 #define BSCIF_PCLKSR_BOD33SYNRDY_Pos 7 /**< \brief (BSCIF_PCLKSR) BOD33 Synchronization Ready */ 357 #define BSCIF_PCLKSR_BOD33SYNRDY (_U_(0x1) << BSCIF_PCLKSR_BOD33SYNRDY_Pos) 358 #define BSCIF_PCLKSR_BOD18SYNRDY_Pos 8 /**< \brief (BSCIF_PCLKSR) BOD18 Synchronization Ready */ 359 #define BSCIF_PCLKSR_BOD18SYNRDY (_U_(0x1) << BSCIF_PCLKSR_BOD18SYNRDY_Pos) 360 #define BSCIF_PCLKSR_SSWRDY_Pos 9 /**< \brief (BSCIF_PCLKSR) VREG Stop Switching Ready */ 361 #define BSCIF_PCLKSR_SSWRDY (_U_(0x1) << BSCIF_PCLKSR_SSWRDY_Pos) 362 #define BSCIF_PCLKSR_VREGOK_Pos 10 /**< \brief (BSCIF_PCLKSR) Main VREG OK */ 363 #define BSCIF_PCLKSR_VREGOK (_U_(0x1) << BSCIF_PCLKSR_VREGOK_Pos) 364 #define BSCIF_PCLKSR_RC1MRDY_Pos 11 /**< \brief (BSCIF_PCLKSR) RC 1MHz Oscillator Ready */ 365 #define BSCIF_PCLKSR_RC1MRDY (_U_(0x1) << BSCIF_PCLKSR_RC1MRDY_Pos) 366 #define BSCIF_PCLKSR_LPBGRDY_Pos 12 /**< \brief (BSCIF_PCLKSR) Low Power Bandgap Voltage Reference Ready */ 367 #define BSCIF_PCLKSR_LPBGRDY (_U_(0x1) << BSCIF_PCLKSR_LPBGRDY_Pos) 368 #define BSCIF_PCLKSR_MASK _U_(0x00001FFF) /**< \brief (BSCIF_PCLKSR) MASK Register */ 369 370 /* -------- BSCIF_UNLOCK : (BSCIF Offset: 0x018) ( /W 32) Unlock Register -------- */ 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 372 typedef union { 373 struct { 374 uint32_t ADDR:10; /*!< bit: 0.. 9 Unlock Address */ 375 uint32_t :14; /*!< bit: 10..23 Reserved */ 376 uint32_t KEY:8; /*!< bit: 24..31 Unlock Key */ 377 } bit; /*!< Structure used for bit access */ 378 uint32_t reg; /*!< Type used for register access */ 379 } BSCIF_UNLOCK_Type; 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define BSCIF_UNLOCK_OFFSET 0x018 /**< \brief (BSCIF_UNLOCK offset) Unlock Register */ 383 #define BSCIF_UNLOCK_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_UNLOCK reset_value) Unlock Register */ 384 385 #define BSCIF_UNLOCK_ADDR_Pos 0 /**< \brief (BSCIF_UNLOCK) Unlock Address */ 386 #define BSCIF_UNLOCK_ADDR_Msk (_U_(0x3FF) << BSCIF_UNLOCK_ADDR_Pos) 387 #define BSCIF_UNLOCK_ADDR(value) (BSCIF_UNLOCK_ADDR_Msk & ((value) << BSCIF_UNLOCK_ADDR_Pos)) 388 #define BSCIF_UNLOCK_KEY_Pos 24 /**< \brief (BSCIF_UNLOCK) Unlock Key */ 389 #define BSCIF_UNLOCK_KEY_Msk (_U_(0xFF) << BSCIF_UNLOCK_KEY_Pos) 390 #define BSCIF_UNLOCK_KEY(value) (BSCIF_UNLOCK_KEY_Msk & ((value) << BSCIF_UNLOCK_KEY_Pos)) 391 #define BSCIF_UNLOCK_KEY_VALID_Val _U_(0xAA) /**< \brief (BSCIF_UNLOCK) Valid Key to Unlock register */ 392 #define BSCIF_UNLOCK_KEY_VALID (BSCIF_UNLOCK_KEY_VALID_Val << BSCIF_UNLOCK_KEY_Pos) 393 #define BSCIF_UNLOCK_MASK _U_(0xFF0003FF) /**< \brief (BSCIF_UNLOCK) MASK Register */ 394 395 /* -------- BSCIF_CSCR : (BSCIF Offset: 0x01C) (R/W 32) Chip Specific Configuration Register -------- */ 396 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 397 typedef union { 398 uint32_t reg; /*!< Type used for register access */ 399 } BSCIF_CSCR_Type; 400 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 401 402 #define BSCIF_CSCR_OFFSET 0x01C /**< \brief (BSCIF_CSCR offset) Chip Specific Configuration Register */ 403 #define BSCIF_CSCR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_CSCR reset_value) Chip Specific Configuration Register */ 404 405 #define BSCIF_CSCR_MASK _U_(0x00000000) /**< \brief (BSCIF_CSCR) MASK Register */ 406 407 /* -------- BSCIF_OSCCTRL32 : (BSCIF Offset: 0x020) (R/W 32) Oscillator 32 Control Register -------- */ 408 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 409 typedef union { 410 struct { 411 uint32_t OSC32EN:1; /*!< bit: 0 32 KHz Oscillator Enable */ 412 uint32_t PINSEL:1; /*!< bit: 1 Pins Select */ 413 uint32_t EN32K:1; /*!< bit: 2 32 KHz output Enable */ 414 uint32_t EN1K:1; /*!< bit: 3 1 KHz output Enable */ 415 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 416 uint32_t MODE:3; /*!< bit: 8..10 Oscillator Mode */ 417 uint32_t :1; /*!< bit: 11 Reserved */ 418 uint32_t SELCURR:4; /*!< bit: 12..15 Current selection */ 419 uint32_t STARTUP:3; /*!< bit: 16..18 Oscillator Start-up Time */ 420 uint32_t :13; /*!< bit: 19..31 Reserved */ 421 } bit; /*!< Structure used for bit access */ 422 uint32_t reg; /*!< Type used for register access */ 423 } BSCIF_OSCCTRL32_Type; 424 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 425 426 #define BSCIF_OSCCTRL32_OFFSET 0x020 /**< \brief (BSCIF_OSCCTRL32 offset) Oscillator 32 Control Register */ 427 #define BSCIF_OSCCTRL32_RESETVALUE _U_(0x00000004); /**< \brief (BSCIF_OSCCTRL32 reset_value) Oscillator 32 Control Register */ 428 429 #define BSCIF_OSCCTRL32_OSC32EN_Pos 0 /**< \brief (BSCIF_OSCCTRL32) 32 KHz Oscillator Enable */ 430 #define BSCIF_OSCCTRL32_OSC32EN (_U_(0x1) << BSCIF_OSCCTRL32_OSC32EN_Pos) 431 #define BSCIF_OSCCTRL32_PINSEL_Pos 1 /**< \brief (BSCIF_OSCCTRL32) Pins Select */ 432 #define BSCIF_OSCCTRL32_PINSEL (_U_(0x1) << BSCIF_OSCCTRL32_PINSEL_Pos) 433 #define BSCIF_OSCCTRL32_EN32K_Pos 2 /**< \brief (BSCIF_OSCCTRL32) 32 KHz output Enable */ 434 #define BSCIF_OSCCTRL32_EN32K (_U_(0x1) << BSCIF_OSCCTRL32_EN32K_Pos) 435 #define BSCIF_OSCCTRL32_EN1K_Pos 3 /**< \brief (BSCIF_OSCCTRL32) 1 KHz output Enable */ 436 #define BSCIF_OSCCTRL32_EN1K (_U_(0x1) << BSCIF_OSCCTRL32_EN1K_Pos) 437 #define BSCIF_OSCCTRL32_MODE_Pos 8 /**< \brief (BSCIF_OSCCTRL32) Oscillator Mode */ 438 #define BSCIF_OSCCTRL32_MODE_Msk (_U_(0x7) << BSCIF_OSCCTRL32_MODE_Pos) 439 #define BSCIF_OSCCTRL32_MODE(value) (BSCIF_OSCCTRL32_MODE_Msk & ((value) << BSCIF_OSCCTRL32_MODE_Pos)) 440 #define BSCIF_OSCCTRL32_SELCURR_Pos 12 /**< \brief (BSCIF_OSCCTRL32) Current selection */ 441 #define BSCIF_OSCCTRL32_SELCURR_Msk (_U_(0xF) << BSCIF_OSCCTRL32_SELCURR_Pos) 442 #define BSCIF_OSCCTRL32_SELCURR(value) (BSCIF_OSCCTRL32_SELCURR_Msk & ((value) << BSCIF_OSCCTRL32_SELCURR_Pos)) 443 #define BSCIF_OSCCTRL32_STARTUP_Pos 16 /**< \brief (BSCIF_OSCCTRL32) Oscillator Start-up Time */ 444 #define BSCIF_OSCCTRL32_STARTUP_Msk (_U_(0x7) << BSCIF_OSCCTRL32_STARTUP_Pos) 445 #define BSCIF_OSCCTRL32_STARTUP(value) (BSCIF_OSCCTRL32_STARTUP_Msk & ((value) << BSCIF_OSCCTRL32_STARTUP_Pos)) 446 #define BSCIF_OSCCTRL32_MASK _U_(0x0007F70F) /**< \brief (BSCIF_OSCCTRL32) MASK Register */ 447 448 /* -------- BSCIF_RC32KCR : (BSCIF Offset: 0x024) (R/W 32) 32 kHz RC Oscillator Control Register -------- */ 449 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 450 typedef union { 451 struct { 452 uint32_t EN:1; /*!< bit: 0 Enable as Generic clock source */ 453 uint32_t TCEN:1; /*!< bit: 1 Temperature Compensation Enable */ 454 uint32_t EN32K:1; /*!< bit: 2 Enable 32 KHz output */ 455 uint32_t EN1K:1; /*!< bit: 3 Enable 1 kHz output */ 456 uint32_t MODE:1; /*!< bit: 4 Mode Selection */ 457 uint32_t REF:1; /*!< bit: 5 Reference select */ 458 uint32_t :1; /*!< bit: 6 Reserved */ 459 uint32_t FCD:1; /*!< bit: 7 Flash calibration done */ 460 uint32_t :24; /*!< bit: 8..31 Reserved */ 461 } bit; /*!< Structure used for bit access */ 462 uint32_t reg; /*!< Type used for register access */ 463 } BSCIF_RC32KCR_Type; 464 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 465 466 #define BSCIF_RC32KCR_OFFSET 0x024 /**< \brief (BSCIF_RC32KCR offset) 32 kHz RC Oscillator Control Register */ 467 #define BSCIF_RC32KCR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_RC32KCR reset_value) 32 kHz RC Oscillator Control Register */ 468 469 #define BSCIF_RC32KCR_EN_Pos 0 /**< \brief (BSCIF_RC32KCR) Enable as Generic clock source */ 470 #define BSCIF_RC32KCR_EN (_U_(0x1) << BSCIF_RC32KCR_EN_Pos) 471 #define BSCIF_RC32KCR_TCEN_Pos 1 /**< \brief (BSCIF_RC32KCR) Temperature Compensation Enable */ 472 #define BSCIF_RC32KCR_TCEN (_U_(0x1) << BSCIF_RC32KCR_TCEN_Pos) 473 #define BSCIF_RC32KCR_EN32K_Pos 2 /**< \brief (BSCIF_RC32KCR) Enable 32 KHz output */ 474 #define BSCIF_RC32KCR_EN32K (_U_(0x1) << BSCIF_RC32KCR_EN32K_Pos) 475 #define BSCIF_RC32KCR_EN1K_Pos 3 /**< \brief (BSCIF_RC32KCR) Enable 1 kHz output */ 476 #define BSCIF_RC32KCR_EN1K (_U_(0x1) << BSCIF_RC32KCR_EN1K_Pos) 477 #define BSCIF_RC32KCR_MODE_Pos 4 /**< \brief (BSCIF_RC32KCR) Mode Selection */ 478 #define BSCIF_RC32KCR_MODE (_U_(0x1) << BSCIF_RC32KCR_MODE_Pos) 479 #define BSCIF_RC32KCR_REF_Pos 5 /**< \brief (BSCIF_RC32KCR) Reference select */ 480 #define BSCIF_RC32KCR_REF (_U_(0x1) << BSCIF_RC32KCR_REF_Pos) 481 #define BSCIF_RC32KCR_FCD_Pos 7 /**< \brief (BSCIF_RC32KCR) Flash calibration done */ 482 #define BSCIF_RC32KCR_FCD (_U_(0x1) << BSCIF_RC32KCR_FCD_Pos) 483 #define BSCIF_RC32KCR_MASK _U_(0x000000BF) /**< \brief (BSCIF_RC32KCR) MASK Register */ 484 485 /* -------- BSCIF_RC32KTUNE : (BSCIF Offset: 0x028) (R/W 32) 32kHz RC Oscillator Tuning Register -------- */ 486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 487 typedef union { 488 struct { 489 uint32_t FINE:6; /*!< bit: 0.. 5 Fine value */ 490 uint32_t :10; /*!< bit: 6..15 Reserved */ 491 uint32_t COARSE:7; /*!< bit: 16..22 Coarse Value */ 492 uint32_t :9; /*!< bit: 23..31 Reserved */ 493 } bit; /*!< Structure used for bit access */ 494 uint32_t reg; /*!< Type used for register access */ 495 } BSCIF_RC32KTUNE_Type; 496 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 497 498 #define BSCIF_RC32KTUNE_OFFSET 0x028 /**< \brief (BSCIF_RC32KTUNE offset) 32kHz RC Oscillator Tuning Register */ 499 #define BSCIF_RC32KTUNE_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_RC32KTUNE reset_value) 32kHz RC Oscillator Tuning Register */ 500 501 #define BSCIF_RC32KTUNE_FINE_Pos 0 /**< \brief (BSCIF_RC32KTUNE) Fine value */ 502 #define BSCIF_RC32KTUNE_FINE_Msk (_U_(0x3F) << BSCIF_RC32KTUNE_FINE_Pos) 503 #define BSCIF_RC32KTUNE_FINE(value) (BSCIF_RC32KTUNE_FINE_Msk & ((value) << BSCIF_RC32KTUNE_FINE_Pos)) 504 #define BSCIF_RC32KTUNE_COARSE_Pos 16 /**< \brief (BSCIF_RC32KTUNE) Coarse Value */ 505 #define BSCIF_RC32KTUNE_COARSE_Msk (_U_(0x7F) << BSCIF_RC32KTUNE_COARSE_Pos) 506 #define BSCIF_RC32KTUNE_COARSE(value) (BSCIF_RC32KTUNE_COARSE_Msk & ((value) << BSCIF_RC32KTUNE_COARSE_Pos)) 507 #define BSCIF_RC32KTUNE_MASK _U_(0x007F003F) /**< \brief (BSCIF_RC32KTUNE) MASK Register */ 508 509 /* -------- BSCIF_BOD33CTRL : (BSCIF Offset: 0x02C) (R/W 32) BOD33 Control Register -------- */ 510 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 511 typedef union { 512 struct { 513 uint32_t EN:1; /*!< bit: 0 Enable */ 514 uint32_t HYST:1; /*!< bit: 1 BOD Hysteresis */ 515 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 516 uint32_t ACTION:2; /*!< bit: 8.. 9 Action */ 517 uint32_t :6; /*!< bit: 10..15 Reserved */ 518 uint32_t MODE:1; /*!< bit: 16 Operation modes */ 519 uint32_t :13; /*!< bit: 17..29 Reserved */ 520 uint32_t FCD:1; /*!< bit: 30 BOD Fuse Calibration Done */ 521 uint32_t SFV:1; /*!< bit: 31 BOD Control Register Store Final Value */ 522 } bit; /*!< Structure used for bit access */ 523 uint32_t reg; /*!< Type used for register access */ 524 } BSCIF_BOD33CTRL_Type; 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 #define BSCIF_BOD33CTRL_OFFSET 0x02C /**< \brief (BSCIF_BOD33CTRL offset) BOD33 Control Register */ 528 529 #define BSCIF_BOD33CTRL_EN_Pos 0 /**< \brief (BSCIF_BOD33CTRL) Enable */ 530 #define BSCIF_BOD33CTRL_EN (_U_(0x1) << BSCIF_BOD33CTRL_EN_Pos) 531 #define BSCIF_BOD33CTRL_HYST_Pos 1 /**< \brief (BSCIF_BOD33CTRL) BOD Hysteresis */ 532 #define BSCIF_BOD33CTRL_HYST (_U_(0x1) << BSCIF_BOD33CTRL_HYST_Pos) 533 #define BSCIF_BOD33CTRL_ACTION_Pos 8 /**< \brief (BSCIF_BOD33CTRL) Action */ 534 #define BSCIF_BOD33CTRL_ACTION_Msk (_U_(0x3) << BSCIF_BOD33CTRL_ACTION_Pos) 535 #define BSCIF_BOD33CTRL_ACTION(value) (BSCIF_BOD33CTRL_ACTION_Msk & ((value) << BSCIF_BOD33CTRL_ACTION_Pos)) 536 #define BSCIF_BOD33CTRL_MODE_Pos 16 /**< \brief (BSCIF_BOD33CTRL) Operation modes */ 537 #define BSCIF_BOD33CTRL_MODE (_U_(0x1) << BSCIF_BOD33CTRL_MODE_Pos) 538 #define BSCIF_BOD33CTRL_FCD_Pos 30 /**< \brief (BSCIF_BOD33CTRL) BOD Fuse Calibration Done */ 539 #define BSCIF_BOD33CTRL_FCD (_U_(0x1) << BSCIF_BOD33CTRL_FCD_Pos) 540 #define BSCIF_BOD33CTRL_SFV_Pos 31 /**< \brief (BSCIF_BOD33CTRL) BOD Control Register Store Final Value */ 541 #define BSCIF_BOD33CTRL_SFV (_U_(0x1) << BSCIF_BOD33CTRL_SFV_Pos) 542 #define BSCIF_BOD33CTRL_MASK _U_(0xC0010303) /**< \brief (BSCIF_BOD33CTRL) MASK Register */ 543 544 /* -------- BSCIF_BOD33LEVEL : (BSCIF Offset: 0x030) (R/W 32) BOD33 Level Register -------- */ 545 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 546 typedef union { 547 struct { 548 uint32_t VAL:6; /*!< bit: 0.. 5 BOD Value */ 549 uint32_t :26; /*!< bit: 6..31 Reserved */ 550 } bit; /*!< Structure used for bit access */ 551 uint32_t reg; /*!< Type used for register access */ 552 } BSCIF_BOD33LEVEL_Type; 553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 554 555 #define BSCIF_BOD33LEVEL_OFFSET 0x030 /**< \brief (BSCIF_BOD33LEVEL offset) BOD33 Level Register */ 556 #define BSCIF_BOD33LEVEL_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BOD33LEVEL reset_value) BOD33 Level Register */ 557 558 #define BSCIF_BOD33LEVEL_VAL_Pos 0 /**< \brief (BSCIF_BOD33LEVEL) BOD Value */ 559 #define BSCIF_BOD33LEVEL_VAL_Msk (_U_(0x3F) << BSCIF_BOD33LEVEL_VAL_Pos) 560 #define BSCIF_BOD33LEVEL_VAL(value) (BSCIF_BOD33LEVEL_VAL_Msk & ((value) << BSCIF_BOD33LEVEL_VAL_Pos)) 561 #define BSCIF_BOD33LEVEL_MASK _U_(0x0000003F) /**< \brief (BSCIF_BOD33LEVEL) MASK Register */ 562 563 /* -------- BSCIF_BOD33SAMPLING : (BSCIF Offset: 0x034) (R/W 32) BOD33 Sampling Control Register -------- */ 564 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 565 typedef union { 566 struct { 567 uint32_t CEN:1; /*!< bit: 0 Clock Enable */ 568 uint32_t CSSEL:1; /*!< bit: 1 Clock Source Select */ 569 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 570 uint32_t PSEL:4; /*!< bit: 8..11 Prescaler Select */ 571 uint32_t :20; /*!< bit: 12..31 Reserved */ 572 } bit; /*!< Structure used for bit access */ 573 uint32_t reg; /*!< Type used for register access */ 574 } BSCIF_BOD33SAMPLING_Type; 575 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 576 577 #define BSCIF_BOD33SAMPLING_OFFSET 0x034 /**< \brief (BSCIF_BOD33SAMPLING offset) BOD33 Sampling Control Register */ 578 #define BSCIF_BOD33SAMPLING_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BOD33SAMPLING reset_value) BOD33 Sampling Control Register */ 579 580 #define BSCIF_BOD33SAMPLING_CEN_Pos 0 /**< \brief (BSCIF_BOD33SAMPLING) Clock Enable */ 581 #define BSCIF_BOD33SAMPLING_CEN (_U_(0x1) << BSCIF_BOD33SAMPLING_CEN_Pos) 582 #define BSCIF_BOD33SAMPLING_CSSEL_Pos 1 /**< \brief (BSCIF_BOD33SAMPLING) Clock Source Select */ 583 #define BSCIF_BOD33SAMPLING_CSSEL (_U_(0x1) << BSCIF_BOD33SAMPLING_CSSEL_Pos) 584 #define BSCIF_BOD33SAMPLING_PSEL_Pos 8 /**< \brief (BSCIF_BOD33SAMPLING) Prescaler Select */ 585 #define BSCIF_BOD33SAMPLING_PSEL_Msk (_U_(0xF) << BSCIF_BOD33SAMPLING_PSEL_Pos) 586 #define BSCIF_BOD33SAMPLING_PSEL(value) (BSCIF_BOD33SAMPLING_PSEL_Msk & ((value) << BSCIF_BOD33SAMPLING_PSEL_Pos)) 587 #define BSCIF_BOD33SAMPLING_MASK _U_(0x00000F03) /**< \brief (BSCIF_BOD33SAMPLING) MASK Register */ 588 589 /* -------- BSCIF_BOD18CTRL : (BSCIF Offset: 0x038) (R/W 32) BOD18 Control Register -------- */ 590 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 591 typedef union { 592 struct { 593 uint32_t EN:1; /*!< bit: 0 Enable */ 594 uint32_t HYST:1; /*!< bit: 1 BOD Hysteresis */ 595 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 596 uint32_t ACTION:2; /*!< bit: 8.. 9 Action */ 597 uint32_t :6; /*!< bit: 10..15 Reserved */ 598 uint32_t MODE:1; /*!< bit: 16 Operation modes */ 599 uint32_t :13; /*!< bit: 17..29 Reserved */ 600 uint32_t FCD:1; /*!< bit: 30 BOD Fuse Calibration Done */ 601 uint32_t SFV:1; /*!< bit: 31 BOD Control Register Store Final Value */ 602 } bit; /*!< Structure used for bit access */ 603 uint32_t reg; /*!< Type used for register access */ 604 } BSCIF_BOD18CTRL_Type; 605 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 606 607 #define BSCIF_BOD18CTRL_OFFSET 0x038 /**< \brief (BSCIF_BOD18CTRL offset) BOD18 Control Register */ 608 #define BSCIF_BOD18CTRL_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BOD18CTRL reset_value) BOD18 Control Register */ 609 610 #define BSCIF_BOD18CTRL_EN_Pos 0 /**< \brief (BSCIF_BOD18CTRL) Enable */ 611 #define BSCIF_BOD18CTRL_EN (_U_(0x1) << BSCIF_BOD18CTRL_EN_Pos) 612 #define BSCIF_BOD18CTRL_HYST_Pos 1 /**< \brief (BSCIF_BOD18CTRL) BOD Hysteresis */ 613 #define BSCIF_BOD18CTRL_HYST (_U_(0x1) << BSCIF_BOD18CTRL_HYST_Pos) 614 #define BSCIF_BOD18CTRL_ACTION_Pos 8 /**< \brief (BSCIF_BOD18CTRL) Action */ 615 #define BSCIF_BOD18CTRL_ACTION_Msk (_U_(0x3) << BSCIF_BOD18CTRL_ACTION_Pos) 616 #define BSCIF_BOD18CTRL_ACTION(value) (BSCIF_BOD18CTRL_ACTION_Msk & ((value) << BSCIF_BOD18CTRL_ACTION_Pos)) 617 #define BSCIF_BOD18CTRL_MODE_Pos 16 /**< \brief (BSCIF_BOD18CTRL) Operation modes */ 618 #define BSCIF_BOD18CTRL_MODE (_U_(0x1) << BSCIF_BOD18CTRL_MODE_Pos) 619 #define BSCIF_BOD18CTRL_FCD_Pos 30 /**< \brief (BSCIF_BOD18CTRL) BOD Fuse Calibration Done */ 620 #define BSCIF_BOD18CTRL_FCD (_U_(0x1) << BSCIF_BOD18CTRL_FCD_Pos) 621 #define BSCIF_BOD18CTRL_SFV_Pos 31 /**< \brief (BSCIF_BOD18CTRL) BOD Control Register Store Final Value */ 622 #define BSCIF_BOD18CTRL_SFV (_U_(0x1) << BSCIF_BOD18CTRL_SFV_Pos) 623 #define BSCIF_BOD18CTRL_MASK _U_(0xC0010303) /**< \brief (BSCIF_BOD18CTRL) MASK Register */ 624 625 /* -------- BSCIF_BOD18LEVEL : (BSCIF Offset: 0x03C) (R/W 32) BOD18 Level Register -------- */ 626 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 627 typedef union { 628 struct { 629 uint32_t VAL:6; /*!< bit: 0.. 5 BOD Value */ 630 uint32_t :25; /*!< bit: 6..30 Reserved */ 631 uint32_t RANGE:1; /*!< bit: 31 BOD Threshold Range */ 632 } bit; /*!< Structure used for bit access */ 633 uint32_t reg; /*!< Type used for register access */ 634 } BSCIF_BOD18LEVEL_Type; 635 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 636 637 #define BSCIF_BOD18LEVEL_OFFSET 0x03C /**< \brief (BSCIF_BOD18LEVEL offset) BOD18 Level Register */ 638 #define BSCIF_BOD18LEVEL_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BOD18LEVEL reset_value) BOD18 Level Register */ 639 640 #define BSCIF_BOD18LEVEL_VAL_Pos 0 /**< \brief (BSCIF_BOD18LEVEL) BOD Value */ 641 #define BSCIF_BOD18LEVEL_VAL_Msk (_U_(0x3F) << BSCIF_BOD18LEVEL_VAL_Pos) 642 #define BSCIF_BOD18LEVEL_VAL(value) (BSCIF_BOD18LEVEL_VAL_Msk & ((value) << BSCIF_BOD18LEVEL_VAL_Pos)) 643 #define BSCIF_BOD18LEVEL_RANGE_Pos 31 /**< \brief (BSCIF_BOD18LEVEL) BOD Threshold Range */ 644 #define BSCIF_BOD18LEVEL_RANGE (_U_(0x1) << BSCIF_BOD18LEVEL_RANGE_Pos) 645 #define BSCIF_BOD18LEVEL_MASK _U_(0x8000003F) /**< \brief (BSCIF_BOD18LEVEL) MASK Register */ 646 647 /* -------- BSCIF_VREGCR : (BSCIF Offset: 0x044) (R/W 32) Voltage Regulator Configuration Register -------- */ 648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 649 typedef union { 650 struct { 651 uint32_t DIS:1; /*!< bit: 0 Voltage Regulator disable */ 652 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 653 uint32_t SSG:1; /*!< bit: 8 Spread Spectrum Generator Enable */ 654 uint32_t SSW:1; /*!< bit: 9 Stop Switching */ 655 uint32_t SSWEVT:1; /*!< bit: 10 Stop Switching On Event Enable */ 656 uint32_t :20; /*!< bit: 11..30 Reserved */ 657 uint32_t SFV:1; /*!< bit: 31 Store Final Value */ 658 } bit; /*!< Structure used for bit access */ 659 uint32_t reg; /*!< Type used for register access */ 660 } BSCIF_VREGCR_Type; 661 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 662 663 #define BSCIF_VREGCR_OFFSET 0x044 /**< \brief (BSCIF_VREGCR offset) Voltage Regulator Configuration Register */ 664 #define BSCIF_VREGCR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_VREGCR reset_value) Voltage Regulator Configuration Register */ 665 666 #define BSCIF_VREGCR_DIS_Pos 0 /**< \brief (BSCIF_VREGCR) Voltage Regulator disable */ 667 #define BSCIF_VREGCR_DIS (_U_(0x1) << BSCIF_VREGCR_DIS_Pos) 668 #define BSCIF_VREGCR_SSG_Pos 8 /**< \brief (BSCIF_VREGCR) Spread Spectrum Generator Enable */ 669 #define BSCIF_VREGCR_SSG (_U_(0x1) << BSCIF_VREGCR_SSG_Pos) 670 #define BSCIF_VREGCR_SSW_Pos 9 /**< \brief (BSCIF_VREGCR) Stop Switching */ 671 #define BSCIF_VREGCR_SSW (_U_(0x1) << BSCIF_VREGCR_SSW_Pos) 672 #define BSCIF_VREGCR_SSWEVT_Pos 10 /**< \brief (BSCIF_VREGCR) Stop Switching On Event Enable */ 673 #define BSCIF_VREGCR_SSWEVT (_U_(0x1) << BSCIF_VREGCR_SSWEVT_Pos) 674 #define BSCIF_VREGCR_SFV_Pos 31 /**< \brief (BSCIF_VREGCR) Store Final Value */ 675 #define BSCIF_VREGCR_SFV (_U_(0x1) << BSCIF_VREGCR_SFV_Pos) 676 #define BSCIF_VREGCR_MASK _U_(0x80000701) /**< \brief (BSCIF_VREGCR) MASK Register */ 677 678 /* -------- BSCIF_VREGNCSR : (BSCIF Offset: 0x04C) (R/W 32) Normal Mode Control and Status Register -------- */ 679 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 680 typedef union { 681 uint32_t reg; /*!< Type used for register access */ 682 } BSCIF_VREGNCSR_Type; 683 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 684 685 #define BSCIF_VREGNCSR_OFFSET 0x04C /**< \brief (BSCIF_VREGNCSR offset) Normal Mode Control and Status Register */ 686 #define BSCIF_VREGNCSR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_VREGNCSR reset_value) Normal Mode Control and Status Register */ 687 688 #define BSCIF_VREGNCSR_MASK _U_(0x00000000) /**< \brief (BSCIF_VREGNCSR) MASK Register */ 689 690 /* -------- BSCIF_VREGLPCSR : (BSCIF Offset: 0x050) (R/W 32) LP Mode Control and Status Register -------- */ 691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 692 typedef union { 693 uint32_t reg; /*!< Type used for register access */ 694 } BSCIF_VREGLPCSR_Type; 695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 696 697 #define BSCIF_VREGLPCSR_OFFSET 0x050 /**< \brief (BSCIF_VREGLPCSR offset) LP Mode Control and Status Register */ 698 #define BSCIF_VREGLPCSR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_VREGLPCSR reset_value) LP Mode Control and Status Register */ 699 700 #define BSCIF_VREGLPCSR_MASK _U_(0x00000000) /**< \brief (BSCIF_VREGLPCSR) MASK Register */ 701 702 /* -------- BSCIF_RC1MCR : (BSCIF Offset: 0x058) (R/W 32) 1MHz RC Clock Configuration Register -------- */ 703 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 704 typedef union { 705 struct { 706 uint32_t CLKOE:1; /*!< bit: 0 1MHz RC Osc Clock Output Enable */ 707 uint32_t :6; /*!< bit: 1.. 6 Reserved */ 708 uint32_t FCD:1; /*!< bit: 7 Flash Calibration Done */ 709 uint32_t CLKCAL:5; /*!< bit: 8..12 1MHz RC Osc Calibration */ 710 uint32_t :19; /*!< bit: 13..31 Reserved */ 711 } bit; /*!< Structure used for bit access */ 712 uint32_t reg; /*!< Type used for register access */ 713 } BSCIF_RC1MCR_Type; 714 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 715 716 #define BSCIF_RC1MCR_OFFSET 0x058 /**< \brief (BSCIF_RC1MCR offset) 1MHz RC Clock Configuration Register */ 717 #define BSCIF_RC1MCR_RESETVALUE _U_(0x00000F00); /**< \brief (BSCIF_RC1MCR reset_value) 1MHz RC Clock Configuration Register */ 718 719 #define BSCIF_RC1MCR_CLKOE_Pos 0 /**< \brief (BSCIF_RC1MCR) 1MHz RC Osc Clock Output Enable */ 720 #define BSCIF_RC1MCR_CLKOE (_U_(0x1) << BSCIF_RC1MCR_CLKOE_Pos) 721 #define BSCIF_RC1MCR_FCD_Pos 7 /**< \brief (BSCIF_RC1MCR) Flash Calibration Done */ 722 #define BSCIF_RC1MCR_FCD (_U_(0x1) << BSCIF_RC1MCR_FCD_Pos) 723 #define BSCIF_RC1MCR_CLKCAL_Pos 8 /**< \brief (BSCIF_RC1MCR) 1MHz RC Osc Calibration */ 724 #define BSCIF_RC1MCR_CLKCAL_Msk (_U_(0x1F) << BSCIF_RC1MCR_CLKCAL_Pos) 725 #define BSCIF_RC1MCR_CLKCAL(value) (BSCIF_RC1MCR_CLKCAL_Msk & ((value) << BSCIF_RC1MCR_CLKCAL_Pos)) 726 #define BSCIF_RC1MCR_MASK _U_(0x00001F81) /**< \brief (BSCIF_RC1MCR) MASK Register */ 727 728 /* -------- BSCIF_BGCR : (BSCIF Offset: 0x05C) (R/W 32) Bandgap Calibration Register -------- */ 729 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 730 typedef union { 731 uint32_t reg; /*!< Type used for register access */ 732 } BSCIF_BGCR_Type; 733 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 734 735 #define BSCIF_BGCR_OFFSET 0x05C /**< \brief (BSCIF_BGCR offset) Bandgap Calibration Register */ 736 #define BSCIF_BGCR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BGCR reset_value) Bandgap Calibration Register */ 737 738 #define BSCIF_BGCR_MASK _U_(0x00000000) /**< \brief (BSCIF_BGCR) MASK Register */ 739 740 /* -------- BSCIF_BGCTRL : (BSCIF Offset: 0x060) (R/W 32) Bandgap Control Register -------- */ 741 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 742 typedef union { 743 struct { 744 uint32_t ADCISEL:2; /*!< bit: 0.. 1 ADC Input Selection */ 745 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 746 uint32_t TSEN:1; /*!< bit: 8 Temperature Sensor Enable */ 747 uint32_t :23; /*!< bit: 9..31 Reserved */ 748 } bit; /*!< Structure used for bit access */ 749 uint32_t reg; /*!< Type used for register access */ 750 } BSCIF_BGCTRL_Type; 751 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 752 753 #define BSCIF_BGCTRL_OFFSET 0x060 /**< \brief (BSCIF_BGCTRL offset) Bandgap Control Register */ 754 #define BSCIF_BGCTRL_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BGCTRL reset_value) Bandgap Control Register */ 755 756 #define BSCIF_BGCTRL_ADCISEL_Pos 0 /**< \brief (BSCIF_BGCTRL) ADC Input Selection */ 757 #define BSCIF_BGCTRL_ADCISEL_Msk (_U_(0x3) << BSCIF_BGCTRL_ADCISEL_Pos) 758 #define BSCIF_BGCTRL_ADCISEL(value) (BSCIF_BGCTRL_ADCISEL_Msk & ((value) << BSCIF_BGCTRL_ADCISEL_Pos)) 759 #define BSCIF_BGCTRL_ADCISEL_DIS_Val _U_(0x0) /**< \brief (BSCIF_BGCTRL) */ 760 #define BSCIF_BGCTRL_ADCISEL_VTEMP_Val _U_(0x1) /**< \brief (BSCIF_BGCTRL) */ 761 #define BSCIF_BGCTRL_ADCISEL_VREF_Val _U_(0x2) /**< \brief (BSCIF_BGCTRL) */ 762 #define BSCIF_BGCTRL_ADCISEL_DIS (BSCIF_BGCTRL_ADCISEL_DIS_Val << BSCIF_BGCTRL_ADCISEL_Pos) 763 #define BSCIF_BGCTRL_ADCISEL_VTEMP (BSCIF_BGCTRL_ADCISEL_VTEMP_Val << BSCIF_BGCTRL_ADCISEL_Pos) 764 #define BSCIF_BGCTRL_ADCISEL_VREF (BSCIF_BGCTRL_ADCISEL_VREF_Val << BSCIF_BGCTRL_ADCISEL_Pos) 765 #define BSCIF_BGCTRL_TSEN_Pos 8 /**< \brief (BSCIF_BGCTRL) Temperature Sensor Enable */ 766 #define BSCIF_BGCTRL_TSEN (_U_(0x1) << BSCIF_BGCTRL_TSEN_Pos) 767 #define BSCIF_BGCTRL_MASK _U_(0x00000103) /**< \brief (BSCIF_BGCTRL) MASK Register */ 768 769 /* -------- BSCIF_BGSR : (BSCIF Offset: 0x064) (R/ 32) Bandgap Status Register -------- */ 770 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 771 typedef union { 772 struct { 773 uint32_t BGBUFRDY:8; /*!< bit: 0.. 7 Bandgap Buffer Ready */ 774 uint32_t :8; /*!< bit: 8..15 Reserved */ 775 uint32_t BGRDY:1; /*!< bit: 16 Bandgap Voltage Reference Ready */ 776 uint32_t LPBGRDY:1; /*!< bit: 17 Low Power Bandgap Voltage Reference Ready */ 777 uint32_t VREF:2; /*!< bit: 18..19 Voltage Reference Used by the System */ 778 uint32_t :12; /*!< bit: 20..31 Reserved */ 779 } bit; /*!< Structure used for bit access */ 780 uint32_t reg; /*!< Type used for register access */ 781 } BSCIF_BGSR_Type; 782 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 783 784 #define BSCIF_BGSR_OFFSET 0x064 /**< \brief (BSCIF_BGSR offset) Bandgap Status Register */ 785 #define BSCIF_BGSR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BGSR reset_value) Bandgap Status Register */ 786 787 #define BSCIF_BGSR_BGBUFRDY_Pos 0 /**< \brief (BSCIF_BGSR) Bandgap Buffer Ready */ 788 #define BSCIF_BGSR_BGBUFRDY_Msk (_U_(0xFF) << BSCIF_BGSR_BGBUFRDY_Pos) 789 #define BSCIF_BGSR_BGBUFRDY(value) (BSCIF_BGSR_BGBUFRDY_Msk & ((value) << BSCIF_BGSR_BGBUFRDY_Pos)) 790 #define BSCIF_BGSR_BGBUFRDY_FLASH_Val _U_(0x1) /**< \brief (BSCIF_BGSR) */ 791 #define BSCIF_BGSR_BGBUFRDY_PLL_Val _U_(0x2) /**< \brief (BSCIF_BGSR) */ 792 #define BSCIF_BGSR_BGBUFRDY_VREG_Val _U_(0x4) /**< \brief (BSCIF_BGSR) */ 793 #define BSCIF_BGSR_BGBUFRDY_BUFRR_Val _U_(0x8) /**< \brief (BSCIF_BGSR) */ 794 #define BSCIF_BGSR_BGBUFRDY_ADC_Val _U_(0x10) /**< \brief (BSCIF_BGSR) */ 795 #define BSCIF_BGSR_BGBUFRDY_LCD_Val _U_(0x20) /**< \brief (BSCIF_BGSR) */ 796 #define BSCIF_BGSR_BGBUFRDY_FLASH (BSCIF_BGSR_BGBUFRDY_FLASH_Val << BSCIF_BGSR_BGBUFRDY_Pos) 797 #define BSCIF_BGSR_BGBUFRDY_PLL (BSCIF_BGSR_BGBUFRDY_PLL_Val << BSCIF_BGSR_BGBUFRDY_Pos) 798 #define BSCIF_BGSR_BGBUFRDY_VREG (BSCIF_BGSR_BGBUFRDY_VREG_Val << BSCIF_BGSR_BGBUFRDY_Pos) 799 #define BSCIF_BGSR_BGBUFRDY_BUFRR (BSCIF_BGSR_BGBUFRDY_BUFRR_Val << BSCIF_BGSR_BGBUFRDY_Pos) 800 #define BSCIF_BGSR_BGBUFRDY_ADC (BSCIF_BGSR_BGBUFRDY_ADC_Val << BSCIF_BGSR_BGBUFRDY_Pos) 801 #define BSCIF_BGSR_BGBUFRDY_LCD (BSCIF_BGSR_BGBUFRDY_LCD_Val << BSCIF_BGSR_BGBUFRDY_Pos) 802 #define BSCIF_BGSR_BGRDY_Pos 16 /**< \brief (BSCIF_BGSR) Bandgap Voltage Reference Ready */ 803 #define BSCIF_BGSR_BGRDY (_U_(0x1) << BSCIF_BGSR_BGRDY_Pos) 804 #define BSCIF_BGSR_LPBGRDY_Pos 17 /**< \brief (BSCIF_BGSR) Low Power Bandgap Voltage Reference Ready */ 805 #define BSCIF_BGSR_LPBGRDY (_U_(0x1) << BSCIF_BGSR_LPBGRDY_Pos) 806 #define BSCIF_BGSR_VREF_Pos 18 /**< \brief (BSCIF_BGSR) Voltage Reference Used by the System */ 807 #define BSCIF_BGSR_VREF_Msk (_U_(0x3) << BSCIF_BGSR_VREF_Pos) 808 #define BSCIF_BGSR_VREF(value) (BSCIF_BGSR_VREF_Msk & ((value) << BSCIF_BGSR_VREF_Pos)) 809 #define BSCIF_BGSR_MASK _U_(0x000F00FF) /**< \brief (BSCIF_BGSR) MASK Register */ 810 811 /* -------- BSCIF_BR : (BSCIF Offset: 0x078) (R/W 32) br Backup Register -------- */ 812 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 813 typedef union { 814 uint32_t reg; /*!< Type used for register access */ 815 } BSCIF_BR_Type; 816 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 817 818 #define BSCIF_BR_OFFSET 0x078 /**< \brief (BSCIF_BR offset) Backup Register */ 819 #define BSCIF_BR_RESETVALUE _U_(0x00000000); /**< \brief (BSCIF_BR reset_value) Backup Register */ 820 #define BSCIF_BR_MASK _U_(0xFFFFFFFF) /**< \brief (BSCIF_BR) MASK Register */ 821 822 /* -------- BSCIF_BRIFBVERSION : (BSCIF Offset: 0x3E4) (R/ 32) Backup Register Interface Version Register -------- */ 823 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 824 typedef union { 825 struct { 826 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 827 uint32_t :4; /*!< bit: 12..15 Reserved */ 828 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 829 uint32_t :12; /*!< bit: 20..31 Reserved */ 830 } bit; /*!< Structure used for bit access */ 831 uint32_t reg; /*!< Type used for register access */ 832 } BSCIF_BRIFBVERSION_Type; 833 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 834 835 #define BSCIF_BRIFBVERSION_OFFSET 0x3E4 /**< \brief (BSCIF_BRIFBVERSION offset) Backup Register Interface Version Register */ 836 #define BSCIF_BRIFBVERSION_RESETVALUE _U_(0x00000100); /**< \brief (BSCIF_BRIFBVERSION reset_value) Backup Register Interface Version Register */ 837 838 #define BSCIF_BRIFBVERSION_VERSION_Pos 0 /**< \brief (BSCIF_BRIFBVERSION) Version Number */ 839 #define BSCIF_BRIFBVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_BRIFBVERSION_VERSION_Pos) 840 #define BSCIF_BRIFBVERSION_VERSION(value) (BSCIF_BRIFBVERSION_VERSION_Msk & ((value) << BSCIF_BRIFBVERSION_VERSION_Pos)) 841 #define BSCIF_BRIFBVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_BRIFBVERSION) Variant Number */ 842 #define BSCIF_BRIFBVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_BRIFBVERSION_VARIANT_Pos) 843 #define BSCIF_BRIFBVERSION_VARIANT(value) (BSCIF_BRIFBVERSION_VARIANT_Msk & ((value) << BSCIF_BRIFBVERSION_VARIANT_Pos)) 844 #define BSCIF_BRIFBVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_BRIFBVERSION) MASK Register */ 845 846 /* -------- BSCIF_BGREFIFBVERSION : (BSCIF Offset: 0x3E8) (R/ 32) BGREFIFB Version Register -------- */ 847 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 848 typedef union { 849 struct { 850 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 851 uint32_t :4; /*!< bit: 12..15 Reserved */ 852 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 853 uint32_t :12; /*!< bit: 20..31 Reserved */ 854 } bit; /*!< Structure used for bit access */ 855 uint32_t reg; /*!< Type used for register access */ 856 } BSCIF_BGREFIFBVERSION_Type; 857 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 858 859 #define BSCIF_BGREFIFBVERSION_OFFSET 0x3E8 /**< \brief (BSCIF_BGREFIFBVERSION offset) BGREFIFB Version Register */ 860 #define BSCIF_BGREFIFBVERSION_RESETVALUE _U_(0x00000110); /**< \brief (BSCIF_BGREFIFBVERSION reset_value) BGREFIFB Version Register */ 861 862 #define BSCIF_BGREFIFBVERSION_VERSION_Pos 0 /**< \brief (BSCIF_BGREFIFBVERSION) Version Number */ 863 #define BSCIF_BGREFIFBVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_BGREFIFBVERSION_VERSION_Pos) 864 #define BSCIF_BGREFIFBVERSION_VERSION(value) (BSCIF_BGREFIFBVERSION_VERSION_Msk & ((value) << BSCIF_BGREFIFBVERSION_VERSION_Pos)) 865 #define BSCIF_BGREFIFBVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_BGREFIFBVERSION) Variant Number */ 866 #define BSCIF_BGREFIFBVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_BGREFIFBVERSION_VARIANT_Pos) 867 #define BSCIF_BGREFIFBVERSION_VARIANT(value) (BSCIF_BGREFIFBVERSION_VARIANT_Msk & ((value) << BSCIF_BGREFIFBVERSION_VARIANT_Pos)) 868 #define BSCIF_BGREFIFBVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_BGREFIFBVERSION) MASK Register */ 869 870 /* -------- BSCIF_VREGIFGVERSION : (BSCIF Offset: 0x3EC) (R/ 32) VREGIFA Version Register -------- */ 871 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 872 typedef union { 873 struct { 874 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 875 uint32_t :4; /*!< bit: 12..15 Reserved */ 876 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 877 uint32_t :12; /*!< bit: 20..31 Reserved */ 878 } bit; /*!< Structure used for bit access */ 879 uint32_t reg; /*!< Type used for register access */ 880 } BSCIF_VREGIFGVERSION_Type; 881 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 882 883 #define BSCIF_VREGIFGVERSION_OFFSET 0x3EC /**< \brief (BSCIF_VREGIFGVERSION offset) VREGIFA Version Register */ 884 #define BSCIF_VREGIFGVERSION_RESETVALUE _U_(0x00000110); /**< \brief (BSCIF_VREGIFGVERSION reset_value) VREGIFA Version Register */ 885 886 #define BSCIF_VREGIFGVERSION_VERSION_Pos 0 /**< \brief (BSCIF_VREGIFGVERSION) Version Number */ 887 #define BSCIF_VREGIFGVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_VREGIFGVERSION_VERSION_Pos) 888 #define BSCIF_VREGIFGVERSION_VERSION(value) (BSCIF_VREGIFGVERSION_VERSION_Msk & ((value) << BSCIF_VREGIFGVERSION_VERSION_Pos)) 889 #define BSCIF_VREGIFGVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_VREGIFGVERSION) Variant Number */ 890 #define BSCIF_VREGIFGVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_VREGIFGVERSION_VARIANT_Pos) 891 #define BSCIF_VREGIFGVERSION_VARIANT(value) (BSCIF_VREGIFGVERSION_VARIANT_Msk & ((value) << BSCIF_VREGIFGVERSION_VARIANT_Pos)) 892 #define BSCIF_VREGIFGVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_VREGIFGVERSION) MASK Register */ 893 894 /* -------- BSCIF_BODIFCVERSION : (BSCIF Offset: 0x3F0) (R/ 32) BODIFC Version Register -------- */ 895 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 896 typedef union { 897 struct { 898 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 899 uint32_t :4; /*!< bit: 12..15 Reserved */ 900 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 901 uint32_t :12; /*!< bit: 20..31 Reserved */ 902 } bit; /*!< Structure used for bit access */ 903 uint32_t reg; /*!< Type used for register access */ 904 } BSCIF_BODIFCVERSION_Type; 905 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 906 907 #define BSCIF_BODIFCVERSION_OFFSET 0x3F0 /**< \brief (BSCIF_BODIFCVERSION offset) BODIFC Version Register */ 908 #define BSCIF_BODIFCVERSION_RESETVALUE _U_(0x00000110); /**< \brief (BSCIF_BODIFCVERSION reset_value) BODIFC Version Register */ 909 910 #define BSCIF_BODIFCVERSION_VERSION_Pos 0 /**< \brief (BSCIF_BODIFCVERSION) Version Number */ 911 #define BSCIF_BODIFCVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_BODIFCVERSION_VERSION_Pos) 912 #define BSCIF_BODIFCVERSION_VERSION(value) (BSCIF_BODIFCVERSION_VERSION_Msk & ((value) << BSCIF_BODIFCVERSION_VERSION_Pos)) 913 #define BSCIF_BODIFCVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_BODIFCVERSION) Variant Number */ 914 #define BSCIF_BODIFCVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_BODIFCVERSION_VARIANT_Pos) 915 #define BSCIF_BODIFCVERSION_VARIANT(value) (BSCIF_BODIFCVERSION_VARIANT_Msk & ((value) << BSCIF_BODIFCVERSION_VARIANT_Pos)) 916 #define BSCIF_BODIFCVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_BODIFCVERSION) MASK Register */ 917 918 /* -------- BSCIF_RC32KIFBVERSION : (BSCIF Offset: 0x3F4) (R/ 32) 32 kHz RC Oscillator Version Register -------- */ 919 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 920 typedef union { 921 struct { 922 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 923 uint32_t :4; /*!< bit: 12..15 Reserved */ 924 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 925 uint32_t :12; /*!< bit: 20..31 Reserved */ 926 } bit; /*!< Structure used for bit access */ 927 uint32_t reg; /*!< Type used for register access */ 928 } BSCIF_RC32KIFBVERSION_Type; 929 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 930 931 #define BSCIF_RC32KIFBVERSION_OFFSET 0x3F4 /**< \brief (BSCIF_RC32KIFBVERSION offset) 32 kHz RC Oscillator Version Register */ 932 #define BSCIF_RC32KIFBVERSION_RESETVALUE _U_(0x00000100); /**< \brief (BSCIF_RC32KIFBVERSION reset_value) 32 kHz RC Oscillator Version Register */ 933 934 #define BSCIF_RC32KIFBVERSION_VERSION_Pos 0 /**< \brief (BSCIF_RC32KIFBVERSION) Version number */ 935 #define BSCIF_RC32KIFBVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_RC32KIFBVERSION_VERSION_Pos) 936 #define BSCIF_RC32KIFBVERSION_VERSION(value) (BSCIF_RC32KIFBVERSION_VERSION_Msk & ((value) << BSCIF_RC32KIFBVERSION_VERSION_Pos)) 937 #define BSCIF_RC32KIFBVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_RC32KIFBVERSION) Variant number */ 938 #define BSCIF_RC32KIFBVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_RC32KIFBVERSION_VARIANT_Pos) 939 #define BSCIF_RC32KIFBVERSION_VARIANT(value) (BSCIF_RC32KIFBVERSION_VARIANT_Msk & ((value) << BSCIF_RC32KIFBVERSION_VARIANT_Pos)) 940 #define BSCIF_RC32KIFBVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_RC32KIFBVERSION) MASK Register */ 941 942 /* -------- BSCIF_OSC32IFAVERSION : (BSCIF Offset: 0x3F8) (R/ 32) 32 KHz Oscillator Version Register -------- */ 943 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 944 typedef union { 945 struct { 946 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 947 uint32_t :4; /*!< bit: 12..15 Reserved */ 948 uint32_t VARIANT:4; /*!< bit: 16..19 Variant nubmer */ 949 uint32_t :12; /*!< bit: 20..31 Reserved */ 950 } bit; /*!< Structure used for bit access */ 951 uint32_t reg; /*!< Type used for register access */ 952 } BSCIF_OSC32IFAVERSION_Type; 953 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 954 955 #define BSCIF_OSC32IFAVERSION_OFFSET 0x3F8 /**< \brief (BSCIF_OSC32IFAVERSION offset) 32 KHz Oscillator Version Register */ 956 #define BSCIF_OSC32IFAVERSION_RESETVALUE _U_(0x00000200); /**< \brief (BSCIF_OSC32IFAVERSION reset_value) 32 KHz Oscillator Version Register */ 957 958 #define BSCIF_OSC32IFAVERSION_VERSION_Pos 0 /**< \brief (BSCIF_OSC32IFAVERSION) Version number */ 959 #define BSCIF_OSC32IFAVERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_OSC32IFAVERSION_VERSION_Pos) 960 #define BSCIF_OSC32IFAVERSION_VERSION(value) (BSCIF_OSC32IFAVERSION_VERSION_Msk & ((value) << BSCIF_OSC32IFAVERSION_VERSION_Pos)) 961 #define BSCIF_OSC32IFAVERSION_VARIANT_Pos 16 /**< \brief (BSCIF_OSC32IFAVERSION) Variant nubmer */ 962 #define BSCIF_OSC32IFAVERSION_VARIANT_Msk (_U_(0xF) << BSCIF_OSC32IFAVERSION_VARIANT_Pos) 963 #define BSCIF_OSC32IFAVERSION_VARIANT(value) (BSCIF_OSC32IFAVERSION_VARIANT_Msk & ((value) << BSCIF_OSC32IFAVERSION_VARIANT_Pos)) 964 #define BSCIF_OSC32IFAVERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_OSC32IFAVERSION) MASK Register */ 965 966 /* -------- BSCIF_VERSION : (BSCIF Offset: 0x3FC) (R/ 32) BSCIF Version Register -------- */ 967 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 968 typedef union { 969 struct { 970 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 971 uint32_t :4; /*!< bit: 12..15 Reserved */ 972 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 973 uint32_t :12; /*!< bit: 20..31 Reserved */ 974 } bit; /*!< Structure used for bit access */ 975 uint32_t reg; /*!< Type used for register access */ 976 } BSCIF_VERSION_Type; 977 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 978 979 #define BSCIF_VERSION_OFFSET 0x3FC /**< \brief (BSCIF_VERSION offset) BSCIF Version Register */ 980 #define BSCIF_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (BSCIF_VERSION reset_value) BSCIF Version Register */ 981 982 #define BSCIF_VERSION_VERSION_Pos 0 /**< \brief (BSCIF_VERSION) Version Number */ 983 #define BSCIF_VERSION_VERSION_Msk (_U_(0xFFF) << BSCIF_VERSION_VERSION_Pos) 984 #define BSCIF_VERSION_VERSION(value) (BSCIF_VERSION_VERSION_Msk & ((value) << BSCIF_VERSION_VERSION_Pos)) 985 #define BSCIF_VERSION_VARIANT_Pos 16 /**< \brief (BSCIF_VERSION) Variant Number */ 986 #define BSCIF_VERSION_VARIANT_Msk (_U_(0xF) << BSCIF_VERSION_VARIANT_Pos) 987 #define BSCIF_VERSION_VARIANT(value) (BSCIF_VERSION_VARIANT_Msk & ((value) << BSCIF_VERSION_VARIANT_Pos)) 988 #define BSCIF_VERSION_MASK _U_(0x000F0FFF) /**< \brief (BSCIF_VERSION) MASK Register */ 989 990 /** \brief BscifBr hardware registers */ 991 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 992 typedef struct { 993 __IO uint32_t BR; /**< \brief Offset: 0x000 (R/W 32) Backup Register */ 994 } BscifBr; 995 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 996 997 /** \brief BSCIF hardware registers */ 998 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 999 typedef struct { 1000 __O uint32_t IER; /**< \brief Offset: 0x000 ( /W 32) Interrupt Enable Register */ 1001 __O uint32_t IDR; /**< \brief Offset: 0x004 ( /W 32) Interrupt Disable Register */ 1002 __I uint32_t IMR; /**< \brief Offset: 0x008 (R/ 32) Interrupt Mask Register */ 1003 __I uint32_t ISR; /**< \brief Offset: 0x00C (R/ 32) Interrupt Status Register */ 1004 __O uint32_t ICR; /**< \brief Offset: 0x010 ( /W 32) Interrupt Clear Register */ 1005 __I uint32_t PCLKSR; /**< \brief Offset: 0x014 (R/ 32) Power and Clocks Status Register */ 1006 __O uint32_t UNLOCK; /**< \brief Offset: 0x018 ( /W 32) Unlock Register */ 1007 __IO uint32_t CSCR; /**< \brief Offset: 0x01C (R/W 32) Chip Specific Configuration Register */ 1008 __IO uint32_t OSCCTRL32; /**< \brief Offset: 0x020 (R/W 32) Oscillator 32 Control Register */ 1009 __IO uint32_t RC32KCR; /**< \brief Offset: 0x024 (R/W 32) 32 kHz RC Oscillator Control Register */ 1010 __IO uint32_t RC32KTUNE; /**< \brief Offset: 0x028 (R/W 32) 32kHz RC Oscillator Tuning Register */ 1011 __IO uint32_t BOD33CTRL; /**< \brief Offset: 0x02C (R/W 32) BOD33 Control Register */ 1012 __IO uint32_t BOD33LEVEL; /**< \brief Offset: 0x030 (R/W 32) BOD33 Level Register */ 1013 __IO uint32_t BOD33SAMPLING; /**< \brief Offset: 0x034 (R/W 32) BOD33 Sampling Control Register */ 1014 __IO uint32_t BOD18CTRL; /**< \brief Offset: 0x038 (R/W 32) BOD18 Control Register */ 1015 __IO uint32_t BOD18LEVEL; /**< \brief Offset: 0x03C (R/W 32) BOD18 Level Register */ 1016 RoReg8 Reserved1[0x4]; 1017 __IO uint32_t VREGCR; /**< \brief Offset: 0x044 (R/W 32) Voltage Regulator Configuration Register */ 1018 RoReg8 Reserved2[0x4]; 1019 __IO uint32_t VREGNCSR; /**< \brief Offset: 0x04C (R/W 32) Normal Mode Control and Status Register */ 1020 __IO uint32_t VREGLPCSR; /**< \brief Offset: 0x050 (R/W 32) LP Mode Control and Status Register */ 1021 RoReg8 Reserved3[0x4]; 1022 __IO uint32_t RC1MCR; /**< \brief Offset: 0x058 (R/W 32) 1MHz RC Clock Configuration Register */ 1023 __IO uint32_t BGCR; /**< \brief Offset: 0x05C (R/W 32) Bandgap Calibration Register */ 1024 __IO uint32_t BGCTRL; /**< \brief Offset: 0x060 (R/W 32) Bandgap Control Register */ 1025 __I uint32_t BGSR; /**< \brief Offset: 0x064 (R/ 32) Bandgap Status Register */ 1026 RoReg8 Reserved4[0x10]; 1027 uint32_t BR[4]; /**< \brief Offset: 0x078 BscifBr groups */ 1028 RoReg8 Reserved5[0x35C]; 1029 __I uint32_t BRIFBVERSION; /**< \brief Offset: 0x3E4 (R/ 32) Backup Register Interface Version Register */ 1030 __I uint32_t BGREFIFBVERSION; /**< \brief Offset: 0x3E8 (R/ 32) BGREFIFB Version Register */ 1031 __I uint32_t VREGIFGVERSION; /**< \brief Offset: 0x3EC (R/ 32) VREGIFA Version Register */ 1032 __I uint32_t BODIFCVERSION; /**< \brief Offset: 0x3F0 (R/ 32) BODIFC Version Register */ 1033 __I uint32_t RC32KIFBVERSION; /**< \brief Offset: 0x3F4 (R/ 32) 32 kHz RC Oscillator Version Register */ 1034 __I uint32_t OSC32IFAVERSION; /**< \brief Offset: 0x3F8 (R/ 32) 32 KHz Oscillator Version Register */ 1035 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) BSCIF Version Register */ 1036 } Bscif; 1037 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1038 1039 /*@}*/ 1040 1041 #endif /* _SAM4L_BSCIF_COMPONENT_ */ 1042
