1 /** 2 * \file 3 * 4 * \brief Component description for AESA 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_AESA_COMPONENT_ 30 #define _SAM4L_AESA_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR AESA */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_AESA Advanced Encryption Standard */ 36 /*@{*/ 37 38 #define AESA_I7558 39 #define REV_AESA 0x102 40 41 /* -------- AESA_CTRL : (AESA Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t ENABLE:1; /*!< bit: 0 Enable Module */ 46 uint32_t DKEYGEN:1; /*!< bit: 1 Decryption Key Generate */ 47 uint32_t NEWMSG:1; /*!< bit: 2 New Message */ 48 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 49 uint32_t SWRST:1; /*!< bit: 8 Software Reset */ 50 uint32_t :23; /*!< bit: 9..31 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint32_t reg; /*!< Type used for register access */ 53 } AESA_CTRL_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define AESA_CTRL_OFFSET 0x00 /**< \brief (AESA_CTRL offset) Control Register */ 57 #define AESA_CTRL_RESETVALUE _U_(0x00000000); /**< \brief (AESA_CTRL reset_value) Control Register */ 58 59 #define AESA_CTRL_ENABLE_Pos 0 /**< \brief (AESA_CTRL) Enable Module */ 60 #define AESA_CTRL_ENABLE (_U_(0x1) << AESA_CTRL_ENABLE_Pos) 61 #define AESA_CTRL_DKEYGEN_Pos 1 /**< \brief (AESA_CTRL) Decryption Key Generate */ 62 #define AESA_CTRL_DKEYGEN (_U_(0x1) << AESA_CTRL_DKEYGEN_Pos) 63 #define AESA_CTRL_NEWMSG_Pos 2 /**< \brief (AESA_CTRL) New Message */ 64 #define AESA_CTRL_NEWMSG (_U_(0x1) << AESA_CTRL_NEWMSG_Pos) 65 #define AESA_CTRL_SWRST_Pos 8 /**< \brief (AESA_CTRL) Software Reset */ 66 #define AESA_CTRL_SWRST (_U_(0x1) << AESA_CTRL_SWRST_Pos) 67 #define AESA_CTRL_MASK _U_(0x00000107) /**< \brief (AESA_CTRL) MASK Register */ 68 69 /* -------- AESA_MODE : (AESA Offset: 0x04) (R/W 32) Mode Register -------- */ 70 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 71 typedef union { 72 struct { 73 uint32_t ENCRYPT:1; /*!< bit: 0 Encryption */ 74 uint32_t KEYSIZE:2; /*!< bit: 1.. 2 Key Size */ 75 uint32_t DMA:1; /*!< bit: 3 DMA Mode */ 76 uint32_t OPMODE:3; /*!< bit: 4.. 6 Confidentiality Mode of Operation */ 77 uint32_t :1; /*!< bit: 7 Reserved */ 78 uint32_t CFBS:3; /*!< bit: 8..10 Cipher Feedback Data Segment Size */ 79 uint32_t :5; /*!< bit: 11..15 Reserved */ 80 uint32_t CTYPE:4; /*!< bit: 16..19 Countermeasure Type */ 81 uint32_t :12; /*!< bit: 20..31 Reserved */ 82 } bit; /*!< Structure used for bit access */ 83 uint32_t reg; /*!< Type used for register access */ 84 } AESA_MODE_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 #define AESA_MODE_OFFSET 0x04 /**< \brief (AESA_MODE offset) Mode Register */ 88 #define AESA_MODE_RESETVALUE _U_(0x000F0000); /**< \brief (AESA_MODE reset_value) Mode Register */ 89 90 #define AESA_MODE_ENCRYPT_Pos 0 /**< \brief (AESA_MODE) Encryption */ 91 #define AESA_MODE_ENCRYPT (_U_(0x1) << AESA_MODE_ENCRYPT_Pos) 92 #define AESA_MODE_KEYSIZE_Pos 1 /**< \brief (AESA_MODE) Key Size */ 93 #define AESA_MODE_KEYSIZE_Msk (_U_(0x3) << AESA_MODE_KEYSIZE_Pos) 94 #define AESA_MODE_KEYSIZE(value) (AESA_MODE_KEYSIZE_Msk & ((value) << AESA_MODE_KEYSIZE_Pos)) 95 #define AESA_MODE_DMA_Pos 3 /**< \brief (AESA_MODE) DMA Mode */ 96 #define AESA_MODE_DMA (_U_(0x1) << AESA_MODE_DMA_Pos) 97 #define AESA_MODE_OPMODE_Pos 4 /**< \brief (AESA_MODE) Confidentiality Mode of Operation */ 98 #define AESA_MODE_OPMODE_Msk (_U_(0x7) << AESA_MODE_OPMODE_Pos) 99 #define AESA_MODE_OPMODE(value) (AESA_MODE_OPMODE_Msk & ((value) << AESA_MODE_OPMODE_Pos)) 100 #define AESA_MODE_CFBS_Pos 8 /**< \brief (AESA_MODE) Cipher Feedback Data Segment Size */ 101 #define AESA_MODE_CFBS_Msk (_U_(0x7) << AESA_MODE_CFBS_Pos) 102 #define AESA_MODE_CFBS(value) (AESA_MODE_CFBS_Msk & ((value) << AESA_MODE_CFBS_Pos)) 103 #define AESA_MODE_CTYPE_Pos 16 /**< \brief (AESA_MODE) Countermeasure Type */ 104 #define AESA_MODE_CTYPE_Msk (_U_(0xF) << AESA_MODE_CTYPE_Pos) 105 #define AESA_MODE_CTYPE(value) (AESA_MODE_CTYPE_Msk & ((value) << AESA_MODE_CTYPE_Pos)) 106 #define AESA_MODE_MASK _U_(0x000F077F) /**< \brief (AESA_MODE) MASK Register */ 107 108 /* -------- AESA_DATABUFPTR : (AESA Offset: 0x08) (R/W 32) Data Buffer Pointer Register -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { 111 struct { 112 uint32_t IDATAW:2; /*!< bit: 0.. 1 Input Data Word */ 113 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 114 uint32_t ODATAW:2; /*!< bit: 4.. 5 Output Data Word */ 115 uint32_t :26; /*!< bit: 6..31 Reserved */ 116 } bit; /*!< Structure used for bit access */ 117 uint32_t reg; /*!< Type used for register access */ 118 } AESA_DATABUFPTR_Type; 119 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 #define AESA_DATABUFPTR_OFFSET 0x08 /**< \brief (AESA_DATABUFPTR offset) Data Buffer Pointer Register */ 122 #define AESA_DATABUFPTR_RESETVALUE _U_(0x00000000); /**< \brief (AESA_DATABUFPTR reset_value) Data Buffer Pointer Register */ 123 124 #define AESA_DATABUFPTR_IDATAW_Pos 0 /**< \brief (AESA_DATABUFPTR) Input Data Word */ 125 #define AESA_DATABUFPTR_IDATAW_Msk (_U_(0x3) << AESA_DATABUFPTR_IDATAW_Pos) 126 #define AESA_DATABUFPTR_IDATAW(value) (AESA_DATABUFPTR_IDATAW_Msk & ((value) << AESA_DATABUFPTR_IDATAW_Pos)) 127 #define AESA_DATABUFPTR_ODATAW_Pos 4 /**< \brief (AESA_DATABUFPTR) Output Data Word */ 128 #define AESA_DATABUFPTR_ODATAW_Msk (_U_(0x3) << AESA_DATABUFPTR_ODATAW_Pos) 129 #define AESA_DATABUFPTR_ODATAW(value) (AESA_DATABUFPTR_ODATAW_Msk & ((value) << AESA_DATABUFPTR_ODATAW_Pos)) 130 #define AESA_DATABUFPTR_MASK _U_(0x00000033) /**< \brief (AESA_DATABUFPTR) MASK Register */ 131 132 /* -------- AESA_SR : (AESA Offset: 0x0C) (R/ 32) Status Register -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint32_t ODATARDY:1; /*!< bit: 0 Output Data Ready */ 137 uint32_t :15; /*!< bit: 1..15 Reserved */ 138 uint32_t IBUFRDY:1; /*!< bit: 16 Input Buffer Ready */ 139 uint32_t :15; /*!< bit: 17..31 Reserved */ 140 } bit; /*!< Structure used for bit access */ 141 uint32_t reg; /*!< Type used for register access */ 142 } AESA_SR_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 #define AESA_SR_OFFSET 0x0C /**< \brief (AESA_SR offset) Status Register */ 146 #define AESA_SR_RESETVALUE _U_(0x00010000); /**< \brief (AESA_SR reset_value) Status Register */ 147 148 #define AESA_SR_ODATARDY_Pos 0 /**< \brief (AESA_SR) Output Data Ready */ 149 #define AESA_SR_ODATARDY (_U_(0x1) << AESA_SR_ODATARDY_Pos) 150 #define AESA_SR_IBUFRDY_Pos 16 /**< \brief (AESA_SR) Input Buffer Ready */ 151 #define AESA_SR_IBUFRDY (_U_(0x1) << AESA_SR_IBUFRDY_Pos) 152 #define AESA_SR_MASK _U_(0x00010001) /**< \brief (AESA_SR) MASK Register */ 153 154 /* -------- AESA_IER : (AESA Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { 157 struct { 158 uint32_t ODATARDY:1; /*!< bit: 0 Output Data Ready Interrupt Enable */ 159 uint32_t :15; /*!< bit: 1..15 Reserved */ 160 uint32_t IBUFRDY:1; /*!< bit: 16 Input Buffer Ready Interrupt Enable */ 161 uint32_t :15; /*!< bit: 17..31 Reserved */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } AESA_IER_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define AESA_IER_OFFSET 0x10 /**< \brief (AESA_IER offset) Interrupt Enable Register */ 168 #define AESA_IER_RESETVALUE _U_(0x00000000); /**< \brief (AESA_IER reset_value) Interrupt Enable Register */ 169 170 #define AESA_IER_ODATARDY_Pos 0 /**< \brief (AESA_IER) Output Data Ready Interrupt Enable */ 171 #define AESA_IER_ODATARDY (_U_(0x1) << AESA_IER_ODATARDY_Pos) 172 #define AESA_IER_IBUFRDY_Pos 16 /**< \brief (AESA_IER) Input Buffer Ready Interrupt Enable */ 173 #define AESA_IER_IBUFRDY (_U_(0x1) << AESA_IER_IBUFRDY_Pos) 174 #define AESA_IER_MASK _U_(0x00010001) /**< \brief (AESA_IER) MASK Register */ 175 176 /* -------- AESA_IDR : (AESA Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ 177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 178 typedef union { 179 struct { 180 uint32_t ODATARDY:1; /*!< bit: 0 Output Data Ready Interrupt Disable */ 181 uint32_t :15; /*!< bit: 1..15 Reserved */ 182 uint32_t IBUFRDY:1; /*!< bit: 16 Input Buffer Ready Interrupt Disable */ 183 uint32_t :15; /*!< bit: 17..31 Reserved */ 184 } bit; /*!< Structure used for bit access */ 185 uint32_t reg; /*!< Type used for register access */ 186 } AESA_IDR_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 #define AESA_IDR_OFFSET 0x14 /**< \brief (AESA_IDR offset) Interrupt Disable Register */ 190 #define AESA_IDR_RESETVALUE _U_(0x00000000); /**< \brief (AESA_IDR reset_value) Interrupt Disable Register */ 191 192 #define AESA_IDR_ODATARDY_Pos 0 /**< \brief (AESA_IDR) Output Data Ready Interrupt Disable */ 193 #define AESA_IDR_ODATARDY (_U_(0x1) << AESA_IDR_ODATARDY_Pos) 194 #define AESA_IDR_IBUFRDY_Pos 16 /**< \brief (AESA_IDR) Input Buffer Ready Interrupt Disable */ 195 #define AESA_IDR_IBUFRDY (_U_(0x1) << AESA_IDR_IBUFRDY_Pos) 196 #define AESA_IDR_MASK _U_(0x00010001) /**< \brief (AESA_IDR) MASK Register */ 197 198 /* -------- AESA_IMR : (AESA Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 200 typedef union { 201 struct { 202 uint32_t ODATARDY:1; /*!< bit: 0 Output Data Ready Interrupt Mask */ 203 uint32_t :15; /*!< bit: 1..15 Reserved */ 204 uint32_t IBUFRDY:1; /*!< bit: 16 Input Buffer Ready Interrupt Mask */ 205 uint32_t :15; /*!< bit: 17..31 Reserved */ 206 } bit; /*!< Structure used for bit access */ 207 uint32_t reg; /*!< Type used for register access */ 208 } AESA_IMR_Type; 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 210 211 #define AESA_IMR_OFFSET 0x18 /**< \brief (AESA_IMR offset) Interrupt Mask Register */ 212 #define AESA_IMR_RESETVALUE _U_(0x00000000); /**< \brief (AESA_IMR reset_value) Interrupt Mask Register */ 213 214 #define AESA_IMR_ODATARDY_Pos 0 /**< \brief (AESA_IMR) Output Data Ready Interrupt Mask */ 215 #define AESA_IMR_ODATARDY (_U_(0x1) << AESA_IMR_ODATARDY_Pos) 216 #define AESA_IMR_IBUFRDY_Pos 16 /**< \brief (AESA_IMR) Input Buffer Ready Interrupt Mask */ 217 #define AESA_IMR_IBUFRDY (_U_(0x1) << AESA_IMR_IBUFRDY_Pos) 218 #define AESA_IMR_MASK _U_(0x00010001) /**< \brief (AESA_IMR) MASK Register */ 219 220 /* -------- AESA_KEY : (AESA Offset: 0x20) ( /W 32) KEY Key Register -------- */ 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 222 typedef union { 223 struct { 224 uint32_t KEY0:32; /*!< bit: 0..31 Key Word 0 */ 225 } bit; /*!< Structure used for bit access */ 226 uint32_t reg; /*!< Type used for register access */ 227 } AESA_KEY_Type; 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define AESA_KEY_OFFSET 0x20 /**< \brief (AESA_KEY offset) Key Register */ 231 #define AESA_KEY_RESETVALUE _U_(0x00000000); /**< \brief (AESA_KEY reset_value) Key Register */ 232 233 #define AESA_KEY_KEY0_Pos 0 /**< \brief (AESA_KEY) Key Word 0 */ 234 #define AESA_KEY_KEY0_Msk (_U_(0xFFFFFFFF) << AESA_KEY_KEY0_Pos) 235 #define AESA_KEY_KEY0(value) (AESA_KEY_KEY0_Msk & ((value) << AESA_KEY_KEY0_Pos)) 236 #define AESA_KEY_MASK _U_(0xFFFFFFFF) /**< \brief (AESA_KEY) MASK Register */ 237 238 /* -------- AESA_INITVECT : (AESA Offset: 0x40) ( /W 32) INITVECT Initialization Vector Register -------- */ 239 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 240 typedef union { 241 struct { 242 uint32_t INITVECT0:32; /*!< bit: 0..31 Initialization Vector Word 0 */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } AESA_INITVECT_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define AESA_INITVECT_OFFSET 0x40 /**< \brief (AESA_INITVECT offset) Initialization Vector Register */ 249 #define AESA_INITVECT_RESETVALUE _U_(0x00000000); /**< \brief (AESA_INITVECT reset_value) Initialization Vector Register */ 250 251 #define AESA_INITVECT_INITVECT0_Pos 0 /**< \brief (AESA_INITVECT) Initialization Vector Word 0 */ 252 #define AESA_INITVECT_INITVECT0_Msk (_U_(0xFFFFFFFF) << AESA_INITVECT_INITVECT0_Pos) 253 #define AESA_INITVECT_INITVECT0(value) (AESA_INITVECT_INITVECT0_Msk & ((value) << AESA_INITVECT_INITVECT0_Pos)) 254 #define AESA_INITVECT_MASK _U_(0xFFFFFFFF) /**< \brief (AESA_INITVECT) MASK Register */ 255 256 /* -------- AESA_IDATA : (AESA Offset: 0x50) ( /W 32) Input Data Register -------- */ 257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 258 typedef union { 259 struct { 260 uint32_t IDATA:32; /*!< bit: 0..31 Input Data */ 261 } bit; /*!< Structure used for bit access */ 262 uint32_t reg; /*!< Type used for register access */ 263 } AESA_IDATA_Type; 264 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 265 266 #define AESA_IDATA_OFFSET 0x50 /**< \brief (AESA_IDATA offset) Input Data Register */ 267 #define AESA_IDATA_RESETVALUE _U_(0x00000000); /**< \brief (AESA_IDATA reset_value) Input Data Register */ 268 269 #define AESA_IDATA_IDATA_Pos 0 /**< \brief (AESA_IDATA) Input Data */ 270 #define AESA_IDATA_IDATA_Msk (_U_(0xFFFFFFFF) << AESA_IDATA_IDATA_Pos) 271 #define AESA_IDATA_IDATA(value) (AESA_IDATA_IDATA_Msk & ((value) << AESA_IDATA_IDATA_Pos)) 272 #define AESA_IDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AESA_IDATA) MASK Register */ 273 274 /* -------- AESA_ODATA : (AESA Offset: 0x60) (R/ 32) Output Data Register -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 struct { 278 uint32_t ODATA:32; /*!< bit: 0..31 Output Data */ 279 } bit; /*!< Structure used for bit access */ 280 uint32_t reg; /*!< Type used for register access */ 281 } AESA_ODATA_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define AESA_ODATA_OFFSET 0x60 /**< \brief (AESA_ODATA offset) Output Data Register */ 285 #define AESA_ODATA_RESETVALUE _U_(0x00000000); /**< \brief (AESA_ODATA reset_value) Output Data Register */ 286 287 #define AESA_ODATA_ODATA_Pos 0 /**< \brief (AESA_ODATA) Output Data */ 288 #define AESA_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << AESA_ODATA_ODATA_Pos) 289 #define AESA_ODATA_ODATA(value) (AESA_ODATA_ODATA_Msk & ((value) << AESA_ODATA_ODATA_Pos)) 290 #define AESA_ODATA_MASK _U_(0xFFFFFFFF) /**< \brief (AESA_ODATA) MASK Register */ 291 292 /* -------- AESA_DRNGSEED : (AESA Offset: 0x70) ( /W 32) DRNG Seed Register -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t SEED:32; /*!< bit: 0..31 DRNG Seed */ 297 } bit; /*!< Structure used for bit access */ 298 uint32_t reg; /*!< Type used for register access */ 299 } AESA_DRNGSEED_Type; 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 301 302 #define AESA_DRNGSEED_OFFSET 0x70 /**< \brief (AESA_DRNGSEED offset) DRNG Seed Register */ 303 #define AESA_DRNGSEED_RESETVALUE _U_(0x00000000); /**< \brief (AESA_DRNGSEED reset_value) DRNG Seed Register */ 304 305 #define AESA_DRNGSEED_SEED_Pos 0 /**< \brief (AESA_DRNGSEED) DRNG Seed */ 306 #define AESA_DRNGSEED_SEED_Msk (_U_(0xFFFFFFFF) << AESA_DRNGSEED_SEED_Pos) 307 #define AESA_DRNGSEED_SEED(value) (AESA_DRNGSEED_SEED_Msk & ((value) << AESA_DRNGSEED_SEED_Pos)) 308 #define AESA_DRNGSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AESA_DRNGSEED) MASK Register */ 309 310 /* -------- AESA_PARAMETER : (AESA Offset: 0xF8) (R/ 32) Parameter Register -------- */ 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 312 typedef union { 313 struct { 314 uint32_t KEYSIZE:2; /*!< bit: 0.. 1 Maximum Key Size */ 315 uint32_t OPMODE:3; /*!< bit: 2.. 4 Maximum Number of Confidentiality Modes of Operation */ 316 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 317 uint32_t CTRMEAS:1; /*!< bit: 8 Countermeasures */ 318 uint32_t :23; /*!< bit: 9..31 Reserved */ 319 } bit; /*!< Structure used for bit access */ 320 uint32_t reg; /*!< Type used for register access */ 321 } AESA_PARAMETER_Type; 322 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 323 324 #define AESA_PARAMETER_OFFSET 0xF8 /**< \brief (AESA_PARAMETER offset) Parameter Register */ 325 #define AESA_PARAMETER_RESETVALUE _U_(0x00000112); /**< \brief (AESA_PARAMETER reset_value) Parameter Register */ 326 327 #define AESA_PARAMETER_KEYSIZE_Pos 0 /**< \brief (AESA_PARAMETER) Maximum Key Size */ 328 #define AESA_PARAMETER_KEYSIZE_Msk (_U_(0x3) << AESA_PARAMETER_KEYSIZE_Pos) 329 #define AESA_PARAMETER_KEYSIZE(value) (AESA_PARAMETER_KEYSIZE_Msk & ((value) << AESA_PARAMETER_KEYSIZE_Pos)) 330 #define AESA_PARAMETER_OPMODE_Pos 2 /**< \brief (AESA_PARAMETER) Maximum Number of Confidentiality Modes of Operation */ 331 #define AESA_PARAMETER_OPMODE_Msk (_U_(0x7) << AESA_PARAMETER_OPMODE_Pos) 332 #define AESA_PARAMETER_OPMODE(value) (AESA_PARAMETER_OPMODE_Msk & ((value) << AESA_PARAMETER_OPMODE_Pos)) 333 #define AESA_PARAMETER_CTRMEAS_Pos 8 /**< \brief (AESA_PARAMETER) Countermeasures */ 334 #define AESA_PARAMETER_CTRMEAS (_U_(0x1) << AESA_PARAMETER_CTRMEAS_Pos) 335 #define AESA_PARAMETER_MASK _U_(0x0000011F) /**< \brief (AESA_PARAMETER) MASK Register */ 336 337 /* -------- AESA_VERSION : (AESA Offset: 0xFC) (R/ 32) Version Register -------- */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef union { 340 struct { 341 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 342 uint32_t :4; /*!< bit: 12..15 Reserved */ 343 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 344 uint32_t :12; /*!< bit: 20..31 Reserved */ 345 } bit; /*!< Structure used for bit access */ 346 uint32_t reg; /*!< Type used for register access */ 347 } AESA_VERSION_Type; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define AESA_VERSION_OFFSET 0xFC /**< \brief (AESA_VERSION offset) Version Register */ 351 #define AESA_VERSION_RESETVALUE _U_(0x00000102); /**< \brief (AESA_VERSION reset_value) Version Register */ 352 353 #define AESA_VERSION_VERSION_Pos 0 /**< \brief (AESA_VERSION) Version Number */ 354 #define AESA_VERSION_VERSION_Msk (_U_(0xFFF) << AESA_VERSION_VERSION_Pos) 355 #define AESA_VERSION_VERSION(value) (AESA_VERSION_VERSION_Msk & ((value) << AESA_VERSION_VERSION_Pos)) 356 #define AESA_VERSION_VARIANT_Pos 16 /**< \brief (AESA_VERSION) Variant Number */ 357 #define AESA_VERSION_VARIANT_Msk (_U_(0xF) << AESA_VERSION_VARIANT_Pos) 358 #define AESA_VERSION_VARIANT(value) (AESA_VERSION_VARIANT_Msk & ((value) << AESA_VERSION_VARIANT_Pos)) 359 #define AESA_VERSION_MASK _U_(0x000F0FFF) /**< \brief (AESA_VERSION) MASK Register */ 360 361 /** \brief AesaInitvect hardware registers */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef union { 364 struct { 365 __O AESA_INITVECT_Type INITVECT; /**< \brief Offset: 0x00 ( /W 32) Initialization Vector Register */ 366 } bf; 367 struct { 368 WoReg AESA_INITVECT; /**< \brief (AESA Offset: 0x00) Initialization Vector Register */ 369 } reg; 370 } AesaInitvect; 371 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 372 373 /** \brief AesaKey hardware registers */ 374 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 375 typedef union { 376 struct { 377 __O AESA_KEY_Type KEY; /**< \brief Offset: 0x00 ( /W 32) Key Register */ 378 } bf; 379 struct { 380 WoReg AESA_KEY; /**< \brief (AESA Offset: 0x00) Key Register */ 381 } reg; 382 } AesaKey; 383 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 384 385 /** \brief AESA hardware registers */ 386 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 387 typedef struct { 388 __IO uint32_t CTRL; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 389 __IO uint32_t MODE; /**< \brief Offset: 0x04 (R/W 32) Mode Register */ 390 __IO uint32_t DATABUFPTR; /**< \brief Offset: 0x08 (R/W 32) Data Buffer Pointer Register */ 391 __I uint32_t SR; /**< \brief Offset: 0x0C (R/ 32) Status Register */ 392 __O uint32_t IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable Register */ 393 __O uint32_t IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable Register */ 394 __I uint32_t IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask Register */ 395 RoReg8 Reserved1[0x4]; 396 __O uint32_t Key[8]; /**< \brief Offset: 0x20 AesaKey groups */ 397 __O uint32_t Initvect[4]; /**< \brief Offset: 0x40 AesaInitvect groups */ 398 __O uint32_t IDATA; /**< \brief Offset: 0x50 ( /W 32) Input Data Register */ 399 RoReg8 Reserved2[0xC]; 400 __I uint32_t ODATA; /**< \brief Offset: 0x60 (R/ 32) Output Data Register */ 401 RoReg8 Reserved3[0xC]; 402 __O uint32_t DRNGSEED; /**< \brief Offset: 0x70 ( /W 32) DRNG Seed Register */ 403 RoReg8 Reserved4[0x84]; 404 __I uint32_t PARAMETER; /**< \brief Offset: 0xF8 (R/ 32) Parameter Register */ 405 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 406 } Aesa; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 /*@}*/ 410 411 #endif /* _SAM4L_AESA_COMPONENT_ */ 412
