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Searched refs:PWM_IMR1_CHID0 (Results 1 – 7 of 7) sorted by relevance

/hal_atmel-3.7.0/asf/sam/include/sam4s/component/
Dpwm.h184 #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask… macro
/hal_atmel-3.7.0/asf/sam/include/sam4e/component/
Dpwm.h199 #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask… macro
/hal_atmel-3.7.0/asf/sam/include/sam3x/component/
Dpwm.h213 #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask… macro
/hal_atmel-3.7.0/asf/sam/include/same70/component/
Dpwm.h796 #define PWM_IMR1_CHID0 PWM_IMR1_CHID0_Msk /**< \de… macro
/hal_atmel-3.7.0/asf/sam/include/samv71b/component/
Dpwm.h816 #define PWM_IMR1_CHID0 PWM_IMR1_CHID0_Msk /**< \de… macro
/hal_atmel-3.7.0/asf/sam/include/samv71/component/
Dpwm.h796 #define PWM_IMR1_CHID0 PWM_IMR1_CHID0_Msk /**< \de… macro
/hal_atmel-3.7.0/asf/sam/include/same70b/component/
Dpwm.h816 #define PWM_IMR1_CHID0 PWM_IMR1_CHID0_Msk /**< \de… macro