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Searched refs:nm_write_reg (Results 1 – 8 of 8) sorted by relevance

/hal_atmel-3.6.0/asf/common/components/wifi/winc1500/spi_flash/source/
Dspi_flash.c103 ret += nm_write_reg(SPI_FLASH_DATA_CNT, 4); in spi_flash_read_status_reg()
104 ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); in spi_flash_read_status_reg()
105 ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); in spi_flash_read_status_reg()
106 ret += nm_write_reg(SPI_FLASH_DMA_ADDR, DUMMY_REGISTER); in spi_flash_read_status_reg()
107 ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); in spi_flash_read_status_reg()
137 ret += nm_write_reg(SPI_FLASH_DATA_CNT, 1); in spi_flash_read_security_reg()
138 ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); in spi_flash_read_security_reg()
139 ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); in spi_flash_read_security_reg()
140 ret += nm_write_reg(SPI_FLASH_DMA_ADDR, DUMMY_REGISTER); in spi_flash_read_security_reg()
141 ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); in spi_flash_read_security_reg()
[all …]
/hal_atmel-3.6.0/asf/common/components/wifi/winc1500/driver/source/
Dm2m_ate_mode.c200 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); in m2m_ate_set_fw_state()
209 s8Ret = nm_write_reg(rNMI_BOOT_RESET_MUX, u32Val); in m2m_ate_set_fw_state()
219 s8Ret = nm_write_reg(0xc0000, 0x71); in m2m_ate_set_fw_state()
229 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); in m2m_ate_set_fw_state()
237 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); in m2m_ate_set_fw_state()
396 s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteTx->use_pmu); in m2m_ate_start_tx()
397 s8Ret += nm_write_reg(rBurstTx_NMI_TX_PHY_CONT, strM2mAteTx->phy_burst_tx); in m2m_ate_start_tx()
398 s8Ret += nm_write_reg(rBurstTx_NMI_NUM_TX_FRAMES, strM2mAteTx->num_frames); in m2m_ate_start_tx()
399 s8Ret += nm_write_reg(rBurstTx_NMI_TX_GAIN, strM2mAteTx->tx_gain_sel); in m2m_ate_start_tx()
400 s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteTx->channel_num); in m2m_ate_start_tx()
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Dnmasic.c90 nm_write_reg(rNMI_GP_REG_1, val32); in chip_apply_conf()
112 nm_write_reg(WAKE_CLK_REG, reg); in chip_idle()
127 ret = nm_write_reg(NMI_PIN_MUX_0, reg); in enable_interrupts()
137 ret = nm_write_reg(NMI_INTR_ENABLE, reg); in enable_interrupts()
150 ret = nm_write_reg(BOOTROM_REG,0); in cpu_start()
151 ret += nm_write_reg(NMI_STATE_REG,0); in cpu_start()
152 ret += nm_write_reg(NMI_REV_REG,0); in cpu_start()
158 ret += nm_write_reg(0x1118, reg); in cpu_start()
162 ret += nm_write_reg(NMI_GLB_RESET_0, reg); in cpu_start()
165 ret += nm_write_reg(NMI_GLB_RESET_0, reg); in cpu_start()
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Dm2m_crypto.c271 nm_write_reg(SHA256_CTRL, u32RegVal); in m2m_crypto_sha256_hash_update()
273 nm_write_reg(SHA256_CTRL, u32RegVal); in m2m_crypto_sha256_hash_update()
282 nm_write_reg(SHA256_DATA_LENGTH, (u32NBlocks * SHA_BLOCK_SIZE)); in m2m_crypto_sha256_hash_update()
283 nm_write_reg(SHA256_START_RD_ADDR, u32WriteAddr); in m2m_crypto_sha256_hash_update()
284 nm_write_reg(SHA256_START_WR_ADDR, u32ReadAddr); in m2m_crypto_sha256_hash_update()
291 nm_write_reg(SHA256_CTRL, u32RegVal); in m2m_crypto_sha256_hash_update()
327 nm_write_reg(SHA256_CTRL,u32RegVal); in m2m_crypto_sha256_hash_finish()
329 nm_write_reg(SHA256_CTRL,u32RegVal); in m2m_crypto_sha256_hash_finish()
365 nm_write_reg(SHA256_DATA_LENGTH, (u16NBlocks * SHA_BLOCK_SIZE)); in m2m_crypto_sha256_hash_finish()
366 nm_write_reg(SHA256_START_RD_ADDR, u32WriteAddr); in m2m_crypto_sha256_hash_finish()
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Dm2m_hif.c107 ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg); in hif_set_rx_done()
323 ret = nm_write_reg(NMI_STATE_REG,reg); in hif_send()
328 ret = nm_write_reg(WIFI_HOST_RCV_CTRL_2, reg); in hif_send()
336 ret = nm_write_reg(WIFI_HOST_RCV_CTRL_2, reg); in hif_send()
392 ret = nm_write_reg(WIFI_HOST_RCV_CTRL_3, reg); in hif_send()
443 ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg); in hif_isr()
Dnmbus.h112 sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val);
Dnmbus.c178 sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val) in nm_write_reg() function
Dnmdrv.c263 nm_write_reg(0x20300,0); in nm_drv_init_download_mode()