1 /** 2 * \file 3 * 4 * \brief Instance description for WDT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_WDT_INSTANCE_ 30 #define _SAM4L_WDT_INSTANCE_ 31 32 /* ========== Register definition for WDT peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_WDT_CTRL (0x400F0C00) /**< \brief (WDT) Control Register */ 35 #define REG_WDT_CLR (0x400F0C04) /**< \brief (WDT) Clear Register */ 36 #define REG_WDT_SR (0x400F0C08) /**< \brief (WDT) Status Register */ 37 #define REG_WDT_IER (0x400F0C0C) /**< \brief (WDT) Interrupt Enable Register */ 38 #define REG_WDT_IDR (0x400F0C10) /**< \brief (WDT) Interrupt Disable Register */ 39 #define REG_WDT_IMR (0x400F0C14) /**< \brief (WDT) Interrupt Mask Register */ 40 #define REG_WDT_ISR (0x400F0C18) /**< \brief (WDT) Interrupt Status Register */ 41 #define REG_WDT_ICR (0x400F0C1C) /**< \brief (WDT) Interrupt Clear Register */ 42 #define REG_WDT_VERSION (0x400F0FFC) /**< \brief (WDT) Version Register */ 43 #else 44 #define REG_WDT_CTRL (*(RwReg *)0x400F0C00UL) /**< \brief (WDT) Control Register */ 45 #define REG_WDT_CLR (*(WoReg *)0x400F0C04UL) /**< \brief (WDT) Clear Register */ 46 #define REG_WDT_SR (*(RoReg *)0x400F0C08UL) /**< \brief (WDT) Status Register */ 47 #define REG_WDT_IER (*(WoReg *)0x400F0C0CUL) /**< \brief (WDT) Interrupt Enable Register */ 48 #define REG_WDT_IDR (*(WoReg *)0x400F0C10UL) /**< \brief (WDT) Interrupt Disable Register */ 49 #define REG_WDT_IMR (*(RoReg *)0x400F0C14UL) /**< \brief (WDT) Interrupt Mask Register */ 50 #define REG_WDT_ISR (*(RoReg *)0x400F0C18UL) /**< \brief (WDT) Interrupt Status Register */ 51 #define REG_WDT_ICR (*(WoReg *)0x400F0C1CUL) /**< \brief (WDT) Interrupt Clear Register */ 52 #define REG_WDT_VERSION (*(RoReg *)0x400F0FFCUL) /**< \brief (WDT) Version Register */ 53 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 /* ========== Instance parameters for WDT peripheral ========== */ 56 #define WDT_WDT_KEY_CONST 85 57 58 #endif /* _SAM4L_WDT_INSTANCE_ */ 59
