1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_USART_COMPONENT_ 31 #define _SAM3XA_USART_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Usart hardware registers */ 41 typedef struct { 42 __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ 43 __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ 44 __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ 45 __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ 46 __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ 47 __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ 48 __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ 49 __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ 50 __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ 51 __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ 52 __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ 53 __I uint32_t Reserved1[5]; 54 __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ 55 __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ 56 __I uint32_t Reserved2[1]; 57 __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ 58 __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ 59 __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ 60 __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ 61 __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ 62 __I uint32_t Reserved3[33]; 63 __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ 64 __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ 65 __I uint32_t Reserved4[5]; 66 __IO uint32_t US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ 67 __IO uint32_t US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ 68 __IO uint32_t US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ 69 __IO uint32_t US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ 70 __IO uint32_t US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ 71 __IO uint32_t US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ 72 __IO uint32_t US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ 73 __IO uint32_t US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ 74 __O uint32_t US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ 75 __I uint32_t US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ 76 } Usart; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ 79 #define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ 80 #define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ 81 #define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ 82 #define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ 83 #define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ 84 #define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ 85 #define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ 86 #define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ 87 #define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ 88 #define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ 89 #define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ 90 #define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ 91 #define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ 92 #define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ 93 #define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ 94 #define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ 95 #define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ 96 #define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ 97 #define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ 98 #define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ 99 /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ 100 #define US_MR_USART_MODE_Pos 0 101 #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ 102 #define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ 103 #define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ 104 #define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ 105 #define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ 106 #define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ 107 #define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ 108 #define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN master */ 109 #define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */ 110 #define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ 111 #define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ 112 #define US_MR_USCLKS_Pos 4 113 #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ 114 #define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) master Clock MCK is selected */ 115 #define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ 116 #define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ 117 #define US_MR_CHRL_Pos 6 118 #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ 119 #define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ 120 #define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ 121 #define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ 122 #define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ 123 #define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ 124 #define US_MR_PAR_Pos 9 125 #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ 126 #define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ 127 #define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ 128 #define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ 129 #define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ 130 #define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ 131 #define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ 132 #define US_MR_NBSTOP_Pos 12 133 #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ 134 #define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ 135 #define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ 136 #define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ 137 #define US_MR_CHMODE_Pos 14 138 #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ 139 #define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ 140 #define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ 141 #define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ 142 #define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ 143 #define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ 144 #define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ 145 #define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ 146 #define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ 147 #define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ 148 #define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ 149 #define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ 150 #define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ 151 #define US_MR_MAX_ITERATION_Pos 24 152 #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ 153 #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) 154 #define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ 155 #define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ 156 #define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ 157 #define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ 158 #define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ 159 #define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ 160 #define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ 161 /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ 162 #define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ 163 #define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ 164 #define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ 165 #define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */ 166 #define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */ 167 #define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ 168 #define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ 169 #define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ 170 #define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ 171 #define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ 172 #define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ 173 #define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */ 174 #define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */ 175 #define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ 176 #define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ 177 #define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ 178 #define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ 179 #define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ 180 #define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ 181 #define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ 182 #define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ 183 #define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ 184 #define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ 185 #define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ 186 #define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ 187 /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ 188 #define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ 189 #define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ 190 #define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ 191 #define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */ 192 #define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */ 193 #define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ 194 #define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ 195 #define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ 196 #define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ 197 #define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ 198 #define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ 199 #define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */ 200 #define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */ 201 #define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ 202 #define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ 203 #define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ 204 #define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ 205 #define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ 206 #define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ 207 #define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ 208 #define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ 209 #define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ 210 #define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ 211 #define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ 212 #define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ 213 /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ 214 #define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ 215 #define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ 216 #define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ 217 #define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */ 218 #define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */ 219 #define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ 220 #define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ 221 #define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ 222 #define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ 223 #define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ 224 #define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ 225 #define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */ 226 #define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */ 227 #define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ 228 #define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ 229 #define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ 230 #define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ 231 #define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ 232 #define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ 233 #define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ 234 #define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ 235 #define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ 236 #define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ 237 #define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ 238 #define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ 239 /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ 240 #define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ 241 #define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ 242 #define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ 243 #define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ 244 #define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ 245 #define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ 246 #define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ 247 #define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ 248 #define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ 249 #define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ 250 #define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */ 251 #define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ 252 #define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ 253 #define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */ 254 #define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ 255 #define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ 256 #define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ 257 #define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */ 258 #define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */ 259 #define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */ 260 #define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */ 261 #define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ 262 #define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */ 263 #define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */ 264 #define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */ 265 #define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */ 266 #define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */ 267 /* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ 268 #define US_RHR_RXCHR_Pos 0 269 #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ 270 #define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ 271 /* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ 272 #define US_THR_TXCHR_Pos 0 273 #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ 274 #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) 275 #define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ 276 /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ 277 #define US_BRGR_CD_Pos 0 278 #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ 279 #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) 280 #define US_BRGR_FP_Pos 16 281 #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ 282 #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) 283 /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ 284 #define US_RTOR_TO_Pos 0 285 #define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ 286 #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) 287 /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ 288 #define US_TTGR_TG_Pos 0 289 #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ 290 #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) 291 /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ 292 #define US_FIDI_FI_DI_RATIO_Pos 0 293 #define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ 294 #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) 295 /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ 296 #define US_NER_NB_ERRORS_Pos 0 297 #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ 298 /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ 299 #define US_IF_IRDA_FILTER_Pos 0 300 #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ 301 #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) 302 /* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ 303 #define US_MAN_TX_PL_Pos 0 304 #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ 305 #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) 306 #define US_MAN_TX_PP_Pos 8 307 #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ 308 #define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ 309 #define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ 310 #define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ 311 #define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ 312 #define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ 313 #define US_MAN_RX_PL_Pos 16 314 #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ 315 #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) 316 #define US_MAN_RX_PP_Pos 24 317 #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ 318 #define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ 319 #define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ 320 #define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ 321 #define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ 322 #define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ 323 #define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ 324 #define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ 325 /* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ 326 #define US_LINMR_NACT_Pos 0 327 #define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ 328 #define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ 329 #define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ 330 #define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ 331 #define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ 332 #define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ 333 #define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ 334 #define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ 335 #define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ 336 #define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ 337 #define US_LINMR_DLC_Pos 8 338 #define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ 339 #define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) 340 #define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */ 341 /* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ 342 #define US_LINIR_IDCHR_Pos 0 343 #define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ 344 #define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) 345 /* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ 346 #define US_LINBRR_LINCD_Pos 0 347 #define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ 348 #define US_LINBRR_LINFP_Pos 16 349 #define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ 350 /* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ 351 #define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ 352 #define US_WPMR_WPKEY_Pos 8 353 #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ 354 #define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ 355 /* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ 356 #define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ 357 #define US_WPSR_WPVSRC_Pos 8 358 #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ 359 /* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ 360 #define US_RPR_RXPTR_Pos 0 361 #define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ 362 #define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) 363 /* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ 364 #define US_RCR_RXCTR_Pos 0 365 #define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ 366 #define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) 367 /* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ 368 #define US_TPR_TXPTR_Pos 0 369 #define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ 370 #define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) 371 /* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ 372 #define US_TCR_TXCTR_Pos 0 373 #define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ 374 #define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) 375 /* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ 376 #define US_RNPR_RXNPTR_Pos 0 377 #define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ 378 #define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) 379 /* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ 380 #define US_RNCR_RXNCTR_Pos 0 381 #define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ 382 #define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) 383 /* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ 384 #define US_TNPR_TXNPTR_Pos 0 385 #define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ 386 #define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) 387 /* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ 388 #define US_TNCR_TXNCTR_Pos 0 389 #define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ 390 #define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) 391 /* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ 392 #define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ 393 #define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ 394 #define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ 395 #define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ 396 /* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ 397 #define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ 398 #define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ 399 400 /*@}*/ 401 402 403 #endif /* _SAM3XA_USART_COMPONENT_ */ 404
