1 /** 2 * \file 3 * 4 * \brief Instance description for TWIS0 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TWIS0_INSTANCE_ 30 #define _SAM4L_TWIS0_INSTANCE_ 31 32 /* ========== Register definition for TWIS0 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TWIS0_CR (0x40018400) /**< \brief (TWIS0) Control Register */ 35 #define REG_TWIS0_NBYTES (0x40018404) /**< \brief (TWIS0) NBYTES Register */ 36 #define REG_TWIS0_TR (0x40018408) /**< \brief (TWIS0) Timing Register */ 37 #define REG_TWIS0_RHR (0x4001840C) /**< \brief (TWIS0) Receive Holding Register */ 38 #define REG_TWIS0_THR (0x40018410) /**< \brief (TWIS0) Transmit Holding Register */ 39 #define REG_TWIS0_PECR (0x40018414) /**< \brief (TWIS0) Packet Error Check Register */ 40 #define REG_TWIS0_SR (0x40018418) /**< \brief (TWIS0) Status Register */ 41 #define REG_TWIS0_IER (0x4001841C) /**< \brief (TWIS0) Interrupt Enable Register */ 42 #define REG_TWIS0_IDR (0x40018420) /**< \brief (TWIS0) Interrupt Disable Register */ 43 #define REG_TWIS0_IMR (0x40018424) /**< \brief (TWIS0) Interrupt Mask Register */ 44 #define REG_TWIS0_SCR (0x40018428) /**< \brief (TWIS0) Status Clear Register */ 45 #define REG_TWIS0_PR (0x4001842C) /**< \brief (TWIS0) Parameter Register */ 46 #define REG_TWIS0_VR (0x40018430) /**< \brief (TWIS0) Version Register */ 47 #define REG_TWIS0_HSTR (0x40018434) /**< \brief (TWIS0) HS-mode Timing Register */ 48 #define REG_TWIS0_SRR (0x40018438) /**< \brief (TWIS0) Slew Rate Register */ 49 #define REG_TWIS0_HSSRR (0x4001843C) /**< \brief (TWIS0) HS-mode Slew Rate Register */ 50 #else 51 #define REG_TWIS0_CR (*(RwReg *)0x40018400UL) /**< \brief (TWIS0) Control Register */ 52 #define REG_TWIS0_NBYTES (*(RwReg *)0x40018404UL) /**< \brief (TWIS0) NBYTES Register */ 53 #define REG_TWIS0_TR (*(RwReg *)0x40018408UL) /**< \brief (TWIS0) Timing Register */ 54 #define REG_TWIS0_RHR (*(RoReg *)0x4001840CUL) /**< \brief (TWIS0) Receive Holding Register */ 55 #define REG_TWIS0_THR (*(WoReg *)0x40018410UL) /**< \brief (TWIS0) Transmit Holding Register */ 56 #define REG_TWIS0_PECR (*(RoReg *)0x40018414UL) /**< \brief (TWIS0) Packet Error Check Register */ 57 #define REG_TWIS0_SR (*(RoReg *)0x40018418UL) /**< \brief (TWIS0) Status Register */ 58 #define REG_TWIS0_IER (*(WoReg *)0x4001841CUL) /**< \brief (TWIS0) Interrupt Enable Register */ 59 #define REG_TWIS0_IDR (*(WoReg *)0x40018420UL) /**< \brief (TWIS0) Interrupt Disable Register */ 60 #define REG_TWIS0_IMR (*(RoReg *)0x40018424UL) /**< \brief (TWIS0) Interrupt Mask Register */ 61 #define REG_TWIS0_SCR (*(WoReg *)0x40018428UL) /**< \brief (TWIS0) Status Clear Register */ 62 #define REG_TWIS0_PR (*(RoReg *)0x4001842CUL) /**< \brief (TWIS0) Parameter Register */ 63 #define REG_TWIS0_VR (*(RoReg *)0x40018430UL) /**< \brief (TWIS0) Version Register */ 64 #define REG_TWIS0_HSTR (*(RwReg *)0x40018434UL) /**< \brief (TWIS0) HS-mode Timing Register */ 65 #define REG_TWIS0_SRR (*(RwReg *)0x40018438UL) /**< \brief (TWIS0) Slew Rate Register */ 66 #define REG_TWIS0_HSSRR (*(RwReg *)0x4001843CUL) /**< \brief (TWIS0) HS-mode Slew Rate Register */ 67 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* ========== Instance parameters for TWIS0 peripheral ========== */ 70 #define TWIS0_PDCA_ID_RX 9 71 #define TWIS0_PDCA_ID_TX 27 72 73 #endif /* _SAM4L_TWIS0_INSTANCE_ */ 74
