1 /** 2 * \file 3 * 4 * \brief Component description for TWIHS 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_TWIHS_COMPONENT_H_ 32 #define _SAMV71_TWIHS_COMPONENT_H_ 33 #define _SAMV71_TWIHS_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Two-wire Interface High Speed 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR TWIHS */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define TWIHS_11210 /**< (TWIHS) Module ID */ 46 #define REV_TWIHS X /**< (TWIHS) Module revision */ 47 48 /* -------- TWIHS_CR : (TWIHS Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t START:1; /**< bit: 0 Send a START Condition */ 54 uint32_t STOP:1; /**< bit: 1 Send a STOP Condition */ 55 uint32_t MSEN:1; /**< bit: 2 TWIHS Master Mode Enabled */ 56 uint32_t MSDIS:1; /**< bit: 3 TWIHS Master Mode Disabled */ 57 uint32_t SVEN:1; /**< bit: 4 TWIHS Slave Mode Enabled */ 58 uint32_t SVDIS:1; /**< bit: 5 TWIHS Slave Mode Disabled */ 59 uint32_t QUICK:1; /**< bit: 6 SMBus Quick Command */ 60 uint32_t SWRST:1; /**< bit: 7 Software Reset */ 61 uint32_t HSEN:1; /**< bit: 8 TWIHS High-Speed Mode Enabled */ 62 uint32_t HSDIS:1; /**< bit: 9 TWIHS High-Speed Mode Disabled */ 63 uint32_t SMBEN:1; /**< bit: 10 SMBus Mode Enabled */ 64 uint32_t SMBDIS:1; /**< bit: 11 SMBus Mode Disabled */ 65 uint32_t PECEN:1; /**< bit: 12 Packet Error Checking Enable */ 66 uint32_t PECDIS:1; /**< bit: 13 Packet Error Checking Disable */ 67 uint32_t PECRQ:1; /**< bit: 14 PEC Request */ 68 uint32_t CLEAR:1; /**< bit: 15 Bus CLEAR Command */ 69 uint32_t ACMEN:1; /**< bit: 16 Alternative Command Mode Enable */ 70 uint32_t ACMDIS:1; /**< bit: 17 Alternative Command Mode Disable */ 71 uint32_t :6; /**< bit: 18..23 Reserved */ 72 uint32_t THRCLR:1; /**< bit: 24 Transmit Holding Register Clear */ 73 uint32_t :1; /**< bit: 25 Reserved */ 74 uint32_t LOCKCLR:1; /**< bit: 26 Lock Clear */ 75 uint32_t :1; /**< bit: 27 Reserved */ 76 uint32_t FIFOEN:1; /**< bit: 28 FIFO Enable */ 77 uint32_t FIFODIS:1; /**< bit: 29 FIFO Disable */ 78 uint32_t :2; /**< bit: 30..31 Reserved */ 79 } bit; /**< Structure used for bit access */ 80 uint32_t reg; /**< Type used for register access */ 81 } TWIHS_CR_Type; 82 #endif 83 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 #define TWIHS_CR_OFFSET (0x00) /**< (TWIHS_CR) Control Register Offset */ 86 87 #define TWIHS_CR_START_Pos 0 /**< (TWIHS_CR) Send a START Condition Position */ 88 #define TWIHS_CR_START_Msk (_U_(0x1) << TWIHS_CR_START_Pos) /**< (TWIHS_CR) Send a START Condition Mask */ 89 #define TWIHS_CR_START TWIHS_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_START_Msk instead */ 90 #define TWIHS_CR_STOP_Pos 1 /**< (TWIHS_CR) Send a STOP Condition Position */ 91 #define TWIHS_CR_STOP_Msk (_U_(0x1) << TWIHS_CR_STOP_Pos) /**< (TWIHS_CR) Send a STOP Condition Mask */ 92 #define TWIHS_CR_STOP TWIHS_CR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_STOP_Msk instead */ 93 #define TWIHS_CR_MSEN_Pos 2 /**< (TWIHS_CR) TWIHS Master Mode Enabled Position */ 94 #define TWIHS_CR_MSEN_Msk (_U_(0x1) << TWIHS_CR_MSEN_Pos) /**< (TWIHS_CR) TWIHS Master Mode Enabled Mask */ 95 #define TWIHS_CR_MSEN TWIHS_CR_MSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSEN_Msk instead */ 96 #define TWIHS_CR_MSDIS_Pos 3 /**< (TWIHS_CR) TWIHS Master Mode Disabled Position */ 97 #define TWIHS_CR_MSDIS_Msk (_U_(0x1) << TWIHS_CR_MSDIS_Pos) /**< (TWIHS_CR) TWIHS Master Mode Disabled Mask */ 98 #define TWIHS_CR_MSDIS TWIHS_CR_MSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSDIS_Msk instead */ 99 #define TWIHS_CR_SVEN_Pos 4 /**< (TWIHS_CR) TWIHS Slave Mode Enabled Position */ 100 #define TWIHS_CR_SVEN_Msk (_U_(0x1) << TWIHS_CR_SVEN_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Mask */ 101 #define TWIHS_CR_SVEN TWIHS_CR_SVEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVEN_Msk instead */ 102 #define TWIHS_CR_SVDIS_Pos 5 /**< (TWIHS_CR) TWIHS Slave Mode Disabled Position */ 103 #define TWIHS_CR_SVDIS_Msk (_U_(0x1) << TWIHS_CR_SVDIS_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Mask */ 104 #define TWIHS_CR_SVDIS TWIHS_CR_SVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVDIS_Msk instead */ 105 #define TWIHS_CR_QUICK_Pos 6 /**< (TWIHS_CR) SMBus Quick Command Position */ 106 #define TWIHS_CR_QUICK_Msk (_U_(0x1) << TWIHS_CR_QUICK_Pos) /**< (TWIHS_CR) SMBus Quick Command Mask */ 107 #define TWIHS_CR_QUICK TWIHS_CR_QUICK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_QUICK_Msk instead */ 108 #define TWIHS_CR_SWRST_Pos 7 /**< (TWIHS_CR) Software Reset Position */ 109 #define TWIHS_CR_SWRST_Msk (_U_(0x1) << TWIHS_CR_SWRST_Pos) /**< (TWIHS_CR) Software Reset Mask */ 110 #define TWIHS_CR_SWRST TWIHS_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SWRST_Msk instead */ 111 #define TWIHS_CR_HSEN_Pos 8 /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Position */ 112 #define TWIHS_CR_HSEN_Msk (_U_(0x1) << TWIHS_CR_HSEN_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Mask */ 113 #define TWIHS_CR_HSEN TWIHS_CR_HSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSEN_Msk instead */ 114 #define TWIHS_CR_HSDIS_Pos 9 /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Position */ 115 #define TWIHS_CR_HSDIS_Msk (_U_(0x1) << TWIHS_CR_HSDIS_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Mask */ 116 #define TWIHS_CR_HSDIS TWIHS_CR_HSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSDIS_Msk instead */ 117 #define TWIHS_CR_SMBEN_Pos 10 /**< (TWIHS_CR) SMBus Mode Enabled Position */ 118 #define TWIHS_CR_SMBEN_Msk (_U_(0x1) << TWIHS_CR_SMBEN_Pos) /**< (TWIHS_CR) SMBus Mode Enabled Mask */ 119 #define TWIHS_CR_SMBEN TWIHS_CR_SMBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBEN_Msk instead */ 120 #define TWIHS_CR_SMBDIS_Pos 11 /**< (TWIHS_CR) SMBus Mode Disabled Position */ 121 #define TWIHS_CR_SMBDIS_Msk (_U_(0x1) << TWIHS_CR_SMBDIS_Pos) /**< (TWIHS_CR) SMBus Mode Disabled Mask */ 122 #define TWIHS_CR_SMBDIS TWIHS_CR_SMBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBDIS_Msk instead */ 123 #define TWIHS_CR_PECEN_Pos 12 /**< (TWIHS_CR) Packet Error Checking Enable Position */ 124 #define TWIHS_CR_PECEN_Msk (_U_(0x1) << TWIHS_CR_PECEN_Pos) /**< (TWIHS_CR) Packet Error Checking Enable Mask */ 125 #define TWIHS_CR_PECEN TWIHS_CR_PECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECEN_Msk instead */ 126 #define TWIHS_CR_PECDIS_Pos 13 /**< (TWIHS_CR) Packet Error Checking Disable Position */ 127 #define TWIHS_CR_PECDIS_Msk (_U_(0x1) << TWIHS_CR_PECDIS_Pos) /**< (TWIHS_CR) Packet Error Checking Disable Mask */ 128 #define TWIHS_CR_PECDIS TWIHS_CR_PECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECDIS_Msk instead */ 129 #define TWIHS_CR_PECRQ_Pos 14 /**< (TWIHS_CR) PEC Request Position */ 130 #define TWIHS_CR_PECRQ_Msk (_U_(0x1) << TWIHS_CR_PECRQ_Pos) /**< (TWIHS_CR) PEC Request Mask */ 131 #define TWIHS_CR_PECRQ TWIHS_CR_PECRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECRQ_Msk instead */ 132 #define TWIHS_CR_CLEAR_Pos 15 /**< (TWIHS_CR) Bus CLEAR Command Position */ 133 #define TWIHS_CR_CLEAR_Msk (_U_(0x1) << TWIHS_CR_CLEAR_Pos) /**< (TWIHS_CR) Bus CLEAR Command Mask */ 134 #define TWIHS_CR_CLEAR TWIHS_CR_CLEAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_CLEAR_Msk instead */ 135 #define TWIHS_CR_ACMEN_Pos 16 /**< (TWIHS_CR) Alternative Command Mode Enable Position */ 136 #define TWIHS_CR_ACMEN_Msk (_U_(0x1) << TWIHS_CR_ACMEN_Pos) /**< (TWIHS_CR) Alternative Command Mode Enable Mask */ 137 #define TWIHS_CR_ACMEN TWIHS_CR_ACMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMEN_Msk instead */ 138 #define TWIHS_CR_ACMDIS_Pos 17 /**< (TWIHS_CR) Alternative Command Mode Disable Position */ 139 #define TWIHS_CR_ACMDIS_Msk (_U_(0x1) << TWIHS_CR_ACMDIS_Pos) /**< (TWIHS_CR) Alternative Command Mode Disable Mask */ 140 #define TWIHS_CR_ACMDIS TWIHS_CR_ACMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMDIS_Msk instead */ 141 #define TWIHS_CR_THRCLR_Pos 24 /**< (TWIHS_CR) Transmit Holding Register Clear Position */ 142 #define TWIHS_CR_THRCLR_Msk (_U_(0x1) << TWIHS_CR_THRCLR_Pos) /**< (TWIHS_CR) Transmit Holding Register Clear Mask */ 143 #define TWIHS_CR_THRCLR TWIHS_CR_THRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_THRCLR_Msk instead */ 144 #define TWIHS_CR_LOCKCLR_Pos 26 /**< (TWIHS_CR) Lock Clear Position */ 145 #define TWIHS_CR_LOCKCLR_Msk (_U_(0x1) << TWIHS_CR_LOCKCLR_Pos) /**< (TWIHS_CR) Lock Clear Mask */ 146 #define TWIHS_CR_LOCKCLR TWIHS_CR_LOCKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_LOCKCLR_Msk instead */ 147 #define TWIHS_CR_FIFOEN_Pos 28 /**< (TWIHS_CR) FIFO Enable Position */ 148 #define TWIHS_CR_FIFOEN_Msk (_U_(0x1) << TWIHS_CR_FIFOEN_Pos) /**< (TWIHS_CR) FIFO Enable Mask */ 149 #define TWIHS_CR_FIFOEN TWIHS_CR_FIFOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFOEN_Msk instead */ 150 #define TWIHS_CR_FIFODIS_Pos 29 /**< (TWIHS_CR) FIFO Disable Position */ 151 #define TWIHS_CR_FIFODIS_Msk (_U_(0x1) << TWIHS_CR_FIFODIS_Pos) /**< (TWIHS_CR) FIFO Disable Mask */ 152 #define TWIHS_CR_FIFODIS TWIHS_CR_FIFODIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFODIS_Msk instead */ 153 #define TWIHS_CR_MASK _U_(0x3503FFFF) /**< \deprecated (TWIHS_CR) Register MASK (Use TWIHS_CR_Msk instead) */ 154 #define TWIHS_CR_Msk _U_(0x3503FFFF) /**< (TWIHS_CR) Register Mask */ 155 156 157 /* -------- TWIHS_MMR : (TWIHS Offset: 0x04) (R/W 32) Master Mode Register -------- */ 158 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 159 #if COMPONENT_TYPEDEF_STYLE == 'N' 160 typedef union { 161 struct { 162 uint32_t :8; /**< bit: 0..7 Reserved */ 163 uint32_t IADRSZ:2; /**< bit: 8..9 Internal Device Address Size */ 164 uint32_t :2; /**< bit: 10..11 Reserved */ 165 uint32_t MREAD:1; /**< bit: 12 Master Read Direction */ 166 uint32_t :3; /**< bit: 13..15 Reserved */ 167 uint32_t DADR:7; /**< bit: 16..22 Device Address */ 168 uint32_t :9; /**< bit: 23..31 Reserved */ 169 } bit; /**< Structure used for bit access */ 170 uint32_t reg; /**< Type used for register access */ 171 } TWIHS_MMR_Type; 172 #endif 173 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 174 175 #define TWIHS_MMR_OFFSET (0x04) /**< (TWIHS_MMR) Master Mode Register Offset */ 176 177 #define TWIHS_MMR_IADRSZ_Pos 8 /**< (TWIHS_MMR) Internal Device Address Size Position */ 178 #define TWIHS_MMR_IADRSZ_Msk (_U_(0x3) << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Internal Device Address Size Mask */ 179 #define TWIHS_MMR_IADRSZ(value) (TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)) 180 #define TWIHS_MMR_IADRSZ_NONE_Val _U_(0x0) /**< (TWIHS_MMR) No internal device address */ 181 #define TWIHS_MMR_IADRSZ_1_BYTE_Val _U_(0x1) /**< (TWIHS_MMR) One-byte internal device address */ 182 #define TWIHS_MMR_IADRSZ_2_BYTE_Val _U_(0x2) /**< (TWIHS_MMR) Two-byte internal device address */ 183 #define TWIHS_MMR_IADRSZ_3_BYTE_Val _U_(0x3) /**< (TWIHS_MMR) Three-byte internal device address */ 184 #define TWIHS_MMR_IADRSZ_NONE (TWIHS_MMR_IADRSZ_NONE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) No internal device address Position */ 185 #define TWIHS_MMR_IADRSZ_1_BYTE (TWIHS_MMR_IADRSZ_1_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) One-byte internal device address Position */ 186 #define TWIHS_MMR_IADRSZ_2_BYTE (TWIHS_MMR_IADRSZ_2_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Two-byte internal device address Position */ 187 #define TWIHS_MMR_IADRSZ_3_BYTE (TWIHS_MMR_IADRSZ_3_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Three-byte internal device address Position */ 188 #define TWIHS_MMR_MREAD_Pos 12 /**< (TWIHS_MMR) Master Read Direction Position */ 189 #define TWIHS_MMR_MREAD_Msk (_U_(0x1) << TWIHS_MMR_MREAD_Pos) /**< (TWIHS_MMR) Master Read Direction Mask */ 190 #define TWIHS_MMR_MREAD TWIHS_MMR_MREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_MMR_MREAD_Msk instead */ 191 #define TWIHS_MMR_DADR_Pos 16 /**< (TWIHS_MMR) Device Address Position */ 192 #define TWIHS_MMR_DADR_Msk (_U_(0x7F) << TWIHS_MMR_DADR_Pos) /**< (TWIHS_MMR) Device Address Mask */ 193 #define TWIHS_MMR_DADR(value) (TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)) 194 #define TWIHS_MMR_MASK _U_(0x7F1300) /**< \deprecated (TWIHS_MMR) Register MASK (Use TWIHS_MMR_Msk instead) */ 195 #define TWIHS_MMR_Msk _U_(0x7F1300) /**< (TWIHS_MMR) Register Mask */ 196 197 198 /* -------- TWIHS_SMR : (TWIHS Offset: 0x08) (R/W 32) Slave Mode Register -------- */ 199 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 200 #if COMPONENT_TYPEDEF_STYLE == 'N' 201 typedef union { 202 struct { 203 uint32_t NACKEN:1; /**< bit: 0 Slave Receiver Data Phase NACK enable */ 204 uint32_t :1; /**< bit: 1 Reserved */ 205 uint32_t SMDA:1; /**< bit: 2 SMBus Default Address */ 206 uint32_t SMHH:1; /**< bit: 3 SMBus Host Header */ 207 uint32_t :2; /**< bit: 4..5 Reserved */ 208 uint32_t SCLWSDIS:1; /**< bit: 6 Clock Wait State Disable */ 209 uint32_t :1; /**< bit: 7 Reserved */ 210 uint32_t MASK:7; /**< bit: 8..14 Slave Address Mask */ 211 uint32_t :1; /**< bit: 15 Reserved */ 212 uint32_t SADR:7; /**< bit: 16..22 Slave Address */ 213 uint32_t :5; /**< bit: 23..27 Reserved */ 214 uint32_t SADR1EN:1; /**< bit: 28 Slave Address 1 Enable */ 215 uint32_t SADR2EN:1; /**< bit: 29 Slave Address 2 Enable */ 216 uint32_t SADR3EN:1; /**< bit: 30 Slave Address 3 Enable */ 217 uint32_t DATAMEN:1; /**< bit: 31 Data Matching Enable */ 218 } bit; /**< Structure used for bit access */ 219 uint32_t reg; /**< Type used for register access */ 220 } TWIHS_SMR_Type; 221 #endif 222 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 223 224 #define TWIHS_SMR_OFFSET (0x08) /**< (TWIHS_SMR) Slave Mode Register Offset */ 225 226 #define TWIHS_SMR_NACKEN_Pos 0 /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Position */ 227 #define TWIHS_SMR_NACKEN_Msk (_U_(0x1) << TWIHS_SMR_NACKEN_Pos) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Mask */ 228 #define TWIHS_SMR_NACKEN TWIHS_SMR_NACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_NACKEN_Msk instead */ 229 #define TWIHS_SMR_SMDA_Pos 2 /**< (TWIHS_SMR) SMBus Default Address Position */ 230 #define TWIHS_SMR_SMDA_Msk (_U_(0x1) << TWIHS_SMR_SMDA_Pos) /**< (TWIHS_SMR) SMBus Default Address Mask */ 231 #define TWIHS_SMR_SMDA TWIHS_SMR_SMDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMDA_Msk instead */ 232 #define TWIHS_SMR_SMHH_Pos 3 /**< (TWIHS_SMR) SMBus Host Header Position */ 233 #define TWIHS_SMR_SMHH_Msk (_U_(0x1) << TWIHS_SMR_SMHH_Pos) /**< (TWIHS_SMR) SMBus Host Header Mask */ 234 #define TWIHS_SMR_SMHH TWIHS_SMR_SMHH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMHH_Msk instead */ 235 #define TWIHS_SMR_SCLWSDIS_Pos 6 /**< (TWIHS_SMR) Clock Wait State Disable Position */ 236 #define TWIHS_SMR_SCLWSDIS_Msk (_U_(0x1) << TWIHS_SMR_SCLWSDIS_Pos) /**< (TWIHS_SMR) Clock Wait State Disable Mask */ 237 #define TWIHS_SMR_SCLWSDIS TWIHS_SMR_SCLWSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SCLWSDIS_Msk instead */ 238 #define TWIHS_SMR_MASK_Pos 8 /**< (TWIHS_SMR) Slave Address Mask Position */ 239 #define TWIHS_SMR_MASK_Msk (_U_(0x7F) << TWIHS_SMR_MASK_Pos) /**< (TWIHS_SMR) Slave Address Mask Mask */ 240 #define TWIHS_SMR_MASK(value) (TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)) 241 #define TWIHS_SMR_SADR_Pos 16 /**< (TWIHS_SMR) Slave Address Position */ 242 #define TWIHS_SMR_SADR_Msk (_U_(0x7F) << TWIHS_SMR_SADR_Pos) /**< (TWIHS_SMR) Slave Address Mask */ 243 #define TWIHS_SMR_SADR(value) (TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)) 244 #define TWIHS_SMR_SADR1EN_Pos 28 /**< (TWIHS_SMR) Slave Address 1 Enable Position */ 245 #define TWIHS_SMR_SADR1EN_Msk (_U_(0x1) << TWIHS_SMR_SADR1EN_Pos) /**< (TWIHS_SMR) Slave Address 1 Enable Mask */ 246 #define TWIHS_SMR_SADR1EN TWIHS_SMR_SADR1EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR1EN_Msk instead */ 247 #define TWIHS_SMR_SADR2EN_Pos 29 /**< (TWIHS_SMR) Slave Address 2 Enable Position */ 248 #define TWIHS_SMR_SADR2EN_Msk (_U_(0x1) << TWIHS_SMR_SADR2EN_Pos) /**< (TWIHS_SMR) Slave Address 2 Enable Mask */ 249 #define TWIHS_SMR_SADR2EN TWIHS_SMR_SADR2EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR2EN_Msk instead */ 250 #define TWIHS_SMR_SADR3EN_Pos 30 /**< (TWIHS_SMR) Slave Address 3 Enable Position */ 251 #define TWIHS_SMR_SADR3EN_Msk (_U_(0x1) << TWIHS_SMR_SADR3EN_Pos) /**< (TWIHS_SMR) Slave Address 3 Enable Mask */ 252 #define TWIHS_SMR_SADR3EN TWIHS_SMR_SADR3EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR3EN_Msk instead */ 253 #define TWIHS_SMR_DATAMEN_Pos 31 /**< (TWIHS_SMR) Data Matching Enable Position */ 254 #define TWIHS_SMR_DATAMEN_Msk (_U_(0x1) << TWIHS_SMR_DATAMEN_Pos) /**< (TWIHS_SMR) Data Matching Enable Mask */ 255 #define TWIHS_SMR_DATAMEN TWIHS_SMR_DATAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_DATAMEN_Msk instead */ 256 #define TWIHS_SMR_Msk _U_(0xF07F7F4D) /**< (TWIHS_SMR) Register Mask */ 257 258 259 /* -------- TWIHS_IADR : (TWIHS Offset: 0x0c) (R/W 32) Internal Address Register -------- */ 260 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 261 #if COMPONENT_TYPEDEF_STYLE == 'N' 262 typedef union { 263 struct { 264 uint32_t IADR:24; /**< bit: 0..23 Internal Address */ 265 uint32_t :8; /**< bit: 24..31 Reserved */ 266 } bit; /**< Structure used for bit access */ 267 uint32_t reg; /**< Type used for register access */ 268 } TWIHS_IADR_Type; 269 #endif 270 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define TWIHS_IADR_OFFSET (0x0C) /**< (TWIHS_IADR) Internal Address Register Offset */ 273 274 #define TWIHS_IADR_IADR_Pos 0 /**< (TWIHS_IADR) Internal Address Position */ 275 #define TWIHS_IADR_IADR_Msk (_U_(0xFFFFFF) << TWIHS_IADR_IADR_Pos) /**< (TWIHS_IADR) Internal Address Mask */ 276 #define TWIHS_IADR_IADR(value) (TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)) 277 #define TWIHS_IADR_MASK _U_(0xFFFFFF) /**< \deprecated (TWIHS_IADR) Register MASK (Use TWIHS_IADR_Msk instead) */ 278 #define TWIHS_IADR_Msk _U_(0xFFFFFF) /**< (TWIHS_IADR) Register Mask */ 279 280 281 /* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) (R/W 32) Clock Waveform Generator Register -------- */ 282 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 283 #if COMPONENT_TYPEDEF_STYLE == 'N' 284 typedef union { 285 struct { 286 uint32_t CLDIV:8; /**< bit: 0..7 Clock Low Divider */ 287 uint32_t CHDIV:8; /**< bit: 8..15 Clock High Divider */ 288 uint32_t CKDIV:3; /**< bit: 16..18 Clock Divider */ 289 uint32_t :5; /**< bit: 19..23 Reserved */ 290 uint32_t HOLD:6; /**< bit: 24..29 TWD Hold Time Versus TWCK Falling */ 291 uint32_t :2; /**< bit: 30..31 Reserved */ 292 } bit; /**< Structure used for bit access */ 293 uint32_t reg; /**< Type used for register access */ 294 } TWIHS_CWGR_Type; 295 #endif 296 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 297 298 #define TWIHS_CWGR_OFFSET (0x10) /**< (TWIHS_CWGR) Clock Waveform Generator Register Offset */ 299 300 #define TWIHS_CWGR_CLDIV_Pos 0 /**< (TWIHS_CWGR) Clock Low Divider Position */ 301 #define TWIHS_CWGR_CLDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CLDIV_Pos) /**< (TWIHS_CWGR) Clock Low Divider Mask */ 302 #define TWIHS_CWGR_CLDIV(value) (TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)) 303 #define TWIHS_CWGR_CHDIV_Pos 8 /**< (TWIHS_CWGR) Clock High Divider Position */ 304 #define TWIHS_CWGR_CHDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CHDIV_Pos) /**< (TWIHS_CWGR) Clock High Divider Mask */ 305 #define TWIHS_CWGR_CHDIV(value) (TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)) 306 #define TWIHS_CWGR_CKDIV_Pos 16 /**< (TWIHS_CWGR) Clock Divider Position */ 307 #define TWIHS_CWGR_CKDIV_Msk (_U_(0x7) << TWIHS_CWGR_CKDIV_Pos) /**< (TWIHS_CWGR) Clock Divider Mask */ 308 #define TWIHS_CWGR_CKDIV(value) (TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)) 309 #define TWIHS_CWGR_HOLD_Pos 24 /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Position */ 310 #define TWIHS_CWGR_HOLD_Msk (_U_(0x3F) << TWIHS_CWGR_HOLD_Pos) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Mask */ 311 #define TWIHS_CWGR_HOLD(value) (TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)) 312 #define TWIHS_CWGR_MASK _U_(0x3F07FFFF) /**< \deprecated (TWIHS_CWGR) Register MASK (Use TWIHS_CWGR_Msk instead) */ 313 #define TWIHS_CWGR_Msk _U_(0x3F07FFFF) /**< (TWIHS_CWGR) Register Mask */ 314 315 316 /* -------- TWIHS_SR : (TWIHS Offset: 0x20) (R/ 32) Status Register -------- */ 317 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 318 #if COMPONENT_TYPEDEF_STYLE == 'N' 319 typedef union { 320 struct { 321 uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed (cleared by writing TWIHS_THR) */ 322 uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ 323 uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ 324 uint32_t SVREAD:1; /**< bit: 3 Slave Read */ 325 uint32_t SVACC:1; /**< bit: 4 Slave Access */ 326 uint32_t GACC:1; /**< bit: 5 General Call Access (cleared on read) */ 327 uint32_t OVRE:1; /**< bit: 6 Overrun Error (cleared on read) */ 328 uint32_t UNRE:1; /**< bit: 7 Underrun Error (cleared on read) */ 329 uint32_t NACK:1; /**< bit: 8 Not Acknowledged (cleared on read) */ 330 uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost (cleared on read) */ 331 uint32_t SCLWS:1; /**< bit: 10 Clock Wait State */ 332 uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access (cleared on read) */ 333 uint32_t :4; /**< bit: 12..15 Reserved */ 334 uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge (cleared on read) */ 335 uint32_t :1; /**< bit: 17 Reserved */ 336 uint32_t TOUT:1; /**< bit: 18 Timeout Error (cleared on read) */ 337 uint32_t PECERR:1; /**< bit: 19 PEC Error (cleared on read) */ 338 uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match (cleared on read) */ 339 uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match (cleared on read) */ 340 uint32_t :2; /**< bit: 22..23 Reserved */ 341 uint32_t SCL:1; /**< bit: 24 SCL Line Value */ 342 uint32_t SDA:1; /**< bit: 25 SDA Line Value */ 343 uint32_t :6; /**< bit: 26..31 Reserved */ 344 } bit; /**< Structure used for bit access */ 345 uint32_t reg; /**< Type used for register access */ 346 } TWIHS_SR_Type; 347 #endif 348 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define TWIHS_SR_OFFSET (0x20) /**< (TWIHS_SR) Status Register Offset */ 351 352 #define TWIHS_SR_TXCOMP_Pos 0 /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Position */ 353 #define TWIHS_SR_TXCOMP_Msk (_U_(0x1) << TWIHS_SR_TXCOMP_Pos) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Mask */ 354 #define TWIHS_SR_TXCOMP TWIHS_SR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXCOMP_Msk instead */ 355 #define TWIHS_SR_RXRDY_Pos 1 /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Position */ 356 #define TWIHS_SR_RXRDY_Msk (_U_(0x1) << TWIHS_SR_RXRDY_Pos) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Mask */ 357 #define TWIHS_SR_RXRDY TWIHS_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_RXRDY_Msk instead */ 358 #define TWIHS_SR_TXRDY_Pos 2 /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Position */ 359 #define TWIHS_SR_TXRDY_Msk (_U_(0x1) << TWIHS_SR_TXRDY_Pos) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Mask */ 360 #define TWIHS_SR_TXRDY TWIHS_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXRDY_Msk instead */ 361 #define TWIHS_SR_SVREAD_Pos 3 /**< (TWIHS_SR) Slave Read Position */ 362 #define TWIHS_SR_SVREAD_Msk (_U_(0x1) << TWIHS_SR_SVREAD_Pos) /**< (TWIHS_SR) Slave Read Mask */ 363 #define TWIHS_SR_SVREAD TWIHS_SR_SVREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVREAD_Msk instead */ 364 #define TWIHS_SR_SVACC_Pos 4 /**< (TWIHS_SR) Slave Access Position */ 365 #define TWIHS_SR_SVACC_Msk (_U_(0x1) << TWIHS_SR_SVACC_Pos) /**< (TWIHS_SR) Slave Access Mask */ 366 #define TWIHS_SR_SVACC TWIHS_SR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVACC_Msk instead */ 367 #define TWIHS_SR_GACC_Pos 5 /**< (TWIHS_SR) General Call Access (cleared on read) Position */ 368 #define TWIHS_SR_GACC_Msk (_U_(0x1) << TWIHS_SR_GACC_Pos) /**< (TWIHS_SR) General Call Access (cleared on read) Mask */ 369 #define TWIHS_SR_GACC TWIHS_SR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_GACC_Msk instead */ 370 #define TWIHS_SR_OVRE_Pos 6 /**< (TWIHS_SR) Overrun Error (cleared on read) Position */ 371 #define TWIHS_SR_OVRE_Msk (_U_(0x1) << TWIHS_SR_OVRE_Pos) /**< (TWIHS_SR) Overrun Error (cleared on read) Mask */ 372 #define TWIHS_SR_OVRE TWIHS_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_OVRE_Msk instead */ 373 #define TWIHS_SR_UNRE_Pos 7 /**< (TWIHS_SR) Underrun Error (cleared on read) Position */ 374 #define TWIHS_SR_UNRE_Msk (_U_(0x1) << TWIHS_SR_UNRE_Pos) /**< (TWIHS_SR) Underrun Error (cleared on read) Mask */ 375 #define TWIHS_SR_UNRE TWIHS_SR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_UNRE_Msk instead */ 376 #define TWIHS_SR_NACK_Pos 8 /**< (TWIHS_SR) Not Acknowledged (cleared on read) Position */ 377 #define TWIHS_SR_NACK_Msk (_U_(0x1) << TWIHS_SR_NACK_Pos) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Mask */ 378 #define TWIHS_SR_NACK TWIHS_SR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_NACK_Msk instead */ 379 #define TWIHS_SR_ARBLST_Pos 9 /**< (TWIHS_SR) Arbitration Lost (cleared on read) Position */ 380 #define TWIHS_SR_ARBLST_Msk (_U_(0x1) << TWIHS_SR_ARBLST_Pos) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Mask */ 381 #define TWIHS_SR_ARBLST TWIHS_SR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_ARBLST_Msk instead */ 382 #define TWIHS_SR_SCLWS_Pos 10 /**< (TWIHS_SR) Clock Wait State Position */ 383 #define TWIHS_SR_SCLWS_Msk (_U_(0x1) << TWIHS_SR_SCLWS_Pos) /**< (TWIHS_SR) Clock Wait State Mask */ 384 #define TWIHS_SR_SCLWS TWIHS_SR_SCLWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCLWS_Msk instead */ 385 #define TWIHS_SR_EOSACC_Pos 11 /**< (TWIHS_SR) End Of Slave Access (cleared on read) Position */ 386 #define TWIHS_SR_EOSACC_Msk (_U_(0x1) << TWIHS_SR_EOSACC_Pos) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Mask */ 387 #define TWIHS_SR_EOSACC TWIHS_SR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_EOSACC_Msk instead */ 388 #define TWIHS_SR_MCACK_Pos 16 /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Position */ 389 #define TWIHS_SR_MCACK_Msk (_U_(0x1) << TWIHS_SR_MCACK_Pos) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Mask */ 390 #define TWIHS_SR_MCACK TWIHS_SR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_MCACK_Msk instead */ 391 #define TWIHS_SR_TOUT_Pos 18 /**< (TWIHS_SR) Timeout Error (cleared on read) Position */ 392 #define TWIHS_SR_TOUT_Msk (_U_(0x1) << TWIHS_SR_TOUT_Pos) /**< (TWIHS_SR) Timeout Error (cleared on read) Mask */ 393 #define TWIHS_SR_TOUT TWIHS_SR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TOUT_Msk instead */ 394 #define TWIHS_SR_PECERR_Pos 19 /**< (TWIHS_SR) PEC Error (cleared on read) Position */ 395 #define TWIHS_SR_PECERR_Msk (_U_(0x1) << TWIHS_SR_PECERR_Pos) /**< (TWIHS_SR) PEC Error (cleared on read) Mask */ 396 #define TWIHS_SR_PECERR TWIHS_SR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_PECERR_Msk instead */ 397 #define TWIHS_SR_SMBDAM_Pos 20 /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Position */ 398 #define TWIHS_SR_SMBDAM_Msk (_U_(0x1) << TWIHS_SR_SMBDAM_Pos) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Mask */ 399 #define TWIHS_SR_SMBDAM TWIHS_SR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBDAM_Msk instead */ 400 #define TWIHS_SR_SMBHHM_Pos 21 /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Position */ 401 #define TWIHS_SR_SMBHHM_Msk (_U_(0x1) << TWIHS_SR_SMBHHM_Pos) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Mask */ 402 #define TWIHS_SR_SMBHHM TWIHS_SR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBHHM_Msk instead */ 403 #define TWIHS_SR_SCL_Pos 24 /**< (TWIHS_SR) SCL Line Value Position */ 404 #define TWIHS_SR_SCL_Msk (_U_(0x1) << TWIHS_SR_SCL_Pos) /**< (TWIHS_SR) SCL Line Value Mask */ 405 #define TWIHS_SR_SCL TWIHS_SR_SCL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCL_Msk instead */ 406 #define TWIHS_SR_SDA_Pos 25 /**< (TWIHS_SR) SDA Line Value Position */ 407 #define TWIHS_SR_SDA_Msk (_U_(0x1) << TWIHS_SR_SDA_Pos) /**< (TWIHS_SR) SDA Line Value Mask */ 408 #define TWIHS_SR_SDA TWIHS_SR_SDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SDA_Msk instead */ 409 #define TWIHS_SR_MASK _U_(0x33D0FFF) /**< \deprecated (TWIHS_SR) Register MASK (Use TWIHS_SR_Msk instead) */ 410 #define TWIHS_SR_Msk _U_(0x33D0FFF) /**< (TWIHS_SR) Register Mask */ 411 412 413 /* -------- TWIHS_IER : (TWIHS Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ 414 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 415 #if COMPONENT_TYPEDEF_STYLE == 'N' 416 typedef union { 417 struct { 418 uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Enable */ 419 uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Enable */ 420 uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Enable */ 421 uint32_t :1; /**< bit: 3 Reserved */ 422 uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Enable */ 423 uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Enable */ 424 uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Enable */ 425 uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Enable */ 426 uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Enable */ 427 uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Enable */ 428 uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Enable */ 429 uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Enable */ 430 uint32_t :4; /**< bit: 12..15 Reserved */ 431 uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Enable */ 432 uint32_t :1; /**< bit: 17 Reserved */ 433 uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Enable */ 434 uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Enable */ 435 uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Enable */ 436 uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Enable */ 437 uint32_t :10; /**< bit: 22..31 Reserved */ 438 } bit; /**< Structure used for bit access */ 439 uint32_t reg; /**< Type used for register access */ 440 } TWIHS_IER_Type; 441 #endif 442 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 443 444 #define TWIHS_IER_OFFSET (0x24) /**< (TWIHS_IER) Interrupt Enable Register Offset */ 445 446 #define TWIHS_IER_TXCOMP_Pos 0 /**< (TWIHS_IER) Transmission Completed Interrupt Enable Position */ 447 #define TWIHS_IER_TXCOMP_Msk (_U_(0x1) << TWIHS_IER_TXCOMP_Pos) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Mask */ 448 #define TWIHS_IER_TXCOMP TWIHS_IER_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXCOMP_Msk instead */ 449 #define TWIHS_IER_RXRDY_Pos 1 /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Position */ 450 #define TWIHS_IER_RXRDY_Msk (_U_(0x1) << TWIHS_IER_RXRDY_Pos) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Mask */ 451 #define TWIHS_IER_RXRDY TWIHS_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_RXRDY_Msk instead */ 452 #define TWIHS_IER_TXRDY_Pos 2 /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Position */ 453 #define TWIHS_IER_TXRDY_Msk (_U_(0x1) << TWIHS_IER_TXRDY_Pos) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Mask */ 454 #define TWIHS_IER_TXRDY TWIHS_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXRDY_Msk instead */ 455 #define TWIHS_IER_SVACC_Pos 4 /**< (TWIHS_IER) Slave Access Interrupt Enable Position */ 456 #define TWIHS_IER_SVACC_Msk (_U_(0x1) << TWIHS_IER_SVACC_Pos) /**< (TWIHS_IER) Slave Access Interrupt Enable Mask */ 457 #define TWIHS_IER_SVACC TWIHS_IER_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SVACC_Msk instead */ 458 #define TWIHS_IER_GACC_Pos 5 /**< (TWIHS_IER) General Call Access Interrupt Enable Position */ 459 #define TWIHS_IER_GACC_Msk (_U_(0x1) << TWIHS_IER_GACC_Pos) /**< (TWIHS_IER) General Call Access Interrupt Enable Mask */ 460 #define TWIHS_IER_GACC TWIHS_IER_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_GACC_Msk instead */ 461 #define TWIHS_IER_OVRE_Pos 6 /**< (TWIHS_IER) Overrun Error Interrupt Enable Position */ 462 #define TWIHS_IER_OVRE_Msk (_U_(0x1) << TWIHS_IER_OVRE_Pos) /**< (TWIHS_IER) Overrun Error Interrupt Enable Mask */ 463 #define TWIHS_IER_OVRE TWIHS_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_OVRE_Msk instead */ 464 #define TWIHS_IER_UNRE_Pos 7 /**< (TWIHS_IER) Underrun Error Interrupt Enable Position */ 465 #define TWIHS_IER_UNRE_Msk (_U_(0x1) << TWIHS_IER_UNRE_Pos) /**< (TWIHS_IER) Underrun Error Interrupt Enable Mask */ 466 #define TWIHS_IER_UNRE TWIHS_IER_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_UNRE_Msk instead */ 467 #define TWIHS_IER_NACK_Pos 8 /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Position */ 468 #define TWIHS_IER_NACK_Msk (_U_(0x1) << TWIHS_IER_NACK_Pos) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Mask */ 469 #define TWIHS_IER_NACK TWIHS_IER_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_NACK_Msk instead */ 470 #define TWIHS_IER_ARBLST_Pos 9 /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Position */ 471 #define TWIHS_IER_ARBLST_Msk (_U_(0x1) << TWIHS_IER_ARBLST_Pos) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Mask */ 472 #define TWIHS_IER_ARBLST TWIHS_IER_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_ARBLST_Msk instead */ 473 #define TWIHS_IER_SCL_WS_Pos 10 /**< (TWIHS_IER) Clock Wait State Interrupt Enable Position */ 474 #define TWIHS_IER_SCL_WS_Msk (_U_(0x1) << TWIHS_IER_SCL_WS_Pos) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Mask */ 475 #define TWIHS_IER_SCL_WS TWIHS_IER_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SCL_WS_Msk instead */ 476 #define TWIHS_IER_EOSACC_Pos 11 /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Position */ 477 #define TWIHS_IER_EOSACC_Msk (_U_(0x1) << TWIHS_IER_EOSACC_Pos) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Mask */ 478 #define TWIHS_IER_EOSACC TWIHS_IER_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_EOSACC_Msk instead */ 479 #define TWIHS_IER_MCACK_Pos 16 /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Position */ 480 #define TWIHS_IER_MCACK_Msk (_U_(0x1) << TWIHS_IER_MCACK_Pos) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Mask */ 481 #define TWIHS_IER_MCACK TWIHS_IER_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_MCACK_Msk instead */ 482 #define TWIHS_IER_TOUT_Pos 18 /**< (TWIHS_IER) Timeout Error Interrupt Enable Position */ 483 #define TWIHS_IER_TOUT_Msk (_U_(0x1) << TWIHS_IER_TOUT_Pos) /**< (TWIHS_IER) Timeout Error Interrupt Enable Mask */ 484 #define TWIHS_IER_TOUT TWIHS_IER_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TOUT_Msk instead */ 485 #define TWIHS_IER_PECERR_Pos 19 /**< (TWIHS_IER) PEC Error Interrupt Enable Position */ 486 #define TWIHS_IER_PECERR_Msk (_U_(0x1) << TWIHS_IER_PECERR_Pos) /**< (TWIHS_IER) PEC Error Interrupt Enable Mask */ 487 #define TWIHS_IER_PECERR TWIHS_IER_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_PECERR_Msk instead */ 488 #define TWIHS_IER_SMBDAM_Pos 20 /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Position */ 489 #define TWIHS_IER_SMBDAM_Msk (_U_(0x1) << TWIHS_IER_SMBDAM_Pos) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Mask */ 490 #define TWIHS_IER_SMBDAM TWIHS_IER_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBDAM_Msk instead */ 491 #define TWIHS_IER_SMBHHM_Pos 21 /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Position */ 492 #define TWIHS_IER_SMBHHM_Msk (_U_(0x1) << TWIHS_IER_SMBHHM_Pos) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Mask */ 493 #define TWIHS_IER_SMBHHM TWIHS_IER_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBHHM_Msk instead */ 494 #define TWIHS_IER_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IER) Register MASK (Use TWIHS_IER_Msk instead) */ 495 #define TWIHS_IER_Msk _U_(0x3D0FF7) /**< (TWIHS_IER) Register Mask */ 496 497 498 /* -------- TWIHS_IDR : (TWIHS Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ 499 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 500 #if COMPONENT_TYPEDEF_STYLE == 'N' 501 typedef union { 502 struct { 503 uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Disable */ 504 uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Disable */ 505 uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Disable */ 506 uint32_t :1; /**< bit: 3 Reserved */ 507 uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Disable */ 508 uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Disable */ 509 uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Disable */ 510 uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Disable */ 511 uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Disable */ 512 uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Disable */ 513 uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Disable */ 514 uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Disable */ 515 uint32_t :4; /**< bit: 12..15 Reserved */ 516 uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Disable */ 517 uint32_t :1; /**< bit: 17 Reserved */ 518 uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Disable */ 519 uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Disable */ 520 uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Disable */ 521 uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Disable */ 522 uint32_t :10; /**< bit: 22..31 Reserved */ 523 } bit; /**< Structure used for bit access */ 524 uint32_t reg; /**< Type used for register access */ 525 } TWIHS_IDR_Type; 526 #endif 527 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 528 529 #define TWIHS_IDR_OFFSET (0x28) /**< (TWIHS_IDR) Interrupt Disable Register Offset */ 530 531 #define TWIHS_IDR_TXCOMP_Pos 0 /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Position */ 532 #define TWIHS_IDR_TXCOMP_Msk (_U_(0x1) << TWIHS_IDR_TXCOMP_Pos) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Mask */ 533 #define TWIHS_IDR_TXCOMP TWIHS_IDR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXCOMP_Msk instead */ 534 #define TWIHS_IDR_RXRDY_Pos 1 /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Position */ 535 #define TWIHS_IDR_RXRDY_Msk (_U_(0x1) << TWIHS_IDR_RXRDY_Pos) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Mask */ 536 #define TWIHS_IDR_RXRDY TWIHS_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_RXRDY_Msk instead */ 537 #define TWIHS_IDR_TXRDY_Pos 2 /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Position */ 538 #define TWIHS_IDR_TXRDY_Msk (_U_(0x1) << TWIHS_IDR_TXRDY_Pos) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Mask */ 539 #define TWIHS_IDR_TXRDY TWIHS_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXRDY_Msk instead */ 540 #define TWIHS_IDR_SVACC_Pos 4 /**< (TWIHS_IDR) Slave Access Interrupt Disable Position */ 541 #define TWIHS_IDR_SVACC_Msk (_U_(0x1) << TWIHS_IDR_SVACC_Pos) /**< (TWIHS_IDR) Slave Access Interrupt Disable Mask */ 542 #define TWIHS_IDR_SVACC TWIHS_IDR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SVACC_Msk instead */ 543 #define TWIHS_IDR_GACC_Pos 5 /**< (TWIHS_IDR) General Call Access Interrupt Disable Position */ 544 #define TWIHS_IDR_GACC_Msk (_U_(0x1) << TWIHS_IDR_GACC_Pos) /**< (TWIHS_IDR) General Call Access Interrupt Disable Mask */ 545 #define TWIHS_IDR_GACC TWIHS_IDR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_GACC_Msk instead */ 546 #define TWIHS_IDR_OVRE_Pos 6 /**< (TWIHS_IDR) Overrun Error Interrupt Disable Position */ 547 #define TWIHS_IDR_OVRE_Msk (_U_(0x1) << TWIHS_IDR_OVRE_Pos) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Mask */ 548 #define TWIHS_IDR_OVRE TWIHS_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_OVRE_Msk instead */ 549 #define TWIHS_IDR_UNRE_Pos 7 /**< (TWIHS_IDR) Underrun Error Interrupt Disable Position */ 550 #define TWIHS_IDR_UNRE_Msk (_U_(0x1) << TWIHS_IDR_UNRE_Pos) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Mask */ 551 #define TWIHS_IDR_UNRE TWIHS_IDR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_UNRE_Msk instead */ 552 #define TWIHS_IDR_NACK_Pos 8 /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Position */ 553 #define TWIHS_IDR_NACK_Msk (_U_(0x1) << TWIHS_IDR_NACK_Pos) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Mask */ 554 #define TWIHS_IDR_NACK TWIHS_IDR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_NACK_Msk instead */ 555 #define TWIHS_IDR_ARBLST_Pos 9 /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Position */ 556 #define TWIHS_IDR_ARBLST_Msk (_U_(0x1) << TWIHS_IDR_ARBLST_Pos) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Mask */ 557 #define TWIHS_IDR_ARBLST TWIHS_IDR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_ARBLST_Msk instead */ 558 #define TWIHS_IDR_SCL_WS_Pos 10 /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Position */ 559 #define TWIHS_IDR_SCL_WS_Msk (_U_(0x1) << TWIHS_IDR_SCL_WS_Pos) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Mask */ 560 #define TWIHS_IDR_SCL_WS TWIHS_IDR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SCL_WS_Msk instead */ 561 #define TWIHS_IDR_EOSACC_Pos 11 /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Position */ 562 #define TWIHS_IDR_EOSACC_Msk (_U_(0x1) << TWIHS_IDR_EOSACC_Pos) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Mask */ 563 #define TWIHS_IDR_EOSACC TWIHS_IDR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_EOSACC_Msk instead */ 564 #define TWIHS_IDR_MCACK_Pos 16 /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Position */ 565 #define TWIHS_IDR_MCACK_Msk (_U_(0x1) << TWIHS_IDR_MCACK_Pos) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Mask */ 566 #define TWIHS_IDR_MCACK TWIHS_IDR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_MCACK_Msk instead */ 567 #define TWIHS_IDR_TOUT_Pos 18 /**< (TWIHS_IDR) Timeout Error Interrupt Disable Position */ 568 #define TWIHS_IDR_TOUT_Msk (_U_(0x1) << TWIHS_IDR_TOUT_Pos) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Mask */ 569 #define TWIHS_IDR_TOUT TWIHS_IDR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TOUT_Msk instead */ 570 #define TWIHS_IDR_PECERR_Pos 19 /**< (TWIHS_IDR) PEC Error Interrupt Disable Position */ 571 #define TWIHS_IDR_PECERR_Msk (_U_(0x1) << TWIHS_IDR_PECERR_Pos) /**< (TWIHS_IDR) PEC Error Interrupt Disable Mask */ 572 #define TWIHS_IDR_PECERR TWIHS_IDR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_PECERR_Msk instead */ 573 #define TWIHS_IDR_SMBDAM_Pos 20 /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Position */ 574 #define TWIHS_IDR_SMBDAM_Msk (_U_(0x1) << TWIHS_IDR_SMBDAM_Pos) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Mask */ 575 #define TWIHS_IDR_SMBDAM TWIHS_IDR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBDAM_Msk instead */ 576 #define TWIHS_IDR_SMBHHM_Pos 21 /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Position */ 577 #define TWIHS_IDR_SMBHHM_Msk (_U_(0x1) << TWIHS_IDR_SMBHHM_Pos) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Mask */ 578 #define TWIHS_IDR_SMBHHM TWIHS_IDR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBHHM_Msk instead */ 579 #define TWIHS_IDR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IDR) Register MASK (Use TWIHS_IDR_Msk instead) */ 580 #define TWIHS_IDR_Msk _U_(0x3D0FF7) /**< (TWIHS_IDR) Register Mask */ 581 582 583 /* -------- TWIHS_IMR : (TWIHS Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ 584 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 585 #if COMPONENT_TYPEDEF_STYLE == 'N' 586 typedef union { 587 struct { 588 uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Mask */ 589 uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Mask */ 590 uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Mask */ 591 uint32_t :1; /**< bit: 3 Reserved */ 592 uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Mask */ 593 uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Mask */ 594 uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Mask */ 595 uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Mask */ 596 uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Mask */ 597 uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Mask */ 598 uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Mask */ 599 uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Mask */ 600 uint32_t :4; /**< bit: 12..15 Reserved */ 601 uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Mask */ 602 uint32_t :1; /**< bit: 17 Reserved */ 603 uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Mask */ 604 uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Mask */ 605 uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Mask */ 606 uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Mask */ 607 uint32_t :10; /**< bit: 22..31 Reserved */ 608 } bit; /**< Structure used for bit access */ 609 uint32_t reg; /**< Type used for register access */ 610 } TWIHS_IMR_Type; 611 #endif 612 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 613 614 #define TWIHS_IMR_OFFSET (0x2C) /**< (TWIHS_IMR) Interrupt Mask Register Offset */ 615 616 #define TWIHS_IMR_TXCOMP_Pos 0 /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Position */ 617 #define TWIHS_IMR_TXCOMP_Msk (_U_(0x1) << TWIHS_IMR_TXCOMP_Pos) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Mask */ 618 #define TWIHS_IMR_TXCOMP TWIHS_IMR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXCOMP_Msk instead */ 619 #define TWIHS_IMR_RXRDY_Pos 1 /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Position */ 620 #define TWIHS_IMR_RXRDY_Msk (_U_(0x1) << TWIHS_IMR_RXRDY_Pos) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Mask */ 621 #define TWIHS_IMR_RXRDY TWIHS_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_RXRDY_Msk instead */ 622 #define TWIHS_IMR_TXRDY_Pos 2 /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Position */ 623 #define TWIHS_IMR_TXRDY_Msk (_U_(0x1) << TWIHS_IMR_TXRDY_Pos) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Mask */ 624 #define TWIHS_IMR_TXRDY TWIHS_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXRDY_Msk instead */ 625 #define TWIHS_IMR_SVACC_Pos 4 /**< (TWIHS_IMR) Slave Access Interrupt Mask Position */ 626 #define TWIHS_IMR_SVACC_Msk (_U_(0x1) << TWIHS_IMR_SVACC_Pos) /**< (TWIHS_IMR) Slave Access Interrupt Mask Mask */ 627 #define TWIHS_IMR_SVACC TWIHS_IMR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SVACC_Msk instead */ 628 #define TWIHS_IMR_GACC_Pos 5 /**< (TWIHS_IMR) General Call Access Interrupt Mask Position */ 629 #define TWIHS_IMR_GACC_Msk (_U_(0x1) << TWIHS_IMR_GACC_Pos) /**< (TWIHS_IMR) General Call Access Interrupt Mask Mask */ 630 #define TWIHS_IMR_GACC TWIHS_IMR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_GACC_Msk instead */ 631 #define TWIHS_IMR_OVRE_Pos 6 /**< (TWIHS_IMR) Overrun Error Interrupt Mask Position */ 632 #define TWIHS_IMR_OVRE_Msk (_U_(0x1) << TWIHS_IMR_OVRE_Pos) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Mask */ 633 #define TWIHS_IMR_OVRE TWIHS_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_OVRE_Msk instead */ 634 #define TWIHS_IMR_UNRE_Pos 7 /**< (TWIHS_IMR) Underrun Error Interrupt Mask Position */ 635 #define TWIHS_IMR_UNRE_Msk (_U_(0x1) << TWIHS_IMR_UNRE_Pos) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Mask */ 636 #define TWIHS_IMR_UNRE TWIHS_IMR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_UNRE_Msk instead */ 637 #define TWIHS_IMR_NACK_Pos 8 /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Position */ 638 #define TWIHS_IMR_NACK_Msk (_U_(0x1) << TWIHS_IMR_NACK_Pos) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Mask */ 639 #define TWIHS_IMR_NACK TWIHS_IMR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_NACK_Msk instead */ 640 #define TWIHS_IMR_ARBLST_Pos 9 /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Position */ 641 #define TWIHS_IMR_ARBLST_Msk (_U_(0x1) << TWIHS_IMR_ARBLST_Pos) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Mask */ 642 #define TWIHS_IMR_ARBLST TWIHS_IMR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_ARBLST_Msk instead */ 643 #define TWIHS_IMR_SCL_WS_Pos 10 /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Position */ 644 #define TWIHS_IMR_SCL_WS_Msk (_U_(0x1) << TWIHS_IMR_SCL_WS_Pos) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Mask */ 645 #define TWIHS_IMR_SCL_WS TWIHS_IMR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SCL_WS_Msk instead */ 646 #define TWIHS_IMR_EOSACC_Pos 11 /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Position */ 647 #define TWIHS_IMR_EOSACC_Msk (_U_(0x1) << TWIHS_IMR_EOSACC_Pos) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Mask */ 648 #define TWIHS_IMR_EOSACC TWIHS_IMR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_EOSACC_Msk instead */ 649 #define TWIHS_IMR_MCACK_Pos 16 /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Position */ 650 #define TWIHS_IMR_MCACK_Msk (_U_(0x1) << TWIHS_IMR_MCACK_Pos) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Mask */ 651 #define TWIHS_IMR_MCACK TWIHS_IMR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_MCACK_Msk instead */ 652 #define TWIHS_IMR_TOUT_Pos 18 /**< (TWIHS_IMR) Timeout Error Interrupt Mask Position */ 653 #define TWIHS_IMR_TOUT_Msk (_U_(0x1) << TWIHS_IMR_TOUT_Pos) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Mask */ 654 #define TWIHS_IMR_TOUT TWIHS_IMR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TOUT_Msk instead */ 655 #define TWIHS_IMR_PECERR_Pos 19 /**< (TWIHS_IMR) PEC Error Interrupt Mask Position */ 656 #define TWIHS_IMR_PECERR_Msk (_U_(0x1) << TWIHS_IMR_PECERR_Pos) /**< (TWIHS_IMR) PEC Error Interrupt Mask Mask */ 657 #define TWIHS_IMR_PECERR TWIHS_IMR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_PECERR_Msk instead */ 658 #define TWIHS_IMR_SMBDAM_Pos 20 /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Position */ 659 #define TWIHS_IMR_SMBDAM_Msk (_U_(0x1) << TWIHS_IMR_SMBDAM_Pos) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Mask */ 660 #define TWIHS_IMR_SMBDAM TWIHS_IMR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBDAM_Msk instead */ 661 #define TWIHS_IMR_SMBHHM_Pos 21 /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Position */ 662 #define TWIHS_IMR_SMBHHM_Msk (_U_(0x1) << TWIHS_IMR_SMBHHM_Pos) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Mask */ 663 #define TWIHS_IMR_SMBHHM TWIHS_IMR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBHHM_Msk instead */ 664 #define TWIHS_IMR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IMR) Register MASK (Use TWIHS_IMR_Msk instead) */ 665 #define TWIHS_IMR_Msk _U_(0x3D0FF7) /**< (TWIHS_IMR) Register Mask */ 666 667 668 /* -------- TWIHS_RHR : (TWIHS Offset: 0x30) (R/ 32) Receive Holding Register -------- */ 669 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 670 #if COMPONENT_TYPEDEF_STYLE == 'N' 671 typedef union { 672 struct { 673 uint32_t RXDATA:8; /**< bit: 0..7 Master or Slave Receive Holding Data */ 674 uint32_t :24; /**< bit: 8..31 Reserved */ 675 } bit; /**< Structure used for bit access */ 676 uint32_t reg; /**< Type used for register access */ 677 } TWIHS_RHR_Type; 678 #endif 679 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 680 681 #define TWIHS_RHR_OFFSET (0x30) /**< (TWIHS_RHR) Receive Holding Register Offset */ 682 683 #define TWIHS_RHR_RXDATA_Pos 0 /**< (TWIHS_RHR) Master or Slave Receive Holding Data Position */ 684 #define TWIHS_RHR_RXDATA_Msk (_U_(0xFF) << TWIHS_RHR_RXDATA_Pos) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Mask */ 685 #define TWIHS_RHR_RXDATA(value) (TWIHS_RHR_RXDATA_Msk & ((value) << TWIHS_RHR_RXDATA_Pos)) 686 #define TWIHS_RHR_MASK _U_(0xFF) /**< \deprecated (TWIHS_RHR) Register MASK (Use TWIHS_RHR_Msk instead) */ 687 #define TWIHS_RHR_Msk _U_(0xFF) /**< (TWIHS_RHR) Register Mask */ 688 689 690 /* -------- TWIHS_THR : (TWIHS Offset: 0x34) (/W 32) Transmit Holding Register -------- */ 691 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 692 #if COMPONENT_TYPEDEF_STYLE == 'N' 693 typedef union { 694 struct { 695 uint32_t TXDATA:8; /**< bit: 0..7 Master or Slave Transmit Holding Data */ 696 uint32_t :24; /**< bit: 8..31 Reserved */ 697 } bit; /**< Structure used for bit access */ 698 uint32_t reg; /**< Type used for register access */ 699 } TWIHS_THR_Type; 700 #endif 701 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 702 703 #define TWIHS_THR_OFFSET (0x34) /**< (TWIHS_THR) Transmit Holding Register Offset */ 704 705 #define TWIHS_THR_TXDATA_Pos 0 /**< (TWIHS_THR) Master or Slave Transmit Holding Data Position */ 706 #define TWIHS_THR_TXDATA_Msk (_U_(0xFF) << TWIHS_THR_TXDATA_Pos) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Mask */ 707 #define TWIHS_THR_TXDATA(value) (TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)) 708 #define TWIHS_THR_MASK _U_(0xFF) /**< \deprecated (TWIHS_THR) Register MASK (Use TWIHS_THR_Msk instead) */ 709 #define TWIHS_THR_Msk _U_(0xFF) /**< (TWIHS_THR) Register Mask */ 710 711 712 /* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) (R/W 32) SMBus Timing Register -------- */ 713 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 714 #if COMPONENT_TYPEDEF_STYLE == 'N' 715 typedef union { 716 struct { 717 uint32_t PRESC:4; /**< bit: 0..3 SMBus Clock Prescaler */ 718 uint32_t :4; /**< bit: 4..7 Reserved */ 719 uint32_t TLOWS:8; /**< bit: 8..15 Slave Clock Stretch Maximum Cycles */ 720 uint32_t TLOWM:8; /**< bit: 16..23 Master Clock Stretch Maximum Cycles */ 721 uint32_t THMAX:8; /**< bit: 24..31 Clock High Maximum Cycles */ 722 } bit; /**< Structure used for bit access */ 723 uint32_t reg; /**< Type used for register access */ 724 } TWIHS_SMBTR_Type; 725 #endif 726 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 727 728 #define TWIHS_SMBTR_OFFSET (0x38) /**< (TWIHS_SMBTR) SMBus Timing Register Offset */ 729 730 #define TWIHS_SMBTR_PRESC_Pos 0 /**< (TWIHS_SMBTR) SMBus Clock Prescaler Position */ 731 #define TWIHS_SMBTR_PRESC_Msk (_U_(0xF) << TWIHS_SMBTR_PRESC_Pos) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Mask */ 732 #define TWIHS_SMBTR_PRESC(value) (TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)) 733 #define TWIHS_SMBTR_TLOWS_Pos 8 /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Position */ 734 #define TWIHS_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWS_Pos) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Mask */ 735 #define TWIHS_SMBTR_TLOWS(value) (TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)) 736 #define TWIHS_SMBTR_TLOWM_Pos 16 /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Position */ 737 #define TWIHS_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWM_Pos) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Mask */ 738 #define TWIHS_SMBTR_TLOWM(value) (TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)) 739 #define TWIHS_SMBTR_THMAX_Pos 24 /**< (TWIHS_SMBTR) Clock High Maximum Cycles Position */ 740 #define TWIHS_SMBTR_THMAX_Msk (_U_(0xFF) << TWIHS_SMBTR_THMAX_Pos) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Mask */ 741 #define TWIHS_SMBTR_THMAX(value) (TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)) 742 #define TWIHS_SMBTR_MASK _U_(0xFFFFFF0F) /**< \deprecated (TWIHS_SMBTR) Register MASK (Use TWIHS_SMBTR_Msk instead) */ 743 #define TWIHS_SMBTR_Msk _U_(0xFFFFFF0F) /**< (TWIHS_SMBTR) Register Mask */ 744 745 746 /* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) (R/W 32) Filter Register -------- */ 747 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 748 #if COMPONENT_TYPEDEF_STYLE == 'N' 749 typedef union { 750 struct { 751 uint32_t FILT:1; /**< bit: 0 RX Digital Filter */ 752 uint32_t PADFEN:1; /**< bit: 1 PAD Filter Enable */ 753 uint32_t PADFCFG:1; /**< bit: 2 PAD Filter Config */ 754 uint32_t :5; /**< bit: 3..7 Reserved */ 755 uint32_t THRES:3; /**< bit: 8..10 Digital Filter Threshold */ 756 uint32_t :21; /**< bit: 11..31 Reserved */ 757 } bit; /**< Structure used for bit access */ 758 uint32_t reg; /**< Type used for register access */ 759 } TWIHS_FILTR_Type; 760 #endif 761 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 762 763 #define TWIHS_FILTR_OFFSET (0x44) /**< (TWIHS_FILTR) Filter Register Offset */ 764 765 #define TWIHS_FILTR_FILT_Pos 0 /**< (TWIHS_FILTR) RX Digital Filter Position */ 766 #define TWIHS_FILTR_FILT_Msk (_U_(0x1) << TWIHS_FILTR_FILT_Pos) /**< (TWIHS_FILTR) RX Digital Filter Mask */ 767 #define TWIHS_FILTR_FILT TWIHS_FILTR_FILT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_FILT_Msk instead */ 768 #define TWIHS_FILTR_PADFEN_Pos 1 /**< (TWIHS_FILTR) PAD Filter Enable Position */ 769 #define TWIHS_FILTR_PADFEN_Msk (_U_(0x1) << TWIHS_FILTR_PADFEN_Pos) /**< (TWIHS_FILTR) PAD Filter Enable Mask */ 770 #define TWIHS_FILTR_PADFEN TWIHS_FILTR_PADFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFEN_Msk instead */ 771 #define TWIHS_FILTR_PADFCFG_Pos 2 /**< (TWIHS_FILTR) PAD Filter Config Position */ 772 #define TWIHS_FILTR_PADFCFG_Msk (_U_(0x1) << TWIHS_FILTR_PADFCFG_Pos) /**< (TWIHS_FILTR) PAD Filter Config Mask */ 773 #define TWIHS_FILTR_PADFCFG TWIHS_FILTR_PADFCFG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFCFG_Msk instead */ 774 #define TWIHS_FILTR_THRES_Pos 8 /**< (TWIHS_FILTR) Digital Filter Threshold Position */ 775 #define TWIHS_FILTR_THRES_Msk (_U_(0x7) << TWIHS_FILTR_THRES_Pos) /**< (TWIHS_FILTR) Digital Filter Threshold Mask */ 776 #define TWIHS_FILTR_THRES(value) (TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)) 777 #define TWIHS_FILTR_MASK _U_(0x707) /**< \deprecated (TWIHS_FILTR) Register MASK (Use TWIHS_FILTR_Msk instead) */ 778 #define TWIHS_FILTR_Msk _U_(0x707) /**< (TWIHS_FILTR) Register Mask */ 779 780 781 /* -------- TWIHS_SWMR : (TWIHS Offset: 0x4c) (R/W 32) SleepWalking Matching Register -------- */ 782 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 783 #if COMPONENT_TYPEDEF_STYLE == 'N' 784 typedef union { 785 struct { 786 uint32_t SADR1:7; /**< bit: 0..6 Slave Address 1 */ 787 uint32_t :1; /**< bit: 7 Reserved */ 788 uint32_t SADR2:7; /**< bit: 8..14 Slave Address 2 */ 789 uint32_t :1; /**< bit: 15 Reserved */ 790 uint32_t SADR3:7; /**< bit: 16..22 Slave Address 3 */ 791 uint32_t :1; /**< bit: 23 Reserved */ 792 uint32_t DATAM:8; /**< bit: 24..31 Data Match */ 793 } bit; /**< Structure used for bit access */ 794 uint32_t reg; /**< Type used for register access */ 795 } TWIHS_SWMR_Type; 796 #endif 797 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 798 799 #define TWIHS_SWMR_OFFSET (0x4C) /**< (TWIHS_SWMR) SleepWalking Matching Register Offset */ 800 801 #define TWIHS_SWMR_SADR1_Pos 0 /**< (TWIHS_SWMR) Slave Address 1 Position */ 802 #define TWIHS_SWMR_SADR1_Msk (_U_(0x7F) << TWIHS_SWMR_SADR1_Pos) /**< (TWIHS_SWMR) Slave Address 1 Mask */ 803 #define TWIHS_SWMR_SADR1(value) (TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)) 804 #define TWIHS_SWMR_SADR2_Pos 8 /**< (TWIHS_SWMR) Slave Address 2 Position */ 805 #define TWIHS_SWMR_SADR2_Msk (_U_(0x7F) << TWIHS_SWMR_SADR2_Pos) /**< (TWIHS_SWMR) Slave Address 2 Mask */ 806 #define TWIHS_SWMR_SADR2(value) (TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)) 807 #define TWIHS_SWMR_SADR3_Pos 16 /**< (TWIHS_SWMR) Slave Address 3 Position */ 808 #define TWIHS_SWMR_SADR3_Msk (_U_(0x7F) << TWIHS_SWMR_SADR3_Pos) /**< (TWIHS_SWMR) Slave Address 3 Mask */ 809 #define TWIHS_SWMR_SADR3(value) (TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)) 810 #define TWIHS_SWMR_DATAM_Pos 24 /**< (TWIHS_SWMR) Data Match Position */ 811 #define TWIHS_SWMR_DATAM_Msk (_U_(0xFF) << TWIHS_SWMR_DATAM_Pos) /**< (TWIHS_SWMR) Data Match Mask */ 812 #define TWIHS_SWMR_DATAM(value) (TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)) 813 #define TWIHS_SWMR_MASK _U_(0xFF7F7F7F) /**< \deprecated (TWIHS_SWMR) Register MASK (Use TWIHS_SWMR_Msk instead) */ 814 #define TWIHS_SWMR_Msk _U_(0xFF7F7F7F) /**< (TWIHS_SWMR) Register Mask */ 815 816 817 /* -------- TWIHS_DR : (TWIHS Offset: 0xd0) (R/ 32) Debug Register -------- */ 818 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 819 #if COMPONENT_TYPEDEF_STYLE == 'N' 820 typedef union { 821 struct { 822 uint32_t SWEN:1; /**< bit: 0 SleepWalking Enable */ 823 uint32_t CLKRQ:1; /**< bit: 1 Clock Request */ 824 uint32_t SWMATCH:1; /**< bit: 2 SleepWalking Match */ 825 uint32_t TRP:1; /**< bit: 3 Transfer Pending */ 826 uint32_t :28; /**< bit: 4..31 Reserved */ 827 } bit; /**< Structure used for bit access */ 828 uint32_t reg; /**< Type used for register access */ 829 } TWIHS_DR_Type; 830 #endif 831 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 832 833 #define TWIHS_DR_OFFSET (0xD0) /**< (TWIHS_DR) Debug Register Offset */ 834 835 #define TWIHS_DR_SWEN_Pos 0 /**< (TWIHS_DR) SleepWalking Enable Position */ 836 #define TWIHS_DR_SWEN_Msk (_U_(0x1) << TWIHS_DR_SWEN_Pos) /**< (TWIHS_DR) SleepWalking Enable Mask */ 837 #define TWIHS_DR_SWEN TWIHS_DR_SWEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_DR_SWEN_Msk instead */ 838 #define TWIHS_DR_CLKRQ_Pos 1 /**< (TWIHS_DR) Clock Request Position */ 839 #define TWIHS_DR_CLKRQ_Msk (_U_(0x1) << TWIHS_DR_CLKRQ_Pos) /**< (TWIHS_DR) Clock Request Mask */ 840 #define TWIHS_DR_CLKRQ TWIHS_DR_CLKRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_DR_CLKRQ_Msk instead */ 841 #define TWIHS_DR_SWMATCH_Pos 2 /**< (TWIHS_DR) SleepWalking Match Position */ 842 #define TWIHS_DR_SWMATCH_Msk (_U_(0x1) << TWIHS_DR_SWMATCH_Pos) /**< (TWIHS_DR) SleepWalking Match Mask */ 843 #define TWIHS_DR_SWMATCH TWIHS_DR_SWMATCH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_DR_SWMATCH_Msk instead */ 844 #define TWIHS_DR_TRP_Pos 3 /**< (TWIHS_DR) Transfer Pending Position */ 845 #define TWIHS_DR_TRP_Msk (_U_(0x1) << TWIHS_DR_TRP_Pos) /**< (TWIHS_DR) Transfer Pending Mask */ 846 #define TWIHS_DR_TRP TWIHS_DR_TRP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_DR_TRP_Msk instead */ 847 #define TWIHS_DR_MASK _U_(0x0F) /**< \deprecated (TWIHS_DR) Register MASK (Use TWIHS_DR_Msk instead) */ 848 #define TWIHS_DR_Msk _U_(0x0F) /**< (TWIHS_DR) Register Mask */ 849 850 851 /* -------- TWIHS_WPMR : (TWIHS Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 852 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 853 #if COMPONENT_TYPEDEF_STYLE == 'N' 854 typedef union { 855 struct { 856 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 857 uint32_t :7; /**< bit: 1..7 Reserved */ 858 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 859 } bit; /**< Structure used for bit access */ 860 uint32_t reg; /**< Type used for register access */ 861 } TWIHS_WPMR_Type; 862 #endif 863 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 864 865 #define TWIHS_WPMR_OFFSET (0xE4) /**< (TWIHS_WPMR) Write Protection Mode Register Offset */ 866 867 #define TWIHS_WPMR_WPEN_Pos 0 /**< (TWIHS_WPMR) Write Protection Enable Position */ 868 #define TWIHS_WPMR_WPEN_Msk (_U_(0x1) << TWIHS_WPMR_WPEN_Pos) /**< (TWIHS_WPMR) Write Protection Enable Mask */ 869 #define TWIHS_WPMR_WPEN TWIHS_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPMR_WPEN_Msk instead */ 870 #define TWIHS_WPMR_WPKEY_Pos 8 /**< (TWIHS_WPMR) Write Protection Key Position */ 871 #define TWIHS_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Write Protection Key Mask */ 872 #define TWIHS_WPMR_WPKEY(value) (TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)) 873 #define TWIHS_WPMR_WPKEY_PASSWD_Val _U_(0x545749) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ 874 #define TWIHS_WPMR_WPKEY_PASSWD (TWIHS_WPMR_WPKEY_PASSWD_Val << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 Position */ 875 #define TWIHS_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPMR) Register MASK (Use TWIHS_WPMR_Msk instead) */ 876 #define TWIHS_WPMR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPMR) Register Mask */ 877 878 879 /* -------- TWIHS_WPSR : (TWIHS Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 880 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 881 #if COMPONENT_TYPEDEF_STYLE == 'N' 882 typedef union { 883 struct { 884 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 885 uint32_t :7; /**< bit: 1..7 Reserved */ 886 uint32_t WPVSRC:24; /**< bit: 8..31 Write Protection Violation Source */ 887 } bit; /**< Structure used for bit access */ 888 uint32_t reg; /**< Type used for register access */ 889 } TWIHS_WPSR_Type; 890 #endif 891 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 892 893 #define TWIHS_WPSR_OFFSET (0xE8) /**< (TWIHS_WPSR) Write Protection Status Register Offset */ 894 895 #define TWIHS_WPSR_WPVS_Pos 0 /**< (TWIHS_WPSR) Write Protection Violation Status Position */ 896 #define TWIHS_WPSR_WPVS_Msk (_U_(0x1) << TWIHS_WPSR_WPVS_Pos) /**< (TWIHS_WPSR) Write Protection Violation Status Mask */ 897 #define TWIHS_WPSR_WPVS TWIHS_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPSR_WPVS_Msk instead */ 898 #define TWIHS_WPSR_WPVSRC_Pos 8 /**< (TWIHS_WPSR) Write Protection Violation Source Position */ 899 #define TWIHS_WPSR_WPVSRC_Msk (_U_(0xFFFFFF) << TWIHS_WPSR_WPVSRC_Pos) /**< (TWIHS_WPSR) Write Protection Violation Source Mask */ 900 #define TWIHS_WPSR_WPVSRC(value) (TWIHS_WPSR_WPVSRC_Msk & ((value) << TWIHS_WPSR_WPVSRC_Pos)) 901 #define TWIHS_WPSR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPSR) Register MASK (Use TWIHS_WPSR_Msk instead) */ 902 #define TWIHS_WPSR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPSR) Register Mask */ 903 904 905 /* -------- TWIHS_VER : (TWIHS Offset: 0xfc) (R/ 32) Version Register -------- */ 906 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 907 #if COMPONENT_TYPEDEF_STYLE == 'N' 908 typedef union { 909 struct { 910 uint32_t VERSION:12; /**< bit: 0..11 Version of the Hardware Module */ 911 uint32_t :4; /**< bit: 12..15 Reserved */ 912 uint32_t MFN:3; /**< bit: 16..18 Metal Fix Number */ 913 uint32_t :13; /**< bit: 19..31 Reserved */ 914 } bit; /**< Structure used for bit access */ 915 uint32_t reg; /**< Type used for register access */ 916 } TWIHS_VER_Type; 917 #endif 918 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 919 920 #define TWIHS_VER_OFFSET (0xFC) /**< (TWIHS_VER) Version Register Offset */ 921 922 #define TWIHS_VER_VERSION_Pos 0 /**< (TWIHS_VER) Version of the Hardware Module Position */ 923 #define TWIHS_VER_VERSION_Msk (_U_(0xFFF) << TWIHS_VER_VERSION_Pos) /**< (TWIHS_VER) Version of the Hardware Module Mask */ 924 #define TWIHS_VER_VERSION(value) (TWIHS_VER_VERSION_Msk & ((value) << TWIHS_VER_VERSION_Pos)) 925 #define TWIHS_VER_MFN_Pos 16 /**< (TWIHS_VER) Metal Fix Number Position */ 926 #define TWIHS_VER_MFN_Msk (_U_(0x7) << TWIHS_VER_MFN_Pos) /**< (TWIHS_VER) Metal Fix Number Mask */ 927 #define TWIHS_VER_MFN(value) (TWIHS_VER_MFN_Msk & ((value) << TWIHS_VER_MFN_Pos)) 928 #define TWIHS_VER_MASK _U_(0x70FFF) /**< \deprecated (TWIHS_VER) Register MASK (Use TWIHS_VER_Msk instead) */ 929 #define TWIHS_VER_Msk _U_(0x70FFF) /**< (TWIHS_VER) Register Mask */ 930 931 932 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 933 #if COMPONENT_TYPEDEF_STYLE == 'R' 934 /** \brief TWIHS hardware registers */ 935 typedef struct { 936 __O uint32_t TWIHS_CR; /**< (TWIHS Offset: 0x00) Control Register */ 937 __IO uint32_t TWIHS_MMR; /**< (TWIHS Offset: 0x04) Master Mode Register */ 938 __IO uint32_t TWIHS_SMR; /**< (TWIHS Offset: 0x08) Slave Mode Register */ 939 __IO uint32_t TWIHS_IADR; /**< (TWIHS Offset: 0x0C) Internal Address Register */ 940 __IO uint32_t TWIHS_CWGR; /**< (TWIHS Offset: 0x10) Clock Waveform Generator Register */ 941 __I uint8_t Reserved1[12]; 942 __I uint32_t TWIHS_SR; /**< (TWIHS Offset: 0x20) Status Register */ 943 __O uint32_t TWIHS_IER; /**< (TWIHS Offset: 0x24) Interrupt Enable Register */ 944 __O uint32_t TWIHS_IDR; /**< (TWIHS Offset: 0x28) Interrupt Disable Register */ 945 __I uint32_t TWIHS_IMR; /**< (TWIHS Offset: 0x2C) Interrupt Mask Register */ 946 __I uint32_t TWIHS_RHR; /**< (TWIHS Offset: 0x30) Receive Holding Register */ 947 __O uint32_t TWIHS_THR; /**< (TWIHS Offset: 0x34) Transmit Holding Register */ 948 __IO uint32_t TWIHS_SMBTR; /**< (TWIHS Offset: 0x38) SMBus Timing Register */ 949 __I uint8_t Reserved2[8]; 950 __IO uint32_t TWIHS_FILTR; /**< (TWIHS Offset: 0x44) Filter Register */ 951 __I uint8_t Reserved3[4]; 952 __IO uint32_t TWIHS_SWMR; /**< (TWIHS Offset: 0x4C) SleepWalking Matching Register */ 953 __I uint8_t Reserved4[128]; 954 __I uint32_t TWIHS_DR; /**< (TWIHS Offset: 0xD0) Debug Register */ 955 __I uint8_t Reserved5[16]; 956 __IO uint32_t TWIHS_WPMR; /**< (TWIHS Offset: 0xE4) Write Protection Mode Register */ 957 __I uint32_t TWIHS_WPSR; /**< (TWIHS Offset: 0xE8) Write Protection Status Register */ 958 __I uint8_t Reserved6[16]; 959 __I uint32_t TWIHS_VER; /**< (TWIHS Offset: 0xFC) Version Register */ 960 } Twihs; 961 962 #elif COMPONENT_TYPEDEF_STYLE == 'N' 963 /** \brief TWIHS hardware registers */ 964 typedef struct { 965 __O TWIHS_CR_Type TWIHS_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 966 __IO TWIHS_MMR_Type TWIHS_MMR; /**< Offset: 0x04 (R/W 32) Master Mode Register */ 967 __IO TWIHS_SMR_Type TWIHS_SMR; /**< Offset: 0x08 (R/W 32) Slave Mode Register */ 968 __IO TWIHS_IADR_Type TWIHS_IADR; /**< Offset: 0x0C (R/W 32) Internal Address Register */ 969 __IO TWIHS_CWGR_Type TWIHS_CWGR; /**< Offset: 0x10 (R/W 32) Clock Waveform Generator Register */ 970 __I uint8_t Reserved1[12]; 971 __I TWIHS_SR_Type TWIHS_SR; /**< Offset: 0x20 (R/ 32) Status Register */ 972 __O TWIHS_IER_Type TWIHS_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ 973 __O TWIHS_IDR_Type TWIHS_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ 974 __I TWIHS_IMR_Type TWIHS_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ 975 __I TWIHS_RHR_Type TWIHS_RHR; /**< Offset: 0x30 (R/ 32) Receive Holding Register */ 976 __O TWIHS_THR_Type TWIHS_THR; /**< Offset: 0x34 ( /W 32) Transmit Holding Register */ 977 __IO TWIHS_SMBTR_Type TWIHS_SMBTR; /**< Offset: 0x38 (R/W 32) SMBus Timing Register */ 978 __I uint8_t Reserved2[8]; 979 __IO TWIHS_FILTR_Type TWIHS_FILTR; /**< Offset: 0x44 (R/W 32) Filter Register */ 980 __I uint8_t Reserved3[4]; 981 __IO TWIHS_SWMR_Type TWIHS_SWMR; /**< Offset: 0x4C (R/W 32) SleepWalking Matching Register */ 982 __I uint8_t Reserved4[128]; 983 __I TWIHS_DR_Type TWIHS_DR; /**< Offset: 0xD0 (R/ 32) Debug Register */ 984 __I uint8_t Reserved5[16]; 985 __IO TWIHS_WPMR_Type TWIHS_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 986 __I TWIHS_WPSR_Type TWIHS_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 987 __I uint8_t Reserved6[16]; 988 __I TWIHS_VER_Type TWIHS_VER; /**< Offset: 0xFC (R/ 32) Version Register */ 989 } Twihs; 990 991 #else /* COMPONENT_TYPEDEF_STYLE */ 992 #error Unknown component typedef style 993 #endif /* COMPONENT_TYPEDEF_STYLE */ 994 995 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 996 /** @} end of Two-wire Interface High Speed */ 997 998 #endif /* _SAMV71_TWIHS_COMPONENT_H_ */ 999
